Display device and manufacturing method thereof

This application claims priority to, and the benefit of, Korean Patent Application No. 10-2009-0107651 filed in the Korean Intellectual Property Office on Dec. 9, 2009, the entire contents of which are incorporated herein by reference.

(a) Field of the Invention

The present invention relates generally to flat panel displays. More specifically, the invention relates to touch-screen flat panel displays.

(b) Description of the Related Art

Liquid crystal displays (LCDs) have found recent application in touch-sensitive devices, such as touch screens. However, it has historically been difficult to develop reliable such displays. Ongoing efforts thus exist to increase the reliability of LCD touch-sensitive devices. The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention. It may thus contain information not in the prior art.

The present invention can reduce the number of photolithography processes for manufacturing an infrared ray sensing transistor, a visible ray sensing transistor, and a readout transistor.

A display device according to an exemplary embodiment of the present invention includes: a lower panel including a lower substrate and a pixel transistor disposed on the lower substrate; and an upper panel facing the lower panel, the upper panel including an upper substrate, an infrared sensing transistor disposed on the upper substrate, and a readout transistor connected to the infrared ray sensing transistor and transmitting a detection signal responsive to the sensing transistor. The infrared sensing transistor includes a source semiconductor layer and a drain semiconductor layer separated from each other on the upper substrate, a source electrode and a drain electrode respectively disposed on the source semiconductor layer and the drain semiconductor layer, an upper semiconductor layer disposed on the source electrode and the drain electrode, and a gate electrode overlapping the first upper semiconductor layer. The source semiconductor layer and the drain semiconductor layer each have an upper surface facing the upper substrate, a lower surface opposite the upper surface, and a side surface extending between the upper and lower surfaces, the upper semiconductor layer contacting the side surfaces of the source semiconductor layer and the drain semiconductor layer.

The display device can also include a blocking insulating layer having an upper surface facing the upper substrate, and a lower surface facing the first source lower semiconductor layer and the first drain lower semiconductor layer. A channel of the upper semiconductor layer is disposed between the source electrode and the drain electrode, and contacts the blocking insulating layer.

The readout transistor may include a lower gate electrode disposed on the upper substrate, a lower semiconductor layer disposed on and overlapping the lower gate electrode, a source electrode and a drain electrode each positioned on the lower semiconductor layer, a source semiconductor layer and a drain semiconductor layer respectively disposed on the source electrode and the drain electrode and separated from each other, and an upper gate electrode overlapping the lower semiconductor layer.

The upper semiconductor layer of the infrared sensing transistor, and the source and drain semiconductor layers of the readout transistor each include amorphous silicon germanium. Also, the source and drain semiconductor layers of the infrared sensing transistor, and the lower semiconductor layer of the readout transistor each include amorphous silicon.

A light blocking film may also be included, where the light blocking film has an upper surface facing the upper substrate and a lower surface opposite the upper surface, the lower surface facing the source semiconductor layer and drain semiconductor layer.

A lower ohmic contact layer can formed between the source semiconductor layer and the source electrode, and between the drain semiconductor layer and the drain electrode. An upper ohmic contact layer can be formed between the source electrode and the upper semiconductor layer, and between the drain electrode and the upper semiconductor layer.

A readout transistor can include a lower semiconductor layer disposed on the upper substrate, a source electrode and a drain electrode each positioned on the lower semiconductor layer, and a source semiconductor layer and a drain semiconductor layer respectively disposed on the source electrode and the drain electrode and separated from each other. A lower ohmic contact layer can be formed between the lower semiconductor layer of the readout transistor and the source electrode of the readout transistor, and between the lower semiconductor layer of the readout transistor and the drain electrode of the readout transistor. Also, an upper ohmic contact layer can be formed between the source electrode of the readout transistor and the source semiconductor layer of the readout transistor, and between the drain electrode of the readout transistor and the drain semiconductor layer of the readout transistor.

Further, a display device according to another exemplary embodiment of the present invention includes: a lower panel including a lower substrate and a pixel transistor disposed on the lower substrate; and an upper panel facing the lower panel, and including an upper substrate, an infrared ray sensing transistor disposed on the upper substrate, and a readout transistor connected to the infrared ray sensing transistor and transmitting a detection signal, wherein the infrared ray sensing transistor includes a first lower semiconductor layer disposed on the upper substrate, a first source electrode and a first drain electrode each disposed on the first lower semiconductor layer, a first upper semiconductor layer disposed on the first source electrode and the first drain electrode, a first gate electrode overlapping the first upper semiconductor layer, and a separating layer disposed between the first lower semiconductor layer and a channel of the first upper semiconductor layer, the channel of the first semiconductor layer positioned generally between the first source electrode and first drain electrode.

The separating layer may include a nitrogen oxide.

The readout transistor may include a second lower gate electrode disposed on the upper substrate, a second lower semiconductor layer disposed on the second gate electrode and overlapping the second gate electrode, a second source electrode and a second drain electrode each positioned on the second lower semiconductor layer, a second source upper semiconductor layer and a second drain upper semiconductor layer respectively disposed on the second source electrode and the second drain electrode and separated from each other, and a second upper gate electrode overlapping the second lower semiconductor layer.

The first upper semiconductor layer, the second source upper semiconductor layer, and the second drain upper semiconductor layer may each include amorphous silicon germanium, and the first lower semiconductor layer and the second lower semiconductor layer may each include amorphous silicon.

A light blocking film disposed between upper substrate and the first lower semiconductor layer, and under the second lower gate electrode, may be further included.

A first lower ohmic contact layer having a first surface facing the first lower semiconductor layer and the first source electrode, and a second surface facing the first lower semiconductor layer and the first drain electrode, and a first upper ohmic contact layer having a first surface facing the first source electrode and the first upper semiconductor layer, and a second surface facing the first drain electrode and the first upper semiconductor layer, may be further included.

A second lower ohmic contact layer having a first surface facing the second lower semiconductor layer and the second source electrode, and a second surface facing the second lower semiconductor layer and the second drain electrode, and a second upper ohmic contact layer having a first surface facing the second source electrode and the second source upper semiconductor layer, and a second surface facing the second drain electrode and the second source upper semiconductor layer, may be further included.

A method for manufacturing a display device according to an exemplary embodiment of the present invention includes: sequentially forming a lower semiconductor material and a conductive layer on a substrate; etching the lower semiconductor material and the conductive layer to form a first source lower semiconductor layer of an infrared ray sensing transistor, a first drain lower semiconductor layer of the infrared ray sensing transistor, a first source electrode of the infrared ray sensing transistor, a first drain electrode of the infrared ray sensing transistor, a second lower semiconductor layer of a readout transistor, and a conductive pattern of the readout transistor; forming an upper semiconductor material on the first source electrode, the first drain electrode, and the conductive pattern; etching the upper semiconductor material and the conductive pattern to form a first upper semiconductor layer of the infrared ray sensing transistor, a second source electrode of the readout transistor, a second drain electrode of the readout transistor, a second source upper semiconductor layer of the readout transistor, and a second drain upper semiconductor layer of the readout transistor; and forming a gate insulating layer on the first upper semiconductor layer, the second source upper semiconductor layer, the second drain upper semiconductor layer, and the second lower semiconductor layer, wherein the first source lower semiconductor layer and the first drain lower semiconductor layer of the infrared ray sensing transistor are separated from each other, and the second source upper semiconductor layer and the second drain upper semiconductor layer of the readout transistor are separated from each other.

The gate insulating layer may be formed on the second lower semiconductor layer between the second source electrode and the second drain electrode.

Forming a lower ohmic contact material between the lower semiconductor material and the conductive layer, and forming an upper ohmic contact material on the conductive layer, may be further included.

Before forming the lower semiconductor material, a light blocking material and a gate conductive layer are sequentially formed, the light blocking material and the gate conductive layer are etched to form a light blocking film and a second lower gate electrode of the readout transistor, and a blocking insulating layer is formed on the substrate, the light blocking film, and the second lower gate electrode.

The etching the light blocking material may further comprise forming the light blocking film and the second lower gate electrode of the readout transistor by etching the light blocking material and the gate conductive layer with a first photosensitive film pattern positioned on the gate conductive layer, the first photosensitive film pattern including a first portion and a second portion that is thinner than the first portion.

The method may also include forming a first upper gate electrode on the gate insulating layer, the first upper gate electrode overlapping a channel of the first upper semiconductor layer, and forming a second upper gate electrode on the gate insulating layer, the second upper gate electrode overlapping a channel of the second lower semiconductor layer on the gate insulating layer.

The first source lower semiconductor layer and the first drain lower semiconductor layer may be separated from each other.

The first source lower semiconductor layer and the first drain lower semiconductor layer may be separated from each other.

A method for manufacturing a display device according to another exemplary embodiment of the present invention includes: sequentially forming a lower semiconductor material and a conductive layer on a substrate; etching the lower semiconductor material and the conductive layer to form a first source lower semiconductor layer, a first drain lower semiconductor layer, a first lower semiconductor layer, a first source electrode, and a first drain electrode of an infrared ray sensing transistor, and a second lower semiconductor layer and a data conductive pattern of a readout transistor; forming a separating layer on a portion of the first lower semiconductor layer that is exposed between the first source electrode and the first drain electrode; forming an upper semiconductor material on the first source electrode, the first drain electrode, the separating layer, and the data conductive pattern; etching the upper semiconductor material and the data conductive pattern to form a first upper semiconductor layer of the infrared ray sensing transistor, and a second source electrode, a second drain electrode, a second source upper semiconductor layer, and a second drain upper semiconductor layer of a readout transistor; and forming a gate insulating layer on the first upper semiconductor layer, the second source upper semiconductor layer, the second drain upper semiconductor layer, and the second lower semiconductor layer, wherein the second source upper semiconductor layer and the second drain upper semiconductor layer of the readout transistor are separated from each other.

The gate insulating layer may be formed on a portion of the second lower semiconductor layer that is exposed between the second source electrode and the second drain electrode.

The separating layer may include a nitrogen oxide layer formed through a plasma treatment.

Forming a lower ohmic contact material between the lower semiconductor material and the conductive layer, and forming an upper ohmic contact material on the conductive layer, may be further included.

Before forming the lower semiconductor material, a light blocking material and a gate conductive layer are sequentially formed, the light blocking material and the gate conductive layer are etched to form a light blocking film and a second lower gate electrode of the readout transistor, and a blocking insulating layer is formed on the substrate, the light blocking film, and the second lower gate electrode.

The etching the light blocking material may further comprises=forming the light blocking film and the second lower gate electrode of the readout transistor by etching the light blocking material and the gate conductive layer with a first photosensitive film pattern positioned on the gate conductive layer, the first photosensitive film pattern including a first portion and a second portion that is thinner than the first portion.

The etching the lower semiconductor material may further comprise forming the first lower semiconductor layer of the infrared ray sensing transistor, the first source electrode, the first drain electrode, and the second lower semiconductor layer of the readout transistor, and the data conductive pattern by etching the lower semiconductor material and the data conductive layer with a second photosensitive film pattern positioned on the conductive layer, the second photosensitive film pattern including a first portion and a second portion that is thinner than the first portion.

The method may also include forming a first upper gate electrode on the gate insulating layer, the first upper gate electrode overlapping a channel of the first upper semiconductor layer, and forming a second upper gate electrode on the gate insulating layer, the second upper gate electrode overlapping a channel of the second lower semiconductor layer.

The second source upper semiconductor layer and the second drain upper semiconductor layer may be separated from each other.

According to an exemplary embodiment of the present invention, the infrared ray sensing transistor may have a semiconductor layer made of amorphous silicon germanium, and the visible ray sensing transistor and the readout transistor may have a semiconductor layer made of amorphous silicon, so as to be formed through fewer photolithography processes, saving manufacturing time and expense.

FIG. 1 is a cross-sectional view of an upper panel of a display device according to an exemplary embodiment of the present invention.

FIG. 2 to FIG. 8 are cross-sectional views sequentially showing a manufacturing method for the display device shown in FIG. 1 .

FIG. 9 is a cross-sectional view of a display device constructed according to an exemplary embodiment of the present invention.

FIG. 10 is a view explaining a method for sensing an object by using the display device of FIG. 9 .

FIG. 11 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention.

FIG. 12 to FIG. 14 are cross-sectional views sequentially showing an exemplary manufacturing method for the liquid crystal display shown in FIG. 11 .

Like reference numerals refer to corresponding parts throughout the drawings. Also, it is understood that the depictions in the figures are diagrammatic and not necessarily to scale.

Exemplary embodiments of the present invention will be hereinafter described in detail with reference to the accompanying drawings. The structural shapes, sizes, ratios, numbers, etc. are schematically illustrated in the accompanying drawings such that they may be altered more or less. The drawings are shown from the viewpoint of observation such that the direction or location of explaining the drawings may be variously changed depending upon the position of the observer. Even when reference is made to different elements, like reference numerals may be used to designate those elements. When the terms “include,” “have,” “consist of,” or the like are used, the relevant subject may include other parts unless the term “only” is used to define the contents thereof. When explanation is made by way of a singular term, it may be interpreted in a plural manner as well as in a singular manner. Even when the numerical values, shapes, size comparisons, positional relations, etc. are not explained with the adverb “about” or “substantially,” they may be so interpreted to include the common error ranges. Even when the terms of “after,” “before,” “and,” “here,” “subsequently,” or the like are introduced, they are not meant to define temporal locations. The terms “the first,” “the second,” . . . , etc. are used only for convenience in distinction selectively, commutatively, or repeatedly, and are not meant to be read in any defined manners. It will be understood that when an element is referred to as being “on,” “over,” “above,” “below,” or “beside” another element, it can be directly on the other element or one or more intervening elements may also be present. When the connective “or” is used to connect two elements, it is meant to indicate the respective elements and a combination thereof, but when the quantifier “any one of” is attached to the connective, it is meant to indicate only the respective elements.

A display device according to an exemplary embodiment of the present invention is now described with reference to FIG. 1 . FIG. 1 shows a liquid crystal display. However, one of ordinary skill in the art will observe that the methods and approaches of the present exemplary embodiment may be applied to various display devices besides LCDs.

FIG. 1 is a cross-sectional view of an upper panel of a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1 , an upper panel 200 includes an upper substrate 210 made of transparent glass or plastic, and sensing transistors TrI and TrV. The sensing transistors TrI and TrV may include at least one infrared ray sensing transistor TrI and at least one visible ray sensing transistor TrV. The infrared ray sensing transistor TrI and the visible ray sensing transistor TrV may be generally uniformly distributed upon the whole upper panel 200 , so as to sense infrared rays and visible light on the whole region of the upper panel 200 . However, the invention includes any distribution of transistors TrV and TrI. As examples, the infrared ray sensing transistor TrI and the visible ray sensing transistor TrV may be placed in alternating manner, may be arranged according to any predetermined ratio, or may be placed in no particular manner (e.g., randomly or pseudorandomly placed). In the present exemplary embodiment, the infrared ray sensing transistor TrI and the visible ray sensing transistor TrV are alternately arranged.

The upper panel 200 may further include a readout transistor TrC that connects to the infrared ray sensing transistor TrI and the visible light sensing transistor TrV, and that transmits a detected signal. Here, the readout transistor TrC may be disposed relatively close to the sensing transistors TrI and TrV.

The infrared ray sensing transistor TrI, visible ray sensing transistor TrV, and the readout transistor TrC may each be positioned on the upper substrate 210 .

In detail, the infrared ray sensing transistor TrI may include lower semiconductor layers 253 Ip and 255 Ip, lower ohmic contact layers 263 Ip and 265 Ip, a source electrode 273 I, a drain electrode 275 I, upper ohmic contact layers 263 Iq and 265 Iq, an upper semiconductor layer 254 Iq, a gate insulating layer 240 , and an upper gate electrode 224 I.

A light blocking film 211 I is disposed on the upper substrate 210 , and at least partially overlaps the upper semiconductor layer 254 Iq. The light blocking film 211 I prevents the upper semiconductor layer 254 Iq from being exposed to visible rays. Accordingly, the light blocking film 211 I may include a material that blocks visible rays incident on the film 211 I from outside the liquid crystal display. For example, the light blocking film 211 I may include an organic material or amorphous silicon including black pigments.

The light blocking film 211 I blocks visible rays that are incident to the liquid crystal display from external sources (e.g., ambient, or environmental, light). This improves the signal-to-noise ratio (SNR) of the display, and also improves the sensitivity of the upper semiconductor layer 254 Iq (which can include amorphous silicon germanium or amorphous germanium) to infrared radiation by reducing the influence of visible rays.

A blocking insulating layer 230 , made of an insulating material such as silicon nitride, is formed on the upper substrate 210 and the light blocking film 211 I. It is preferable that the thickness of the blocking insulating layer 230 be in the range of about 3000 Å to about 10,000 Å. When the thickness of the blocking insulating layer 230 is less than about 3000 Å, the minute charges accumulated in the light blocking film 211 I may affect the sensitivity of the upper semiconductor layer 254 Iq, and when the thickness of the blocking insulating layer 230 is larger than 10,000 Å, the thickness of the transistor may not be thin. A lower gate electrode (not shown) may be disposed on a portion of the light blocking film 211 I, and may be connected to the upper gate electrode 224 I. In this case, a light blocking film 211 I that contacts the lower gate electrode (not shown) helps to reduce the number of operational errors of the transistor caused by the light blocking film 211 I itself. That is, when the light blocking film 211 I is separated from the lower gate electrode (not shown), the light blocking film 211 I absorbs external light, thereby generating minute charges within. If not dissipated, these charges can influence the operation of the transistor. Accordingly, the light blocking film 211 I is connected to the upper gate electrode 224 I through the lower gate electrode (not shown) so that the gate voltage is applied to the light blocking film 211 I, clearing the accumulated minute charges and thereby reducing operation errors caused by the light blocking film 211 I.

The channels of the lower semiconductor layers 253 Ip and 255 Ip and the upper semiconductor layer 254 Iq are disposed on the blocking insulating layer 230 . Also, the upper semiconductor layer 254 Iq contacts the side surface of the lower semiconductor layers 253 Ip and 255 Ip. The lower semiconductor layers 253 Ip and 255 Ip may include amorphous silicon, and the upper semiconductor layer 254 Iq may include amorphous silicon germanium or amorphous germanium. When the upper semiconductor layer 254 Iq is made of amorphous silicon germanium or amorphous germanium, the resulting infrared ray sensing transistor TrI has excellent sensitivity. It is preferable that the thickness of the semiconductor layer 254 I is in the range of about 3000 Å to about 10,000 Å. When it is less than about 3000 Å, the infrared ray sensitivity is decreased, when it is more than 10000 Å, the transistor may undesirably large.

The lower semiconductor layers 253 Ip and 255 Ip are divided into a source lower semiconductor layer 253 Ip and a drain lower semiconductor layer 255 Ip such that the current can not flow through the lower semiconductor layers 253 Ip and 255 Ip when the gate voltage is appled to the upper gate electrode 224 I, and noise due to the current may be prevented. Also, the lower semiconductor layers 253 Ip and 255 Ip help block the visible-light rays that are incident to the upper semiconductor layer 254 Iq from backlight unit 910 , thereby improving signal-to-noise ratio (SNR), and improving the sensitivity of the upper semiconductor layer 254 Iq to infrared rays region by reducing the influence of visible rays.

The lower ohmic contact layers 263 Ip and 265 Ip may be disposed on the lower semiconductor layers 253 Ip and 255 Ip. The source electrode 273 I may be disposed on the lower ohmic contact layer 263 Ip, and the drain electrode 275 I may be disposed on the lower ohmic contact layer 265 Ip and separated from the source electrode 273 I.

The upper ohmic contact layer 263 Iq may be disposed on the source electrode 273 I, and the upper ohmic contact layer 265 Iq may be disposed on the drain electrode 275 I.

The upper semiconductor layer 254 Iq may be disposed on the exposed blocking insulating layer 230 between the upper ohmic contact layers 263 Iq and 265 Iq, and the source electrode 273 I and drain electrode 275 I.

The gate insulating layer 240 covers the upper semiconductor layer 254 Iq. It is preferable that the thickness of the gate insulating layer 240 is in the range of about 3000 Å to about 10,000 Å. When it is less than about 3000 Å, the transistor TrI is insufficiently sensitive to infrared rays, and when it is more than about 10000 Å, the transistor may be too large.

The upper gate electrode 224 I may be disposed to overlap the upper semiconductor layer 254 Iq on the gate insulating layer 240 . This upper gate electrode 224 I is opaque to both visible and infrared light, and largely prevents the infrared rays and the visible rays from the backlight unit 910 from being directly incident to the infrared ray sensing transistor TrI. Accordingly, the noise caused by the infrared rays and the visible rays directly incident to the infrared ray sensing transistor TrI from the backlight unit 910 may be substantially eliminated, improving the SNR, sensing margin, and infrared ray sensitivity of transistor TrI.

A passivation layer 280 protects the upper gate electrode 224 I, and is formed on the upper gate electrode 224 I and the gate insulating layer 240 . The passivation layer 280 may include an insulating material such as silicon nitride.

A portion of the source electrode 2731 and a portion of the capacitor data line (not shown) overlap each other, thereby forming an infrared ray sensing capacitor Ci, and the infrared rays may be detected through a change in the charge they impart in the infrared ray sensing capacitor Ci.

The readout transistor TrC transmits the input signal to the source electrode 273 C connected to a readout line (not shown), and may be connected to the source electrode 273 I of the infrared ray sensing transistor TrI through the drain electrode 275 C.

The readout transistor TrC may include a lower semiconductor layer 254 Cp, lower ohmic contact layers 263 Cp and 265 Cp, a source electrode 273 C, a drain electrode 275 C, upper ohmic contact layers 263 Cq and 265 Cq, upper semiconductor layers 253 Cq and 255 Cq, a gate insulating layer 240 , a lower gate electrode 221 C, and an upper gate electrode 224 C.

A light blocking film 211 C is disposed on the upper substrate 210 , the lower gate electrode 221 C is disposed on the light blocking film 211 C, and the lower gate electrode 221 C overlaps the lower semiconductor layer 254 Cp.

The light blocking film 211 C blocks infrared and visible rays from reaching the lower semiconductor layer 254 Cp, thereby improving the signal-to-noise ratio (SNR) of the transistor TrC.

The blocking insulating layer 230 is formed on the upper substrate 210 , thereby covering the lower gate electrode 211 C. The blocking insulating layer 230 can include an insulating material such as silicon nitride.

The lower semiconductor layer 254 Cp is disposed on the blocking insulating layer 230 , and may be made of amorphous silicon. It is preferable that the thickness of the semiconductor layer 254 C is in the range of about 500 Å to 3000 Å. When the thickness is less than about 500 Å, it is difficult to fabricate a uniform channel, and when the thickness is greater than about 3000 Å, the transistor may be too large.

The lower ohmic contact layers 263 Cp and 265 Cp may be disposed on the semiconductor layer 254 Cp. The source electrode 273 C may be disposed on the lower ohmic contact layer 263 Cp, and the drain electrode 275 C may be separated from the source electrode 273 C on the lower ohmic contact layer 265 Cp.

The upper ohmic contact layer 263 Cq may be disposed on the source electrode 273 C, and the upper ohmic contact layer 265 Cq may be disposed on the drain electrode 275 C.

The upper semiconductor layer 253 Cq may be disposed on the upper ohmic contact layer 263 Cq, and the upper semiconductor layer 255 Cq may be disposed on the upper ohmic contact layer 265 Cq. The upper semiconductor layers 253 Cq and 255 Cq may be formed of amorphous silicon germanium or amorphous germanium. However, the upper semiconductor layers 253 Cq and 255 Cq are divided into the source upper semiconductor layer 253 Cp and the drain upper semiconductor layer 255 Cp, and thereby they may not have the semiconductor characteristic that the current flows through the upper semiconductor layers 253 Cq and 255 Cq when the gate voltage is appled to the upper gate electrode 224 C. The gate insulating layer 240 may be disposed on the channel of the lower semiconductor layer 254 Cp and the upper semiconductor layers 253 Cq and 255 Cq.

The upper gate electrode 224 C may overlap the channel of the lower semiconductor layer 254 Cp on the gate insulating layer 240 . Accordingly, the upper gate electrode 224 C blocks infrared and visible rays from the backlight unit 910 , largely preventing them from falling incident upon the lower semiconductor layer 254 Cp. This helps eliminate that portion of noise that is caused by the irradiation of infrared rays and the visible rays from the backlight unit 910 upon the readout transistor TrC.

Also, similar to light blocking film 211 I above, light blocking film 211 C may connect to the lower gate electrode 221 C, which in turn may be connected to the upper gate electrode 224 C. In this manner, the gate voltage is applied to the light blocking film 211 C, clearing accumulated charge in film 211 C from incident light.

The passivation layer 280 protects the upper gate electrode 224 C, and is formed on the upper gate electrode 224 C and the gate insulating layer 240 .

On the other hand, the visible ray sensing transistor TrV is disposed on the upper substrate 210 , and the readout transistor TrC that is electrically connected to the visible ray sensing transistor TrV is disposed with the same layer as the visible ray sensing transistor TrV.

In detail, the visible ray sensing transistor TrV may include a lower semiconductor layer 254 Vp, lower ohmic contact layers 263 Vp and 265 Vp, a source electrode 273 V, a drain electrode 275 V, lower ohmic contact layers 263 Vq and 265 Vq, upper semiconductor layers 253 Vq and 255 Vq, the gate insulating layer 240 , and an upper gate electrode 224 V.

The blocking insulating layer 230 can include an insulating material such as silicon nitride, and is disposed on the upper substrate 210 . The lower semiconductor layer 254 Vp can be made of amorphous silicon, and is disposed on the blocking insulating layer 230 . It is preferable that the thickness of the lower semiconductor layer 254 Vp is in the range of about 500 Å to about 3000 Å. When the thickness is less than about 500 Å, it is difficult to fabricate uniform channels, and when the thickness is greater than about 3000 Å, the resulting transistor may excessively large.

The ohmic contact layers 263 Vp and 265 Vp may be disposed on the lower semiconductor layer 254 Vp. The source electrode 273 V may be disposed on the lower ohmic contact layer 263 Vp, and the drain electrode 275 V may be disposed on the lower ohmic contact layer 265 Vp and separated from the source electrode 273 V.

The upper ohmic contact layer 263 Vq may be disposed on the source electrode 273 V, and the upper ohmic contact layer 265 Vq may be disposed on the drain electrode 275 V.

The upper semiconductor layer 253 Vq may be disposed on the upper ohmic contact layer 263 Vq, and the upper semiconductor layer 255 Vq may be disposed on the upper ohmic contact layer 265 Vq. The upper semiconductor layers 253 Vq and 255 Vq may include amorphous silicon germanium or amorphous germanium. However, the upper semiconductor layers 253 Vq and 255 Vq are divided into a source upper semiconductor layer 253 Vp and a drain upper semiconductor layer 255 Vp such that they may not have the semiconductor characteristic that the current flows through the upper semiconductor layers 253 Vq and 255 Vq when the gate voltage is appled to the upper gate electrode 224 V. The gate insulating layer 240 may be disposed on the channel of the lower semiconductor layer 254 Vp and the upper semiconductor layers 253 Vq and 255 Vq.

The upper gate electrode 224 V may overlap the channel of the lower semiconductor layer 254 Vp on the gate insulating layer 240 . Accordingly, the upper gate electrode 224 V substantially blocks those infrared and visible rays incident to the lower semiconductor layer 254 Vp from the backlight unit 910 . This reduces noise in the transistor TrV caused by light from the backlight unit 910 .

The passivation layer 280 protecting the upper gate electrode 224 V is formed on the upper gate electrode 224 V and the gate insulating layer 240 .

The readout transistor TrC transmits the input signal to the source electrode 273 C connected to the readout line (not shown), and may be connected to the source electrode 273 V of the visible ray sensing transistor TrV through the drain electrode 275 C.

A portion of the source electrode 273 V overlaps a portion of the capacitor data line (not shown) thereby forming the visible ray sensing capacitor Cv, allowing visible rays to be sensed through a change they cause in the charge stored in the visible ray sensing capacitor Cv.

A light blocking member 310 may be formed on the passivation layer 280 covering the infrared ray sensing transistor TrI, the visible ray sensing transistor TrV, and the readout transistor TrC. The light blocking member 310 prevents the infrared rays and visible rays generated from the backlight unit 910 from being incident to the infrared ray sensing transistor TrI and the visible ray sensing transistor TrV, and prevents external light (both infrared and visible) from being incident to the pixel transistor TrP.

An overcoat 320 is formed on the light blocking member 310 . The overcoat 320 may be made of an organic layer for planarization. A common electrode 330 is formed on the overcoat 320 , and can be made of ITO or IZO.

As described above, the infrared ray sensing transistor including the amorphous silicon germanium is formed, and the visible ray sensing transistor and the readout transistor including the amorphous silicon are formed. Therefore, the present invention increases the reliability of LCD touch-sensitive devices in the dark environment.

FIG. 2 to FIG. 8 are cross-sectional views sequentially showing a method of manufacturing the display device shown in FIG. 1 . First, as shown in FIG. 2 , a light blocking material 2110 and a gate conductive layer 2210 are formed on a substrate 210 . The light blocking material 2110 can be made of any suitable material, such as an organic material or an amorphous silicon that includes black pigments. Next, a first photosensitive film pattern 1000 , including a first portion 1100 and a second portion 1200 having a thinner thickness than the first portion 1100 , is formed on the gate conductive layer 2210 .

Next, as shown in FIG. 3 , the light blocking material and the gate conductive layer are etched by using the first photosensitive film pattern 1000 as a mask, to form light blocking films 211 C and 211 V, as well as lower gate electrodes 221 C and 221 V. Next, the first photosensitive film pattern 1000 is etched back to remove the second portion 1200 , thereby exposing the lower gate electrode 221 V and reducing the thickness of the first portion 1100 so as to form a thinner third portion 1101 . Next, the exposed lower gate electrode 221 V is etched to expose the light blocking film 211 V. Next, the first photosensitive film pattern 1000 is removed.

Next, as shown in FIG. 4 , a blocking insulating layer 230 is formed. This blocking insulating layer 230 can be made of an insulating material such as silicon nitride, and covers the upper substrate 210 , the light blocking film 211 V, and the lower gate electrode 221 C. Next, a lower semiconductor material 250 p , a lower ohmic contact material 260 p , a data conductive layer 270 , and an upper ohmic contact material 260 q are sequentially formed on the blocking insulating layer 230 . Here, the lower semiconductor material 250 C may be made of amorphous silicon. The second photosensitive film pattern 2000 is then formed on the upper ohmic contact material 260 q.

Next, as shown in FIG. 5 , the lower semiconductor material 250 p , the lower ohmic contact material 260 p , the data conductive layer 270 , and the upper ohmic contact material 260 q are etched by using the second photosensitive film pattern 2000 as a mask to form lower semiconductor layers 253 Ip and 255 Ip, lower ohmic contact layers 263 Ip and 265 Ip, a source electrode 273 I, a drain electrode 275 I, and upper ohmic contact layers 263 Iq and 265 Iq of the infrared ray sensing transistor TrI. This also simultaneously forms lower semiconductor layer 254 Cp, lower ohmic contact pattern 261 Cp, data conductive pattern 271 C, and upper ohmic contact pattern 261 Cq of the readout transistor TrC. This etching also forms lower semiconductor layer 254 Vp, lower ohmic contact pattern 261 Vp, data conductive pattern 271 V, and upper ohmic contact pattern 261 Vq of the visible ray sensing transistor TrV.

Here, the lower semiconductor layers 253 Ip and 255 Ip are divided into a source lower semiconductor layer 253 Ip and a drain lower semiconductor layer 255 Ip such that the current can not flow through the lower semiconductor layers 253 Ip and 255 Ip when the gate voltage is appled to the upper gate electrode 224 I, and the noise caused by the current may be prevented. It is preferable that the upper ohmic contact material 260 q is dry-etched, the data conductive layer 270 is wet-etched, and the lower ohmic contact material 260 p and the lower semiconductor material 250 p are dry-etched. The upper ohmic contact material 260 q , the lower ohmic contact material 260 p and the lower semiconductor material 250 p are dry-etched since the thickness of the upper ohmic contact material 260 q , the lower ohmic contact material 260 p and the lower semiconductor material 250 p are thin.

Next, the second photosensitive film pattern 2000 is removed.

Next, as shown in FIG. 6 , an upper semiconductor material 250 q is formed on the upper ohmic contact layers 263 Iq and 265 Iq of the infrared ray sensing transistor TrI, the upper ohmic contact pattern 261 Cq of the readout transistor TrC, the upper ohmic contact pattern 261 Vq of the visible ray sensing transistor TrV, and the blocking insulating layer 230 . Here, the upper semiconductor material 250 q may be made of amorphous silicon germanium or amorphous germanium.

Next, a third photosensitive film pattern 3000 is formed on the upper semiconductor material 250 q.

Next, as shown in FIG. 7 , the underlying layers are etched by using the third photosensitive film pattern 3000 as a mask to form an upper semiconductor layer 254 Iq of the infrared ray sensing transistor TrI. This etching also simultaneously forms lower ohmic contact layers 263 Cp and 265 Cp, a source electrode 273 C, a drain electrode 275 C, upper ohmic contact layers 263 Cq and 265 Cq, and upper semiconductor layers 253 Cq and 255 Cq of the readout transistor TrC. This step also forms lower ohmic contact layers 263 Vp and 265 Vp, a source electrode 273 V, a drain electrode 275 V, lower ohmic contact layers 263 Vq and 265 Vq, and upper semiconductor layers 253 Vq and 255 Vq of the visible ray sensing transistor TrV. Next, the third photosensitive film pattern 3000 is removed.

Next, as shown in FIG. 8 , a gate insulating layer 240 is formed on the upper semiconductor layer 254 Iq of the infrared ray sensing transistor TrI, the upper semiconductor layers 253 Cq and 255 Cq of the readout transistor TrC, and the upper semiconductor layers 253 Vq and 255 Vq of the visible ray sensing transistor TrV and the blocking insulating layer 230 .

Next, as shown in FIG. 1 , upper gate electrodes 224 V, 224 I, and 224 C are formed on the gate insulating layer 240 . The upper gate electrodes 224 V and 224 C overlap the lower semiconductor layers 254 Vp and 254 Cp, and the upper gate electrode 224 I overlaps the upper semiconductor layer 254 Iq. Next, a passivation layer 280 , a light blocking member 310 , an overcoat 320 , and a common electrode 330 are sequentially formed on the upper gate electrodes 224 V, 224 I, and 224 C.

As described above, the infrared ray sensing transistor, the visible ray sensing transistor, and the readout transistor are formed by using the second photosensitive film pattern and the third photosensitive film pattern in the same process, such that the number of photolithography processes used in fabricating the infrared ray sensing transistor, the visible ray sensing transistor, and the readout transistor may be reduced.

FIG. 9 is a cross-sectional view of a display device according to a further exemplary embodiment of the present invention.

As shown in FIG. 9 , a display device includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200 .

The liquid crystal layer 3 has negative dielectric anisotropy, and liquid crystal molecules 31 of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels when an electric field is not applied.

Alignment layers (not shown) may be formed on the inner surfaces of the display panels 100 and 200 , and they may be vertical alignment layers.

The display device may further include a lower polarizer 12 disposed under the lower panel 100 , and an upper polarizer 22 disposed on the upper panel 200 . The intensity of the light provided to the lower panel 100 and the upper panel 200 may be controlled by controlling the polarization characteristics of the lower polarizer 12 and the upper polarizer 22 .

The display device may further include a backlight unit 910 disposed under the lower panel 100 . In this embodiment, the backlight unit 910 includes at least one infrared ray emitting member 920 and at least one visible ray emitting member 930 . The infrared ray emitting member 920 and the visible ray emitting member 930 may be point light sources such as light-emitting devices (LEDs). Also, the infrared rays and the visible rays respectively emitted from the infrared ray emitting member 920 and the visible ray emitting member 930 may be incident to the lower panel in a direction generally perpendicular to the panel.

The infrared ray emitting member 920 and the visible ray emitting member 930 may be generally uniformly distributed across the whole surface of the backlight unit 910 , or at least a substantial portion thereof, so that substantially the entire surface of the backlight unit 910 (or a substantial portion thereof) emits infrared and visible light. The invention contemplates any arrangement and number of infrared and visible light emitters. For example, the members 920 , 930 may be arranged in alternating fashion, may be arranged according to some predetermined ratio of members 920 to members 930 , or may be arranged in a random, pseudorandom, or arbitrary manner.

The lower panel 100 includes a lower substrate 110 made of transparent glass or plastic, and a pixel transistor TrP disposed on the lower substrate 110 . The pixel transistor TrP includes a gate electrode 124 p formed on the lower substrate 110 , a gate insulating layer 140 covering the lower substrate 110 and the gate electrode 124 P, a semiconductor layer 154 P overlapping the gate electrode 124 P and disposed on the gate insulating layer 140 , ohmic contact layers 163 P and 165 P disposed on the semiconductor layer 154 P, a source electrode 173 P disposed on the ohmic contact layer 163 P, and a drain electrode 175 P separated from the source electrode 173 P on the ohmic contact layer 165 P.

The lower panel 100 may further include a gate line disposed on the lower substrate 110 and a data line intersecting the gate line. Here, the gate line may be connected to the gate electrode 124 P of the pixel transistor TrP. Also, the data line may be connected to the source electrode 173 P of the pixel transistor TrP.

The lower panel 100 may further include a passivation layer 180 covering the pixel transistor TrP, a color filter 23 disposed on the passivation layer 180 , an overcoat 25 disposed on the color filter 23 , and a pixel electrode 190 disposed on the overcoat 25 . Here, the pixel electrode 190 may be connected to the drain electrode 175 P of the pixel transistor TrP while passing through the overcoat 25 and the passivation layer 180 .

FIG. 10 is an isometric cutaway view illustrating the sensing of an object by using the display device of FIG. 9 .

As shown in FIG. 10 , infrared rays and visible rays are generated in the backlight unit 910 . The infrared rays sequentially pass the lower polarizer 12 , the lower panel 100 , the liquid crystal layer 3 , the upper panel 200 , and the upper polarizer 22 .

The visible rays sequentially pass the lower polarizer 12 , the lower panel 100 , the liquid crystal layer 3 , the upper panel 200 , and the upper polarizer 22 . Here, the visible rays may be made any desirable color by the color filter 23 of the lower panel 100 .

For touch sensing of a first object T 1 positioned on the liquid crystal display, the infrared rays provided from the backlight unit 910 may be used. When the first object T 1 is close to the liquid crystal display, the infrared rays emitted from the liquid crystal display are reflected by the first object T 1 . The reflected infrared rays are incident to, and detected by, the infrared ray sensors TrI positioned in the upper panel 200 . The number and locations of sensors TrI that detect object T 1 are used to determine whether and where a “touch” has occurred, as well as the size and shape of the contact.

When the visible light emitted from the LCD panel is brighter than the ambient light, visible light from the LCD panel can be used for image sensing. This is illustrated in connection with second object T 2 , which is shown in FIG. 10 as being moved proximate to the LCD. When object T 2 is moved sufficiently close, it reflects visible light from the LCD. This reflected visible light is incident to, and detected by, the visible ray sensor TrV positioned in the upper panel 200 . The number and locations of sensors TrV that detect object T 2 are used to determine the presence of object T 2 (i.e., whether it has “touched” the LCD), as well as the size, shape, and color of the object.

After confirming the contact portion of the second object T 2 through touch sensing, the visible light emitted from the liquid crystal display may be selectively changed, to more accurately sense the second object T 2 . That is, once an object such as object T 2 is detected through one mechanism (e.g., infrared sensing), another mechanism (e.g., visible light) can be adjusted to further sense the object. For example, when the visible light emitted from the liquid crystal display is darker than the ambient visible light, the object T 2 can be first detected by infrared rays. Once detection has occurred, the visible rays emitted from the liquid crystal display can be selectively brightened, e.g., only in areas close to the object T 2 , such that more effective image sensing of the second object T 2 is possible.

FIG. 11 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention.

This embodiment is substantially the same as the exemplary embodiment shown in FIG. 1 , except that the lower semiconductor layers of the infrared ray sensing transistor TrI are not divided. Description of those elements that remain largely unchanged from FIG. 1 is thus largely omitted.

In FIG. 11 , a lower semiconductor layer 254 Ip is positioned on the blocking insulating layer 230 , and a separating layer 25 is formed on the channel of the lower semiconductor layer 254 Ip. The separating layer 25 may be a nitrogen oxide layer formed through a plasma treatment.

Lower ohmic contact layers 263 Ip and 265 Ip are positioned on the lower semiconductor layer 254 Ip. A source electrode 273 I is positioned on the lower ohmic contact layer 263 Ip, and a drain electrode 275 I is separated from the source electrode 273 I on the lower ohmic contact layer 265 Ip. An upper ohmic contact layer 263 Iq is positioned on the source electrode 273 I, and an upper ohmic contact layer 265 Iq is positioned on the drain electrode 275 I.

The upper semiconductor layer 254 Iq may be positioned on the exposed separating layer 25 between the upper ohmic contact layers 263 Iq and 265 Iq, as well as the source electrode 273 I and the drain electrode 275 I.

The lower semiconductor layer 254 Ip can include amorphous silicon, and the upper semiconductor layer 254 Iq can include amorphous silicon germanium or amorphous germanium. The separating layer 25 separates the lower semiconductor layer 254 Ip and the upper semiconductor layer 254 Iq, thereby preventing noise caused by the lower semiconductor layer 254 Ip. This allows the infrared ray sensing transistor TrI, which utilizes the upper semiconductor layer 254 Iq, to have greater infrared ray sensitivity.

FIG. 12 to FIG. 14 are cross-sectional views sequentially showing a manufacturing method of an exemplary embodiment for a liquid crystal display shown in FIG. 11 . A manufacturing method for the liquid crystal display shown in FIG. 11 will be described with reference to FIGS. 12 to 14 .

The present exemplary embodiment is substantially the same as the exemplary embodiment shown in FIG. 1 to FIG. 8 , except that the lower semiconductor layers of the infrared ray sensing transistor TrI are not divided. Description of those elements that remain unchanged from previous figures is thus largely omitted.

As shown in FIG. 12 , a fourth photosensitive film pattern 4000 is formed on the upper ohmic contact material 260 p . The pattern 4000 includes a first portion 4100 , and a second portion 4200 that is thinner than the first portion 4100 .

Next, a lower semiconductor material 250 p , a lower ohmic contact material 260 p , a data conductive layer 270 , and an upper ohmic contact material 260 q are etched by using the fourth photosensitive film pattern 4000 as a mask. This forms lower semiconductor layer 2541 p , lower ohmic contact pattern 261 Ip, data conductive pattern 271 I, and upper ohmic contact pattern 261 Iq of the infrared ray sensing transistor TrI. This etching also simultaneously forms lower semiconductor layer 254 Cp, lower ohmic contact pattern 261 Cp, data conductive pattern 271 C, and upper ohmic contact pattern 261 Cq of the readout transistor TrC. This etching also forms lower semiconductor layer 254 Vp, lower ohmic contact pattern 261 Vp, data conductive pattern 271 V, and upper ohmic contact pattern 261 Vq of the visible ray sensing transistor TrV.

Next, as shown in FIG. 13 , the fourth photosensitive film pattern 4000 is etched back to remove the second portion 4200 , thereby exposing the upper ohmic contact pattern 261 Iq of the infrared ray sensing transistor TrI. Also, the exposed upper ohmic contact pattern 261 Iq, the underlying data conductive pattern 271 I, and the lower ohmic contact pattern 261 Ip are etched to form upper ohmic contact layers 263 Iq and 265 Iq, a source electrode 273 I, a drain electrode 275 I, and lower ohmic contact layers 263 Ip and 265 Ip. Here, the lower semiconductor layer 254 Ip of the infrared ray sensing transistor TrI is exposed, and the first portion 4100 is etched so as to form a third portion 4101 having a reduced thickness.

Next, a process such as plasma treatment using nitrogen oxide (N 20 ) is executed to form a separating layer 25 at the channel of the exposed lower semiconductor layer 254 Ip of the infrared ray sensing transistor TrI. The separating layer 25 can be formed as a nitrogen oxide layer.

Next, as shown in FIG. 14 , the fourth photosensitive film pattern 4000 is removed. After that, an upper semiconductor material 250 q is formed on the upper ohmic contact layers 263 Iq and 265 Iq of the infrared ray sensing transistor TrI, the upper ohmic contact pattern 261 Cq of the readout transistor TrC, the upper ohmic contact pattern 261 Vq of the visible ray sensing transistor TrV, and the blocking insulating layer 230 . Here, the upper semiconductor material 250 q may be made of amorphous silicon germanium or amorphous germanium. Next, a fifth photosensitive film pattern 5000 is formed on the upper semiconductor material 250 q . Then, the underlying layers are etched by using the fifth photosensitive film pattern 5000 as a mask to form an upper semiconductor layer 254 Iq of the infrared ray sensing transistor TrI. This also simultaneously forms lower ohmic contact layers 263 Cp and 265 Cp, source electrode 273 C, drain electrode 275 C, upper ohmic contact layers 263 Cq and 265 Cq, and upper semiconductor layers 253 Cq and 255 Cq of the readout transistor TrC. This etching also forms lower ohmic contact layers 263 Vp and 265 Vp, source electrode 273 V, drain electrode 275 V, upper ohmic contact layers 263 Vq and 265 Vq, and upper semiconductor layers 253 Vq and 255 Vq of the visible ray sensing transistor TrV. Then, the fifth photosensitive film pattern 5000 is removed.

Next, as shown in FIG. 11 , a gate insulating layer 240 is formed on the upper semiconductor layer 254 Iq of the infrared ray sensing transistor TrI, the upper semiconductor layers 253 Cq and 255 Cq of the readout transistor TrC, the upper semiconductor layers 253 Vq and 255 Vq of the visible ray sensing transistor TrV, and the blocking insulating layer 230 . Afterward, upper gate electrodes 224 V, 224 I, and 224 C are formed on the gate insulating layer 240 . The upper gate electrodes 224 V and 224 C overlap the lower semiconductor layers 254 Vp and 254 Cp, and the upper gate electrode 224 I overlaps the upper semiconductor layer 254 Iq. Next, a passivation layer 280 , a light blocking member 310 , an overcoat 320 , and a common electrode 330 are formed on the upper gate electrodes 224 V, 224 I, and 224 C.

As described above, the infrared ray sensing transistor, the visible ray sensing transistor, and the readout transistor are formed by using the second photosensitive film pattern and the third photosensitive film pattern in the same process, such that the number of photolithography processes for manufacturing the infrared ray sensing transistor, the visible ray sensing transistor, and the readout transistor may be reduced.

While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.