Method and system for converting time intervals

This application claims the benefit of the priority date of German application 102009047860.4 filed on Sep. 30, 2009, the entire content of which are herein incorporated by reference.

The present invention relates generally to time interval measurements. In particular, the present disclosure relates to a method and system for improved time interval conversions.

In many areas of engineering, accurate measurement of a time interval is useful. For example, accurate measurement of a time interval is used in a phase detector of a digital phase locked loop (PLL). In addition, accurate measurement of a time interval is used in analog-to-digital converters and in high-resolution measuring equipment.

Often, time-to-digital converters (TDC) are used in order to perform accurate measurement of a time interval. After a time interval has been measured by a time-to-digital converter, it is necessary to wait a certain time until the time-to-digital converter is ready for a fresh measurement. This time is referred to as dead time for a time-to-digital converter. In order to allow measurement of time intervals without dead time, it is possible to alternatively use two time-to-digital converters which are connected in parallel. This is called time interleaving. The arrangement has the associated drawback that a mismatch in the two parallel-connected time-to-digital converters, which is caused by process variations, for example, results in the occurrence of a periodically occurring conversion error. In addition, such an arrangement takes up a large surface area. Therefore, a need exists for a method and system for improved time interval conversions.

FIG. 1 is a diagram illustrating a system for converting time intervals in accordance with one embodiment of the present disclosure.

FIG. 2 is a diagram of a time profile of a signal in accordance with one embodiment of the present disclosure.

FIG. 3 is a diagram illustrating an embodiment of a system for converting time intervals in accordance with an alternative embodiment of the present disclosure.

FIG. 4 is a diagram of a time-to-digital converter in accordance with one embodiment of the present disclosure.

FIG. 5 is a diagram of a time profile of signals of a time-to-digital converter in accordance with one embodiment of the present disclosure.

FIG. 6 is a diagram of a time-to-digital converter in accordance with an alternative embodiment of the present disclosure.

FIG. 7 is a diagram of a time profile of signals of a time-to-digital converter in accordance with an alternative embodiment of the present disclosure.

FIG. 8 is a diagram of two time-to-digital converters in accordance with one embodiment of the present disclosure.

FIG. 9 is a diagram of a system for converting time intervals in accordance with one embodiment of the present disclosure.

FIG. 10 is a diagram of a system for converting time intervals in accordance with yet another embodiment of the present disclosure.

FIG. 11 is a flowchart of an exemplary process for converting time intervals in accordance with one embodiment of the present disclosure.

The present disclosure provides a system and method for converting time intervals. In one embodiment, the system comprises a first time-to-digital converter having a first resolution configured to convert a first time interval, a second time-to-digital converter having a second resolution configured to convert a second time interval, and a third time-to-digital converter having a third resolution and coupled to the first time-to-digital converter and the second time-to-digital converter, the third time-to-digital converter configured to convert a third time interval and a fourth time interval.

In another embodiment, an analog to digital converter is provided comprising a pulse modulator configured to convert an analog signal into a pulse-modulated signal, at least one time-to-digital converter coupled to the pulse modulator configured to convert the pulse-modulated signal into at least one digital value, and a digital processing unit coupled to the at least one time-to-digital converter configured to process the at least one digital value.

In yet another embodiment, a method for converting time intervals is provided. The method comprises converting a first time interval in a first time-to-digital converter, converting a second time interval in a second time-to-digital converter, controlling a conversion of a third time interval in a third time-to-digital converter, decoupling the first time-to-digital converter from the third time-to-digital converter; an, controlling a conversion of a fourth time interval in the third time-to-digital converter.

Referring to FIG. 1 , a diagram illustrating a system for converting time intervals is depicted in accordance with one embodiment of the present disclosure. Circuit arrangement 100 comprises a first time-to-digital converter 102 , a second time-to-digital converter 104 and a third time-to-digital converter 106 . The third time-to-digital converter 106 is coupled to the first time-to-digital converter 102 and the second time-to-digital converter 104 . The first time-to-digital converter 102 has a first resolution, the second time-to-digital converter 104 has a second resolution and the third time-to-digital converter 106 has a third resolution.

Referring to FIG. 2 , a diagram of a time profile of a signal is depicted in accordance with one embodiment of the present disclosure. Signal 202 is a pulse-modulated signal which has the value of a logic ‘1’ during a high phase or during a period TH and which has the value of a logic ‘0’ during a low phase or during a period TL.

Circuit arrangement 100 in FIG. 1 may be used to measure both the period TH and the period TL of the signal 202 and to convert them into digital values. For the conversion of the period or time interval TH, the first time-to-digital converter 102 converts a first time interval t 1 , which is a first interval portion of period TH. In addition, the third time-to-digital converter 106 converts a third time interval t 3 , which is a second interval portion of period TH. The third time interval t 3 follows the first time interval t 1 in time, and the first time interval t 1 and the third time interval t 3 together form the period TH.

For the conversion of the period or time interval TL, the second time-to-digital converter 104 converts a second time interval t 2 , which is a first interval portion of the period TL. In addition, the third time-to-digital converter 106 converts a fourth time interval t 4 , which is a second interval portion of the period TL. The fourth time interval t 4 follows the second time interval t 2 in time, and the second time interval t 2 and the fourth time interval t 4 together form the period TL.

Circuit arrangement 100 in FIG. 1 allows conversion of successive time intervals TH and TL without dead time. A dead time in one of the two time-to-digital converters 102 , 104 is avoided by virtue of a conversion being performed by the respective time-to-digital converters 102 , 104 . The first time-to-digital converter 102 has a certain dead time after the conversion of the first time interval t 1 . During this dead time in the first time-to-digital converter 102 , the time interval TL is converted in the second time-to-digital converter 104 .

The conversion of the time interval TH does not take place completely in the first time-to-digital converter 102 , but rather a portion of the time interval TH is converted in the third time-to-digital converter 106 . Similarly, the time interval TL is not converted completely in the second time-to-digital converter 104 , but rather it is partially converted in the third time-to-digital converter 106 . The first time-to-digital converter 102 and the second time-to-digital converter 104 share the third time-to-digital converter 106 for the conversion of time intervals. The conversion of a portion of the time intervals by a common time-to-digital converter, such as the third time-to-digital converter 106 , allows a low surface area requirement for circuit arrangement 100 . Since the time intervals t 3 , t 4 which are converted by the third time-to-digital converter 106 are not adjacent to one another in time, a possible dead time in the third time-to-digital converter 106 is insignificant.

In FIG. 2 , the time interval TL directly follows the time interval TH in time, and the time intervals TL, TH do not overlap. In other exemplary embodiments, the time intervals TL, TH may partially overlap or the time intervals TL, TH may not follow one another directly in time.

Referring to FIG. 3 , a diagram illustrating an embodiment of a system for converting time intervals is depicted in accordance with an alternative embodiment of the present disclosure. Circuit arrangement 300 comprises a first time-to-digital converter 302 , a second time-to-digital converter 304 , a third time-to-digital converter 306 , a changeover unit 308 and a calculation unit 310 . The changeover unit 308 is used to couple either the first time-to-digital converter 302 or the second time-to-digital converter 304 to the third time-to-digital converter 306 . As illustrated in the embodiment from FIG. 2 , the first time-to-digital converter 302 and the second time-to-digital converter 304 share the third time-to-digital converter 306 .

The first time-to-digital converter 302 receives a first start signal 312 and a first stop signal 314 . The first start signal 312 is used in the first time-to-digital converter 302 to control a beginning of a conversion of a first time interval, and the first stop signal 314 is used in the first time-to-digital converter 302 to control an end of the conversion of the first time interval. The first time-to-digital converter 302 outputs one or more output signals 316 which indicate a digital value of the converted, first time interval. The calculation unit 310 receives the one or more output signals 316 via the changeover unit 308 . The first time-to-digital converter 302 also outputs a first control signal 318 which is coupled by the changeover unit 308 to the third time-to-digital converter 306 in order to control it.

In a similar manner, the second time-to-digital converter 304 receives a second start signal 320 and a second stop signal 322 . The second start signal 320 is used in the second time-to-digital converter 304 to control a beginning of a conversion of a second time interval, and the second stop signal 322 is used in the second time-to-digital converter 304 to control an end of the conversion of the second time interval. The second time-to-digital converter 304 outputs one or more output signals 324 which indicate a digital value of the converted, second time interval. The calculation unit 310 receives the one or more output signals 324 via the changeover unit 308 . The second time-to-digital converter 304 also outputs a second control signal 326 which is coupled by the changeover unit 308 to the third time-to-digital converter 306 in order to control it.

The third time-to-digital converter 306 receives a third start signal 328 and a third stop signal 330 . The third start signal 328 is used in the third time-to-digital converter 306 to control a beginning of a conversion of a third and a fourth time interval. The third stop signal 330 is used in the third time-to-digital converter 306 to control an end of the conversion of the third and fourth time intervals. The third time-to-digital converter 306 converts the third time interval into a third digital value and the fourth time interval into a fourth digital value. The third time-to-digital converter 302 outputs one or more output signal 338 which indicate the digital value of the converted, third or fourth time interval, and the calculation unit 310 receives the one or more output signal 338 .

The control of the beginning and the end of the conversion of the third time interval in the third time-to-digital converter 306 is derived from the first start signal 312 and the first stop signal 314 , which control the conversion of the first time interval. In other words, the third time interval is derived from the first time interval, and there is a time reference between the first time interval and the third time interval. As FIG. 3 shows, the first stop signal 314 is coupled to the third start signal 328 by a first multiplexer 332 of the changeover unit 308 . The conversion of the third time interval is therefore started at the end of the conversion of the first time interval. The first control signal 318 is coupled to the third stop signal 330 by a second multiplexer 334 of the changeover unit 308 . The end of the conversion of the third time interval is therefore controlled by the first time-to-digital converter 302 , which produces the first control signal 318 internally.

Similarly, the control of the beginning and the end of the conversion of the fourth time interval in the third time-to-digital converter 306 is derived from the second start signal 320 and the second stop signal 322 , which control the conversion of the second time interval. In other words, the fourth time interval is derived from the second time interval, and there is a time reference between the second time interval and the fourth time interval. As FIG. 3 shows, the second stop signal 322 is coupled to the third start signal 328 by the first multiplexer 332 of the changeover unit 308 . The conversion of the fourth time interval is therefore started at the end of the conversion of the second time interval. The second control signal 326 is coupled to the third stop signal 330 by the second multiplexer 334 of the changeover unit 308 . The end of the conversion of the fourth time interval in the third time-to-digital converter 306 is therefore controlled by the second time-to-digital converter 304 , which produces the second control signal 326 internally.

In one exemplary embodiment, the first time-to-digital converter 302 has a first resolution which is the same as a second resolution of the second time-to-digital converter 304 . In this case, the first or second resolution is lower than a third resolution of the third time-to-digital converter 306 . In other words, the first time-to-digital converter 302 and the second time-to-digital converter 304 each have a coarse resolution and the third time-to-digital converter 306 has a fine resolution. The first time-to-digital converter 302 is used to perform coarse quantization of the first time interval, and the second time-to-digital converter 304 is used to perform coarse quantization of the second time interval. The third time-to-digital converter 306 , which is selectively coupled to the first time-to-digital converter 302 and the second time-to-digital converter 304 , performs respective fine quantization of the third and fourth time intervals.

The first digital value, which is output by the first time-to-digital converter 302 , corresponds to a length of the first time interval, but is subject to a coarse quantization error on account of the low resolution. As already described above with reference to FIG. 3 , the third time interval is derived from the first time interval. In this case, the third time interval is derived from the first time interval such that the coarse quantization error caused in the first time-to-digital converter 302 can be corrected. The third time-to-digital converter 306 converts the third time interval into a third digital value, and the high resolution means that this conversion causes no or a small quantization error.

The calculation unit 310 receives the one or more output signals 316 , which indicate a first digital value of the converted, first time interval, via a third multiplexer 336 of the changeover unit 308 , and the calculation unit 310 also receives one or more output signals 338 which indicate a third digital value of the converted, third time interval. The quantization error in the first time-to-digital converter 302 is corrected via the calculation unit 310 by calculating a corrected digital value, which corresponds to the first time interval, from the first digital value and the third digital value. The calculation unit 310 outputs a result signal 340 which indicates the corrected digital value of the converted first time interval.

In a similar manner, the second digital value, which is output by the second time-to-digital converter 304 , corresponds to a length of the second time interval, but is subject to a coarse quantization error on account of the low resolution. As already described further above with reference to FIG. 3 , the fourth time interval is derived from the second time interval. In this case, the fourth time interval is derived from the second time interval such that the coarse quantization error caused in the second time-to-digital converter 304 can be corrected. The third time-to-digital converter 306 converts the fourth time interval into a fourth digital value, and the high resolution means that this conversion causes no or a small quantization error. The calculation unit 310 receives the one or more output signals 324 , which indicate a second digital value of the converted, second time interval, via the third multiplexer 336 of the changeover unit 308 , and the calculation unit 310 also receives one or more output signals 338 which indicate a fourth digital value of the converted, fourth time interval. The quantization error in the second time-to-digital converter 304 is corrected by the calculation unit 310 by calculating a corrected digital value, which corresponds to the second time interval, from the second digital value and the fourth digital value. The calculation unit 310 outputs the result signal 340 , which indicates the corrected digital value of the converted second time interval.

Circuit arrangement 300 performs hierarchic measurement of the first time interval. The first time interval is first of all converted into a first digital value, which is subject to a coarse quantization error, by the first time-to-digital converter 302 . Then, a third time interval, which is derived from the first time interval, is converted into a third digital value by the third time-to-digital converter 306 , with no or a small quantization error occurring. The third time-to-digital converter 306 is hierarchically subordinate to the first time-to-digital converter 302 in this case. Similarly, the circuit arrangement 300 performs hierarchic measurement of the second time interval.

In circuit arrangement 300 , the third time-to-digital converter 306 is selectively coupled to the first time-to-digital converter 302 and to the second time-to-digital converter 304 in order to correct a coarse quantization error which is caused by the first time-to-digital converter 302 or by the second time-to-digital converter 304 . The conversion in the third time-to-digital converter 306 causes no or a small quantization error.

The coarse quantization error is corrected by the third time-to-digital converter 306 . A mismatch between the first time-to-digital converter 302 and the second time-to-digital converter 304 may be kept to a minimum by appropriate design measures. Since the coarse quantization error is corrected the third time-to-digital converter 306 , no mismatch occurs in this case. Within the circuit arrangement 300 , the conversion of the first and second time intervals generates no periodically occurring conversion errors, even if there is a mismatch between the first time-to-digital converter 302 and the second time-to-digital converter 304 .

Referring to FIG. 4 , a diagram of a time-to-digital converter is depicted in accordance with one embodiment of the present disclosure. By way of example, the time-to-digital converter 402 may be used as a first 102 , 302 or as a second 104 , 304 time-to-digital converter in the circuit arrangements from FIG. 1 and FIG. 3 . The time-to-digital converter 402 comprises a loop counter 444 , a stop generator 446 and a plurality of delay elements 442 _ 1 - 442 _ 4 which are connected in a ring or in a loop. A first delay element 442 _ 1 receives a start signal 412 , which triggers a time event to control the beginning of a conversion of a time interval in the time-to-digital converter 402 . The time event received on the start signal 412 propagates through the delay elements 442 _ 1 - 442 _ 4 . An output of a fourth delay element 442 _ 4 outputs a signal 450 which is returned to an input of a first delay element 442 _ 1 in order to close the loop and to inject the time event which was delayed in the delay elements 442 _ 1 - 442 _ 4 into the loop again.

The output of the fourth delay element 442 _ 4 is also coupled to the loop counter 444 . The loop counter 444 counts a number of iterations which the time event propagates through the delay elements 442 _ 1 - 442 _ 4 . By way of example, the loop counter 444 comprises a counter whose count is incremented by the value ‘1’ each time that the time event reaches the output of the fourth delay element 442 _ 4 . The loop counter 444 performs a coarse conversion of the time interval. The loop counter 444 outputs one or more output signals 416 which indicate a digital value of the coarsely converted time interval.

The stop generator 446 is also coupled to the output of the fourth delay element 442 _ 4 and receives a stop signal 414 . The stop generator 446 comprises a sampling element 448 and outputs a control signal 418 which controls an end of a conversion of a time interval in another time-to-digital converter. As shown and described with reference to FIG. 3 , the control signal 418 may be coupled to another time-to-digital converter which performs fine conversion of the time interval. By way of example, the sampling element 448 is a flip-flop, wherein the stop signal 414 is injected into a data input of the flip-flop and wherein a clock input of the flip-flop is coupled to the output of the fourth delay element 442 _ 4 .

The delay elements 442 _ 1 - 442 _ 4 may be implemented as any desirable circuit element which delays the propagation of a signal. By way of example, each of the delay elements 442 _ 1 - 442 _ 4 respectively comprises a buffer, an inverter or an amplifier. A time event may be a pulse, an edge or a spike.

Referring to FIG. 5 , a diagram of a time profile of signals of a time-to-digital converter is depicted in accordance with one embodiment of the present disclosure. By way of example, the signals show a mode of operation of the embodiments shown in FIG. 3 and FIG. 4 .

A time event in the form of a pulse on the start signal 412 starts a conversion of a time interval tm which is to be converted in the time-to-digital converter 402 . The pulse propagates through the delay elements 442 _ 1 - 442 _ 4 as far as the output of the fourth delay element 442 _ 4 , which outputs the signal 450 . Once the pulse has reached the output of the fourth delay element 442 _ 4 , it prompts an increase in a count in the loop counter 444 , and the output signals 416 at the output of the loop counter 444 indicate a digital value which corresponds to a count increased by the value ‘1’. As FIG. 5 shows, the pulse transits the ring of delay elements 442 _ 1 - 442 _ 4 completely four times before the stop signal 414 becomes active by changing from the value of a logic ‘0’ to the value of a logic ‘1’. The activation of the stop signal 414 terminates the conversion of the time interval tm in the time-to-digital converter 402 , and the count in the loop counter 444 is no longer increased further.

As FIG. 5 shows, a time interval tc converted by the time-to-digital converter 402 does not correspond exactly to the time interval tm which is to be measured. A time interval tc actually converted by the time-to-digital converter 402 starts at the pulse of the start signal 412 and ends at the time of the last increase in the count in the loop counter 444 . A period of time tg situated between the time of the last increase in the count in the loop counter 444 and the activation of the stop signal 414 is not covered by the time-to-digital converter 402 . The digital value which is output on the output signals 416 is subject to a quantization error which is caused by the low or coarse resolution of the time-to-digital converter 402 . The resolution of the coarse time-to-digital converter 402 is defined by the delay that a time event undergoes when it propagates the loop of delay elements 442 _ 1 - 442 _ 4 completely once.

As already described with reference to FIG. 3 and FIG. 4 , the quantization error can be corrected by means of additional time-to-digital converter which is coupled to the time-to-digital converter 402 and which has a high resolution. The additional time-to-digital converter converts an additional time interval tf which is derived from the time interval tc or tm. The additional, fine time-to-digital converter corresponds to the third time-to-digital converter 306 as illustrated and described in FIG. 3 , for example, and the additional time interval tf corresponds to the third time interval described in FIG. 3 , for example. The time interval tm to be measured and the time interval tc actually converted by the time-to-digital converter 402 correspond to the first time interval described in FIG. 3 .

As FIG. 5 shows and in a similar manner to that described with reference to FIG. 3 , a conversion of the time interval tf in the additional time-to-digital converter is started with the activation of the stop signal 414 . An end of the conversion in the additional time-to-digital converter is controlled by the time-to-digital converter 402 using the control signal 418 . As described with reference to FIG. 4 , the control signal 418 is produced by the time-to-digital converter 402 . The control signal 418 is activated by virtue of it changing from the value of a logic ‘0’ to the value of a logic ‘1’. The time-to-digital converter 402 activates the control signal 418 after the stop signal 414 has been activated and after the time event has reached the output of the fourth delay element 442 _ 4 again. Activation of the control signal 418 prompts an end to the conversion of the additional time interval tf in the additional time-to-digital converter.

A digital value which is output by the additional time-to-digital converter corresponds to the time interval tf and is subjected to no or a small quantization error. The quantization error caused by the coarse time-to-digital converter 402 can be corrected by calculating a corrected digital value which corresponds to the time interval tm which is to be measured. By way of example, the correction can be made in a calculation unit 310 , as has been shown and described with reference to FIG. 3 , with the calculation unit 310 receiving a digital value output by the time-to-digital converter 402 and a digital value output by the additional time-to-digital converter.

For the coarse measurement of the time interval tm or tc, it is possible to use a coarse time-to-digital converter with a low resolution. By way of example, the coarse time-to-digital converter may be in the form of a loop time-to-digital converter, as has been described with reference to FIG. 3 and FIG. 4 . A coarse time-to-digital converter has a low surface area requirement and a low power consumption. The fine measurement of the time interval tf requires a fine time-to-digital converter with a high resolution. By way of example, a Vernier time-to-digital converter or an interpolation time-to-digital converter can be used for the fine measurement. A fine time-to-digital converter has a high power consumption. As FIG. 5 shows, the time interval tf which is measured by the fine time-to-digital converter is short in comparison with the time interval tm or tc which is measured by the coarse time-to-digital converter.

The fine time-to-digital converter is therefore in operation only for a relatively short period of time, and the high power consumption of the fine time-to-digital converter occurs only during a relatively short period of time. Furthermore, a fine time-to-digital converter has a high surface area requirement. As FIG. 3 shows, the fine time-to-digital converter can be used jointly by a plurality of coarse time-to-digital converters, however, by virtue of the fine time-to-digital converter being selectively coupled to one of the coarse time-to-digital converters.

Referring to FIG. 6 , a diagram of a time-to-digital converter is depicted in accordance with an alternative embodiment of the present disclosure. By way of example, the time-to-digital converter 602 can be used in the circuit arrangements from FIG. 1 and FIG. 3 as a first or a second time-to-digital converter. The time-to-digital converter 602 is an extension of the time-to-digital converter 402 which has been shown and described with reference to FIG. 4 . In a similar manner to the time-to-digital converter 402 from FIG. 4 , the time-to-digital converter 602 receives a start signal 612 and a stop signal 614 , and it outputs a control signal 618 which can control an end of a conversion of a time interval in an additional time-to-digital converter. In a similar manner to the time-to-digital converter 402 from FIG. 4 , the time-to-digital converter 602 comprises a plurality of delay elements 642 _ 1 - 642 _ 4 which are connected in a ring or loop counter 644 into which a signal 650 _ 3 which is output by a fourth delay element 642 _ 4 , and a stop generator 646 .

In contrast to the time-to-digital converter 402 from FIG. 4 , the stop generator 646 of the time-to-digital converter 602 comprises a plurality of sampling elements 648 _ 1 - 648 _ 4 and a logic unit 652 . By way of example, the sampling elements 648 _ 1 - 648 _ 4 are in the form of flip-flop elements, with the stop signal 614 being input into a data input of each of the plurality of delay elements 642 _ 1 - 642 _ 4 and with a clock input of each of the plurality of sampling elements 648 _ 1 - 648 _ 4 being respectively coupled to an output of one of the plurality of delay elements 642 _ 1 - 642 _ 4 . Each of the plurality of sampling elements 648 _ 1 - 648 _ 4 therefore has a respective associated delay element 642 _ 1 - 642 _ 4 . In the time-to-digital converter 602 , the plurality of delay elements 642 _ 1 - 642 _ 4 are used to divide a transmit time which a time event requires in order to transmit the ring of delay elements 642 _ 1 - 642 _ 4 completely once into a plurality of phases. The logic unit 652 is coupled to the outputs of the plurality of delay elements 642 _ 1 - 642 _ 4 via the sampling elements 648 _ 1 - 648 _ 4 and outputs one or more signals 654 which indicate a digital value for that phase which the time event was in when the stop signal 614 was activated.

The signals 654 which indicate a digital value for the phase are input into a local calculation unit 658 in the same way as signals 656 which indicate at an output of the loop counter 644 a number of iteration loops which the time event has passed through. The local calculation unit 658 is part of the time-to-digital converter 602 and outputs one or more output signals 616 which indicate a digital value of the time interval converted in the time-to-digital converter 602 .

The logic unit 652 also produces a control signal 618 at an output which can control an end of a conversion of a time interval in an additional time-to-digital converter. Furthermore, the logic unit 652 controls enable inputs of the sampling elements 648 _ 1 - 648 _ 4 and of the loop counter 644 . The enable inputs and corresponding enable control lines are not shown in FIG. 6 for the sake of clarity.

The resolution of the time-to-digital converter 602 is essentially determined by a delay in which a time event occurs in one of the plurality of delay elements 642 _ 1 - 642 _ 4 . In comparison with the time-to-digital converter 402 from FIG. 4 , the time-to-digital converter 602 has a higher resolution, since the transmit time of the time event in the ring of delay elements 642 _ 1 - 642 _ 4 is divided into a plurality of phases. Since the time-to-digital converter 602 comprises four delay elements 642 _ 1 - 642 _ 4 , the transmit time is divided into four phases, namely phase 0 , phase 1 , phase 2 and phase 3 . An additional time-to-digital converter, which is coupled to the time-to-digital converter 602 in order to correct a quantization error, merely needs to have a small measurement range. The additional time-to-digital converter therefore has only a low surface area requirement and a low power requirement.

Referring to FIG. 7 , a diagram of a time profile of signals of a time-to-digital converter is depicted in accordance with an alternative embodiment of the present disclosure. The signals show a mode of operation of the embodiments presented in FIG. 3 and FIG. 4 by way of example.

A time event in the form of a pulse on the start signal 612 starts a conversion of a time interval tm which is to be converted in the time-to-digital converter 602 . The pulse propagates through the delay elements 642 _ 1 - 642 _ 4 , the outputs of which output the signals 650 _ 0 - 650 _ 3 . Once the pulse has reached the output of the fourth delay element 642 _ 4 , it prompts an increase in a count in the loop counter 644 , and the output signals 656 at the output of the loop counter 644 indicate a digital value which corresponds to a count increased by the value ‘1’. As FIG. 6 shows, the pulse transmits through the ring of delay elements 642 _ 1 - 642 _ 4 completely five times before the stop signal 614 becomes active by changing from the value of a logic ‘0’ to the value of a logic ‘1’. The activation of the stop signal 614 prompts the count in the loop counter 644 to be increased no further.

The activation of the stop signal 614 also prompts a signal 660 _ 1 at an output of the flip-flop element 648 _ 2 to be set to the value of a logic ‘1’. The logic unit 652 then outputs the digital value ‘1’ on the signals 654 . This indicates that the time event was in phase 1 at the time at which the stop signal 614 was activated. The other flip-flop elements 648 _ 1 , 648 _ 3 , 648 _ 4 are deactivated as soon as the stop signal 614 has been sampled in the flip-flop element 648 _ 2 .

As FIG. 7 shows, a count indicated by the loop counter 644 corresponds to the time interval tc 1 . A value indicated by the logic unit 652 corresponds to the time interval tc 2 . The local calculation unit 658 performs weighting of the value which is output by the logic unit 652 , and adds this weighted value to the value which is output by the loop counter 644 . The local calculation unit 658 outputs a value corresponding to the time interval tc on the output signals 616 . This time interval tc does not correspond exactly to the time interval tm which is to be measured. A time interval tc actually converted by the time-to-digital converter 602 starts with the pulse of the start signal 412 and ends at the time at which the time event arrives at the output of the flip-flop element 642 _ 2 . In this case, a period of time tg between the activation of the stop signal 614 and the time at which the time event arrives at the output of the flip-flop element 642 _ 2 is covered excessively by the time-to-digital converter 602 . The value which is output on the output signals 616 is subject to a quantization error which is caused by the low or coarse resolution of the time-to-digital converter 602 .

As already described with reference to FIG. 3 , FIG. 4 and FIG. 6 , the quantization error can be corrected by means of an additional time-to-digital converter which is coupled to the time-to-digital converter 602 and which has a high resolution. The additional time-to-digital converter converts an additional time interval tf which is derived from the time interval tc or tm. The additional, fine time-to-digital converter corresponds to the third time-to-digital converter 306 presented and described in FIG. 3 , for example, and the additional time interval tf corresponds to the third time interval described in FIG. 3 , for example. The time interval tm to be measured and the time interval tc actually converted by the time-to-digital converter 602 corresponds to the first time interval described in FIG. 3 , for example.

As FIG. 7 shows and as described in a similar manner to that with reference to FIG. 3 , a conversion of the time interval tf in the additional time-to-digital converter is started when the stop signal 614 is activated. An end of the conversion in the additional time-to-digital converter is controlled by the time-to-digital converter 602 using the control signal 618 . As described with reference to FIG. 6 , the control signal 618 is produced by the time-to-digital converter 602 . The control signal 618 is activated by changing from the value of a logic ‘0’ to the value of a logic ‘1’. The time-to-digital converter 602 activates the control signal 618 after the stop signal 614 has been activated. As FIG. 7 shows, the time-to-digital converter 602 activates the control signal 618 with a delay of two phases after the signal 660 _ 1 at the output of the flip-flop element 648 _ 2 has been set to the value of a logic ‘1’, for example. Activation of the control signal 618 prompts an end of the conversion of the further time interval tf in the additional time-to-digital converter. A digital value which is output by the additional time-to-digital converter corresponds to the time interval tf and is subject to no or a small quantization error.

The quantization error, caused by the coarse time-to-digital converter 602 , can be corrected by calculating a corrected digital value which corresponds to the time interval tm which is to be measured. By way of example, the correction can be made in a calculation unit of a circuit arrangement, as has been shown and described with reference to FIG. 3 , with the calculation unit receiving a digital value which is output by the time-to-digital converter 602 and a digital value which is output by the additional time-to-digital converter.

Referring to FIG. 8 , a diagram of two time-to-digital converters is depicted in accordance with one embodiment of the present disclosure. By way of example, the time-to-digital converters can be used in the circuit arrangements from FIG. 1 and FIG. 3 as first and second time-to-digital converters. The first time-to-digital converter 802 and the second time-to-digital converter 804 have the same logical circuit design, which is similar to the logical circuit design of the time-to-digital converter 602 , as has been shown and described with reference to FIG. 6 . The first time-to-digital converter 802 receives a first stop signal 814 _ 1 and outputs a first control signal 818 _ 1 and first output signals 816 _ 1 which indicate a digital value of the time interval converted in the first time-to-digital converter 802 . The first time-to-digital converter 802 comprises a first stop generator 846 _ 1 and a first, local calculation unit 658 _ 1 . The second time-to-digital converter 804 receives a second stop signal 814 _ 2 and outputs a second control signal 818 _ 2 and second output signals 816 _ 2 which indicate a digital value of the time interval converted in the second time-to-digital converter 804 . The second time-to-digital converter 804 comprises a second stop generator 846 _ 2 and a second, local calculation unit 658 _ 2 .

The first time-to-digital converter 802 and the second time-to-digital converter 804 are coupled to a common circuit unit 862 . The common circuit unit 862 receives a start signal 812 and comprises a plurality of delay elements 842 _ 1 - 842 _ 4 , which are connected as a ring, and a loop counter 844 , which is coupled to an output of a fourth delay element 842 _ 4 . The logical design of the common circuit unit 862 in this case corresponds to the logical design of the delay elements 642 _ 1 - 642 _ 4 and of the loop counter 644 from FIG. 6 .

When the first time-to-digital converter 802 , the second time-to-digital converter 804 and the circuit unit 862 are used in the circuit arrangement 300 from FIG. 3 , for example, it is not necessary for the delay elements and the loop counter to be provided separately for each time-to-digital converter 302 , 304 , but rather the two time-to-digital converters 302 , 304 share the delay elements and the loop counter. In this case, the first time-to-digital converter 302 and the second time-to-digital converter 304 share the third time-to-digital converter 306 . In addition, the first time-to-digital converter 302 and the second time-to-digital converter 304 share the delay elements 642 _ 1 - 642 _ 4 and the loop counters 644 . This allows a further reduction in the surface area requirement of the circuit arrangement 300 , which results in an ultracompact circuit arrangement with an optimized mode of operation without dead times and with reduced energy consumption. Since the surface area requirement determines the production costs to a considerable extent, this ultracompact circuit arrangement can achieve a substantial reduction in the production costs.

The delay elements 842 _ 1 - 842 _ 4 of the common circuit unit 862 are constantly in operation, for example, i.e. a time event propagates continually through the ring of delay elements 842 _ 1 - 842 _ 4 . The conversion in the first time-to-digital converter 802 and in the second time-to-digital converter 804 is in this case controlled by the first stop signal 814 _ 1 and the second stop signal 814 _ 2 . In another embodiment, the propagation of the time event is stopped at the end of each conversion and restarted before the beginning of a new conversion.

Referring to FIG. 9 , a diagram of a system for converting time intervals is depicted in accordance with one embodiment of the present disclosure. The circuit arrangement 900 comprises an event generator 964 , an event distributor 966 , a result unit 968 , a plurality of M time-to-digital converters 902 _ 1 - 902 _M with a low resolution and a plurality of N time-to-digital converters 906 _ 1 - 906 _N with a high resolution. Each of the plurality of M time-to-digital converters 902 _ 1 - 902 _M has a lower resolution than each of the plurality of N time-to-digital converters 906 _ 1 - 906 _N. The plurality of M time-to-digital converters 902 _ 1 - 902 _M is subsequently referred to as coarse time-to-digital converters, and the plurality of N time-to-digital converters 906 _ 1 - 906 _N is subsequently referred to as fine time-to-digital converters. The plurality of coarse time-to-digital converters comprises a time-to-digital converter as has been described in the preceding sections, for example.

The event generator 964 receives a plurality of K input signals 970 _ 1 - 970 _K and produces time events from the input signals 970 _ 1 - 970 _K. The time events control a beginning and an end of a conversion of time intervals in the coarse time-to-digital converters 902 _ 1 - 902 _M. The time events are input into the coarse time-to-digital converters 902 _ 1 - 902 _M by start signals 912 _ 1 - 912 _M and stop signals 914 _ 1 - 914 _M. The coarse time-to-digital converters 902 _ 1 - 902 _M output output signals 916 _ 1 - 916 _M which indicate values of the converted time intervals. The output signals 916 _ 1 - 916 _M are input into the result unit 968 .

The coarse time-to-digital converters 902 _ 1 - 902 _M also output control signals 918 _ 1 - 918 _M which control an end of a conversion of time intervals in the fine time-to-digital converters 902 _ 1 - 902 _M. The control signals 918 _ 1 - 918 _M and the stop signals 914 _ 1 - 914 _M are input into the event distributor 966 , which distributes the time events on the control signals 918 _ 1 - 918 _M and the stop signals 914 _ 1 - 914 _M over the fine time-to-digital converters 906 _ 1 - 906 _N. The event distributor 966 selectively couples the fine time-to-digital converters 906 _ 1 - 906 _M to the coarse time-to-digital converters 902 _ 1 - 902 _M. The fine time-to-digital converters 906 _ 1 - 906 _N output output signals 938 _ 1 - 938 _N which indicate values of the time intervals converted by them. The output signals 938 _ 1 - 938 _N are input into the result unit 968 . The result unit 968 performs postprocessing, and an output 972 outputs an overall measurement result from the circuit arrangement 900 .

The event generator 964 selects one of the coarse time-to-digital converters 902 _ 1 - 902 _M for performing the conversion of a time interval on the basis of a random algorithm, for example. Similarly, the event distributor 966 selects one of the fine time-to-digital converters 906 _ 1 - 906 _N on the basis of a random algorithm, for example. By way of example, the event generator 964 and/or the event distributor 966 comprises a digital multi-bit sigma-delta converter in order to produce the random algorithm. The use of random algorithms for the selection of the time-to-digital converters 902 _ 1 - 902 _M, 906 _ 1 - 906 _N makes it possible to avoid occurrence of periodicities at the output 972 .

In order to achieve a low surface area requirement for the circuit arrangement 900 , one or more coarse time-to-digital converters 902 _ 1 - 902 _M can be coupled to the same instance of the fine time-to-digital converters 906 _ 1 - 906 _N by the event distributor 966 . In other words, one or more of the coarse time-to-digital converters 902 _ 1 - 902 _M can share one or more of the fine time-to-digital converters 906 _ 1 - 906 _N. In this case, the plurality of M coarse time-to-digital converters 902 _ 1 - 902 _M is smaller than the plurality of N fine time-to-digital converters 906 _ 1 - 906 _N.

Referring to FIG. 10 , a diagram of a system for converting time intervals is depicted in accordance with yet another embodiment of the present disclosure. The analog-to-digital converter 1000 comprises a pulse modulator 1074 , a time-to-digital converter 1076 and a digital processing unit 1078 . The pulse modulator 1074 receives an analog input signal 1080 at an input and converts the input signal into a pulse-modulated signal 1082 at its output. The pulse-modulated signal 1082 is input into the time-to-digital converter 1076 , which comprises a circuit arrangement, as has been described in the preceding sections.

The time-to-digital converter 1076 converts a period of a high phase of the pulse-modulated signal 1082 into a digital value and outputs the digital value at its output 1084 . In addition, the time-to-digital converter 1076 converts a period of a low phase of the pulse-modulated signal 1082 into an additional digital value and outputs the digital value at its additional output 1086 . The output 1084 and the additional output 1086 of the time-to-digital converter 1076 are coupled to the digital processing unit 1078 , which performs postprocessing of the digital value and of the additional digital value.

Referring to FIG. 11 , a flowchart of an exemplary process for converting time intervals is depicted in accordance with one embodiment of the present disclosure. Process 1100 begins at step 1102 to convert a first time interval. Step 1102 may be performed by a first time-to-digital converter. Process 1100 continues to step 1104 to convert a second time interval. Step 1104 may be performed by a second time-to-digital converter. Process 1000 then continues to step 1106 to couple the first time-to-digital converter to a third time-to-digital converter for the purpose of controlling a conversion of a third time interval in the third time-to-digital converter. Process 1100 then continues to step 1108 to decouple the first time-to-digital converter from the third time-to-digital converter.

Process 1100 completes at step 1110 to couple the second time-to-digital converter to the third time-to-digital converter for the purpose of controlling a conversion of a fourth time interval in the third time-to-digital converter. The order of the steps of process 1100 does not need to correspond to the order described above. The method 1100 can be performed with one of the circuit arrangements or with one of the time-to-digital converters as have been described in the preceding sections.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.