Low power, multi-chip diversity architecture

1. Technical Field

The embodiments herein generally relate to a multi-chip antenna diversity architecture, and, more particularly, to an optimized antenna diversity and power consumption architecture based on channel conditions.

2. Description of the Related Art

Mobile television receivers can be integrated with a variety of devices ranging from low cost low performance products to high cost high performance products to achieve the benefits of antenna diversity. It is possible to design a single chip product to address both ends of the market by creating a multi-chip diversity solution to produce error free audio/video. For the low-performance market a single receiver can be used. For the high-performance market multiple receivers can be tied together to achieve the performance benefits associated with antenna diversity.

For optimizing the performance of mobile television receivers, multiple receiver chips are tied together in order to obtain better performance associated with antenna diversity. In a traditional multi-chip diversity architecture, both receiver chips are kept powered on all the time in order to protect against degrading channel conditions in an effort to receive error free audio/video. This leads to double power consumption even in good channel conditions though the diversity architecture is not providing superior quality audio/video data.

FIG. 1 illustrates a block diagram of a traditional multi-chip architecture 100 where receiver chips 104 A-B are tied together to achieve the benefits of antenna diversity. The mobile television receiver architecture 100 includes antennas 102 A-B, and receiver chips 104 A-B. The receiver chips 104 A-B include a tuner 106 A- 106 B and a demodulator 108 A-B. The receiver chip 104 A receives the signal input of varying range from the antenna 102 A.

The received signal is then sent into the receiver block 104 A. The tuner 106 A in the receiver chip 104 A is used to amplify the signal for further processing and finally the demodulator 108 A decodes the signal into an error free audio/video.

The receiver chip 104 A transmits the diversity data to the receiver chip 104 B to improve the quality of the audio/video signal. In favorable channel conditions, receiver chip 104 A is capable of processing the received signal to generate an error free audio/video data. But the received signal is sent to the receiver chip 104 B. Thus, in favorable channel conditions there is double power consumption by the architecture 100 . Therefore, there remains a need of a multi chip antenna diversity architecture that optimizes diversity as well as power consumption.

In view of the foregoing, an embodiment herein provides a multi-chip antenna diversity architecture that includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source V SS that indicates the first receiver chip as a slave chip. A second receiver chip that receives a second input signal from a second antenna. The second receiver chip includes a second tuner that amplifies the second input signal, a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. The second diversity combiner receives diversity data from the first demodulator. A second chip ID including a voltage source V DD that indicates the second receiver chip as a master chip, and a Diversity State Machine (DSM) that receives signal statistics from the first demodulator and the second demodulator. The DSM controls an operating state of the first receiver chip and the second receiver chip. The first receiver chip and the second receiver chip are structurally identical.

The DSM transmits a command to the Slave chip to power down using a general purpose input-output switch (GPIOX) available on the first receiver chip and the second receiver chip. The slave chip is powered ON upon the GPIOX being set to VDD. The slave chip is powered OFF upon the GPIOX being set to VSS. The DSM automatically power downs either the master chip or the slave chip depending upon channel conditions. The first demodulator transmits diversity data and signal statistics to the second receiver chip.

In another aspect, a multi-chip antenna diversity architecture that optimizes power consumption based on channel conditions is provided. The multi-chip antenna diversity architecture includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first clock phase lock loop (PLL) that generates a first digital clock, a first crystal oscillator operatively connected to the first clock PLL, a first tuner that amplifies the first input signal, a first demodulator operatively connected to the first tuner. The first demodulator demodulates the first input signal received from the first tuner. A first maximum ratio combiner (MRC) operatively connected to the first demodulator, a first power sequencer that controls the first receiver chip, and a first Diversity State Machine (DSM) operatively connected to the first power sequencer.

The multi-chip antenna diversity architecture further includes a second receiver chip that receives a second input signal from a second antenna. The second receiver chip includes a second clock PLL that generates a second digital clock, a second crystal oscillator operatively connected to the second clock PLL, a second tuner that amplifies the second input signal, a second demodulator operatively connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second MRC operatively connected to the second demodulator, a second power sequencer, and a second DSM operatively connected to the second power sequencer. The first receiver chip or the second receiver chip transitions a power state based on a value of at least one channel metric, and the second MRC and the second crystal oscillator are disabled.

The first receiver chip or the second receiver chip is powered OFF when the value of the channel metric exceeds a predetermined threshold value. The first DSM powers down any of the first receiver chip and the receiver chip when the channel conditions allow the first receiver chip or the second receiver to receive audio/video. The first power sequencer, and the first DSM are in an ‘Always On’ domain. The second power sequencer and the second DSM are in an ‘Always On’ domain. The second demodulator transmits the second input signal being demodulated to the first MRC and the second MRC. Digital power is removed to eliminate a majority of device leakage power.

The second clock PLL, the second crystal oscillator, the second tuner, the second demodulator, and the second MRC are disabled upon the first receiver chip being powered ON. The first tuner and the first demodulator, the second crystal oscillator and the second MRC are disabled upon the second receiver chip being powered ON, wherein the first MRC is powered ON. The channel metric includes any of a signal-to-noise ratio (SNR), a bit error rate (BER), a packet error rate (PER), and a received signal strength indication (RSSI).

In yet another aspect, a method of operating a multi-chip antenna diversity architecture to optimize antenna diversity and power consumption based on channel conditions is provided. The multi-chip antenna diversity architecture includes a master chip comprising a chip pin operatively connected to VDD. The master chip receives a first input signal from a first antenna. A slave chip that includes a chip pin operatively connected to VSS. The slave chip receives a second input signal from a second antenna. The method includes powering ON the master chip and the slave chip when a value of at least one channel metric of the multi-chip antenna diversity architecture is below a threshold value, and powering OFF the master chip or the slave chip when the value of the channel metrics of the multi-chip antenna diversity architecture exceeds the threshold value. Any of the master chip and the slave chip is powered OFF if the channel conditions allow for at least one of the master chip and the slave chip to receive error free audio/video data. The channel conditions comprise any of the SNR, a bit error rate (BER), a packet error rate (PER), and a received signal strength indication (RSSI). A Diversity State Machine (DSM) is used to automatically power down any of the master chip and the slave chip.

These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.

The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which:

FIG. 1 illustrates a block diagram of a traditional multi-chip architecture where receiver chips are tied together to achieve the benefits of antenna diversity;

FIG. 2 illustrates a block diagram of a multi-chip antenna diversity architecture according to an embodiment herein;

FIG. 3A illustrates a block diagram of a multi-chip antenna diversity architecture when both a master chip and a slave chip are powered ON according to a first embodiment herein;

FIG. 3B illustrates the block diagram of the multi-chip antenna diversity architecture when only the master chip is powered ON according to a second embodiment herein;

FIG. 3C illustrates the block diagram of the multi-chip antenna diversity architecture when only the slave chip is powered ON according to a third embodiment herein;

FIG. 4 illustrates a graphical representation of a received Signal-to-Noise Ratio (SNR) being operated by the DSM of FIGS. 3A through 3C , over a period of time according to an embodiment herein;

FIG. 5 illustrates a graphical representation of the operating states of the DSM of FIGS. 3A through 3C according to an embodiment herein;

FIG. 6 illustrates a graphical representation of a Packet Error Rate (PER) for a single chip according to an embodiment herein;

FIG. 7 illustrates a graphical representation of a Packet Error Rate (PER) after MRC combining according to an embodiment herein; and

FIG. 8 is a flow diagram illustrating a method according to an embodiment herein.

The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those skilled in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

The embodiments herein provide an architecture which selectively shuts down an individual chip in favorable channel conditions to save power. The embodiments herein achieve this by providing a Diversity State Machine (DSM) which automatically powers down either the master receiver or the slave receiver in a multi-chip diversity architecture depending upon the channel conditions to receive audio/video without errors. All transitions are completely controlled by circuits inside the chip, therefore intervention of any external processor is not required. The audio/video data is always emitted from a master chip. Also switching from diversity to a single chip configuration is seamless. There are no audio/video glitches when a chip or another is powered on or off. Referring now to the drawings, and more particularly to FIGS. 2 through 8 , where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments.

FIG. 2 illustrates a block diagram of a multi-chip antenna diversity architecture 200 according to an embodiment herein. The multi-chip antenna diversity architecture includes antennas 202 A-B and receiver chips 204 A-B. The receiver chips 204 A-B receive input signals from the antenna 202 A-B. In one embodiment, the receiver chip 204 A receives the input signal from the antenna 202 A. In another embodiment, the receiver chip 204 B receives the input signal from the antenna 202 B.

The receiver chip 204 A includes a tuner 206 A, a demodulator 208 A, a diversity (Maximum Ratio Combiner (MRC)) combiner 210 A, a Diversity State Machine (DSM) 212 A, a power sequencer 214 A, and a chip_ID 216 A. The receiver chip 204 B includes a tuner 206 B, a demodulator 208 B, a diversity (MRC) combiner 210 B, a Diversity State Machine (DSM) 212 B, a power sequencer 214 B, and a chip_ID 216 B. The chip_ID 216 A of the receiver chip 204 A is tied to V SS and indicates that the receiver chip 204 A is a slave chip. The chip_ID 216 B when tied to V DD indicates that the receiver chip 204 B is a master chip. In one embodiment, the receiver chip 204 A is referred to as the slave chip and the receiver chip 204 B is referred to as the master chip.

The tuner 206 A amplifies the input signal received from the antenna 202 A. Similarly, the tuner 206 B amplifies the input signal received from the antenna 202 B and transmits the amplified input signal to the demodulator 208 B. The demodulator 208 A receives the amplified input signal from the tuner 206 A and demodulates the amplified input signal. The demodulator 208 A transmits diversity data and corresponding signal statistics to the receiver chip 204 B (the master chip 204 B). The MRC combiner 210 B receives the diversity data from the demodulator 208 A and the demodulated input signal from the demodulator 208 B.

The MRC combiner 210 B combines the data from both demodulators and transmits the output data. In one embodiment, the output data may be audio/video data. In another embodiment, the output data comprises error free audio/video data. The demodulator 208 B transmits signal statistics to the DSM 212 B. The DSM 212 B additionally receives signal statistics from the demodulator 208 A. The DSM 212 B of the master chip 204 A controls the slave chip 204 A and the master chip 204 B.

In one embodiment, the DSM 212 B determines if the channel conditions are adequate to receive audio/video without errors based on channel conditions. In another embodiment, the channel conditions are the signal statistics. In yet another embodiment, the DSM 212 B sends signals to power sequencers 214 A-B instructing the power sequencers to power ON/OFF the slave chip 204 A and the master chip 204 B based on the channel conditions such as Signal-to-Noise Ratio (SNR), Bit Error Rate (BER), Packet Error Rate (PER), and a Received Signal Strength Indication (RSSI). If the conditions degrade, the DSM 212 B automatically powers ON both the receiver chips 204 A-B to receive the benefits of antenna diversity. Thus, the DSM 212 B will put the receiver chips 204 A and 204 B in three different operating states. In a first state both the master chip 204 B and the slave chip 204 A are powered ON, in a second state only the master chip 204 B is powered ON, and in a third state, only the slave chip 204 A is powered ON. Even when a receiver is powered OFF there is a small portion of digital logic in the ‘Always On’ domain which is used to maintain device state and be prepared to turn on the receiver in the event that signal conditions degrade. The ‘Always On’ domain includes the Power Sequencer ( 214 A-B) and the Diversity State Machine ( 212 A-B).

The DSM 212 B in the receiver chip 204 B controls the power switching of receiver chips 204 A-B based on the channel conditions using the power sequencers 214 A-B. In one embodiment, the power sequencers 214 A-B control the power ON and OFF of the receiver chip 204 A-B as determined by DSM 212 B. The DSM 212 B in the master chip 204 B transmits a command to the slave chip 204 A to power ON or OFF using a General Purpose Input-Output (GPIO) switch 211 A-B available in the receiver chips 204 A-B. The GPIO switch 211 A-B provides an interface between the master chip 204 B and the slave chip 204 A.

In an example embodiment, the GPIO is referred to as GPIOX. In one embodiment, when GPIOX 211 A-B is set to V DD , then the slave chip 204 A is powered ON. In another embodiment, when GPIOX 211 A-B is set to V SS , then the slave chip 204 A is powered OFF. In yet another embodiment, a bi-directional transmission between the master chip 204 B and the slave chip 204 A may be performed. The digital power is removed to eliminate the majority of CMOS leakage power. However, the DSM 212 A-B is powered ON to maintain an operating state by providing a power domain. The slave chip demodulator 208 A demodulates the incoming signal before it is sent to the master chip 204 B. The diversity combiner 210 A and the DSM 212 A are physically on the slave chip 204 A because the master and slave chips 204 A-B are identical. However, diversity combiner 210 A and DSM 212 A are not functional on the slave chip 204 A.

FIG. 3A illustrates a block diagram of multi-chip antenna diversity architecture 300 A when both a master chip 304 B and a slave chip 304 A are powered ON according to a first embodiment herein. The multi-chip antenna diversity architecture 300 A includes the slave chip 304 A and master chip 304 B. The slave chip 304 A includes an antenna 302 A, a clock PLL 306 A, a crystal oscillator 308 A, a tuner 310 A, a demodulator 312 A, a MRC 314 A, a power sequencer 316 A, and a Diversity State Machine 318 A. Similarly, the master chip 304 B includes an antenna 302 B, a clock phase lock loop (PLL) 306 B, a crystal oscillator 308 B, a tuner 310 B, a demodulator 312 B, a MRC 314 B, a power sequencer 316 B, and a Diversity State Machine 318 B.

The master chip 304 B receives an input signal from the antenna 302 B. Similarly, the slave chip 304 A receives an input signal from the antenna 302 A. The clock PLL 306 A-B generates digital clock signals from an input signal received. The output from crystal oscillator 308 B of the master chip 304 B is sent to the clock PLL 306 A of the slave chip 304 A in order to maintain frequency synchronization of both the master chip 304 B and the slave chip 304 A. In one embodiment, when both the master chip 304 B and the slave chip 304 A are powered ON, then the clock PLL 306 B, the crystal oscillator 308 B, the power sequencer 316 A-B, and the DSM 318 A-B are powered ON. In another embodiment, the functions of the crystal oscillator 308 A, and the MRC 314 A are disabled or powered OFF as shown in FIG. 3A . The output from the demodulator 312 A-B is transmitted to the MRC 314 B.

With reference to FIG. 3A , FIG. 3B illustrates the block diagram of the multi-chip antenna diversity architecture 300 B when only the master chip 304 B is powered ON according to a second embodiment herein. In one embodiment, when only the master chip 304 B is powered ON, then the clock PLL 306 B, the crystal oscillator 308 B, the power sequencer 316 A-B, and the Diversity State Machine 318 A-B are powered ON. In another embodiment, the functions of the clock PLL 306 A, the crystal oscillator 308 A, the tuner 310 A, the demodulator 312 A, and the MRC 314 A are disabled or powered OFF as shown in FIG. 3B . The tuner 310 B, the demodulator 312 B, and the MRC 314 B are active.

With reference to FIG. 3A through FIG. 3B , FIG. 3C illustrates the block diagram of the multi-chip antenna diversity architecture 300 C when only the slave chip 304 A is powered ON according to a third embodiment herein. In one embodiment, when only the slave chip 304 A is powered ON, then the clock PLL 306 A, the crystal oscillator 308 A, the power sequencer 316 A-B, the MRC 314 A, and the Diversity State Machine 318 A-B are powered ON. In another embodiment, the functions of the crystal oscillator 308 A, and the MRC 314 A are disabled or powered OFF as shown in FIG. 3C . The MRC 314 B, the clock PLL 306 A, the tuner 310 A, and the demodulator 312 A are active.

If the channel conditions are adequate for a single chip (e.g., the master chip 304 B, or the slave chip 304 A) to receive error free audio/video data, then the DSM 318 B powers down either the master chip 304 B or the slave chip 304 A. This occurs to allow the final audio/video data to always be transmitted from the master chip 304 B. The DSM 318 B determines the receiver chip (e.g., the master chip 304 B, or the slave chip 304 A) to power down based on channel conditions (e.g., or channel metrics). The channel metric may be one or more of a Signal-to-Noise Ratio (SNR), a Bit Error Rate (BER), a Packet Error Rate (PER), and a Received Signal Strength Indication (RSSI).

FIG. 4 illustrates a graphical representation 400 of the received Signal-to-Noise Ratio (SNR) while the receiver chips are operated by the DSM 318 B of FIG. 3A according to a first embodiment herein. The SNR is plotted on the y-axis over a period of time plotted on the x-axis. With reference to FIG. 4 , FIG. 5 illustrates a graphical representation 500 of the operating states (OS) of the DSM 318 B of FIG. 3A according to an embodiment herein. The operating state of the DSM 318 B is plotted on the y-axis and the time period is plotted on x-axis. In an example embodiment, the graphical representation of FIG. 5 illustrates when the value of the operating state of the DSM 318 B is 1, then both the master chip 304 B and the slave chip 304 A are powered ON.

In one example embodiment, both the master chip 304 B and the slave chip 304 A are powered ON if a value of the channel metrics is below a threshold value. In another example embodiment, when the value of the operating state of the DSM 318 B is 2, then only the master chip 304 B is powered ON and the slave chip 304 A is powered OFF. In yet another example embodiment, when the value of the operating state of the DSM 318 B is 3, then the master chip 304 B is powered OFF and the slave chip 304 A is powered ON. In one example, either the master chip 304 B or the slave chip 304 A is powered OFF if the value of the channel metric exceeds the threshold value. In one embodiment, the master chip 304 B or the slave chip 304 A is powered OFF when the value of the channel metric exceeds a predetermined threshold value. The master chip 304 B or the slave chip 304 A is powered OFF if the channel conditions are adequate for at least one of the master chip 304 B or the slave chip 304 A to receive an error free audio/video data.

FIG. 4 illustrates a graphical representation of a received Signal-to-Noise Ratio (SNR) being operated by the DSM of FIGS. 3A through 3C , over a period of time according to an embodiment herein. Between time period starting from t=220 to t=270, the DSM state is recorded as 2 which implies only the master chip is powered ON due to a higher SNR in the corresponding time interval. Time period starting from t=400 to t=510, a low SNR as depicted in FIG. 4 , the operating state of the DSM is recorded as 1. After time t=540, the operating state of the DSM is recorded as 2 which implies only the master chip is powered ON and the signal quality improves corresponding to a higher SNR as depicted in the FIG. 4 .

With reference to FIG. 4 and FIG. 5 , FIG. 6 illustrates a graphical representation 600 of a Packet Error Rate (PER) for a single chip according to an embodiment herein. Packet Error Rate tests the performance of the receiver chip receiving signals from the antenna. With reference to FIG. 4 through FIG. 6 , FIG. 7 illustrates a graphical representation 700 of a PER after MRC combining according to an embodiment herein. The signals received from the antenna are combined and received by the receiver chip to reduce the PER after the MRC combining.

FIG. 8 , with reference to FIGS. 2 through 7 , is a flow diagram illustrating a method of operating a multi-chip antenna diversity architecture 200 of FIG. 2 to optimize antenna diversity and power consumption based on channel conditions according to an embodiment herein. The multi-chip antenna diversity architecture 200 includes a master chip 204 B that includes a chip pin operatively connected to V DD . The master chip 204 B receives a first input signal from a first antenna. A slave chip 204 A that includes a chip pin operatively connected to V SS . The slave chip 204 A receives a second input signal from a second antenna. In step 802 , the master chip 204 B and the slave chip 204 A are powered ON when a value of at least one channel metric of the multi-chip antenna diversity architecture 200 is below a threshold value. In step 804 , the master chip 204 B or the slave chip 204 A is powered OFF when the value of the channel metrics of the multi-chip antenna diversity architecture 200 exceeds the threshold value.

The master chip 204 B or the slave chip 204 A is powered OFF if the channel conditions allow for at least one of the master chip 204 B and the slave chip 204 A to receive error free audio/video data. The channel conditions may be any of the SNR, a bit error rate (BER), a packet error rate (PER), and a received signal strength indication (RSSI). A Diversity State Machine (DSM) may be used to automatically power down the master chip 204 B or the slave chip 204 A.

In the multi-chip diversity architecture 300 A- 300 C, antenna diversity and power consumption are optimized based on the quality of signal. Powering OFF any of the master chip 304 B or the slave chip 304 A is based on channel conditions. The DSM 318 B of the multi-chip diversity architecture 300 A- 300 C controls the transitions, thus eliminating a need of an external processor. The audio/video data is always transmitted from the master chip 304 B. There are no audio/video glitches when any of the chips (e.g., the master chip 304 B, or the slave chip 304 A) is powered ON/OFF. In addition, the communication between the master chip 304 B and the slave chip 304 A may be bi-directional. The output from the crystal oscillator 308 B of the master chip 304 B is transmitted to the slave chip 304 A such that the digital clocks of both the chips (the master chip 304 B and the slave chip 304 A) are frequency synchronized. Further, digital power is removed to eliminate majority of CMOS leakage power.

The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.