Liquid crystal display, method of driving the same, and method of manufacturing the same

This application claims priority to Korean Patent Application No. 2010-37536, filed on Apr. 22, 2010, and all the benefits accruing therefrom under 35 U.S.C. §119, the content of which in its entirety is herein incorporated by reference.

1. Field of the Invention

The present invention generally relates to a liquid crystal display with substantially improved light transmittance and lateral visibility, a method of driving the liquid crystal display, and a method of manufacturing the liquid crystal display.

2. Description of the Related Art

To overcome a narrow viewing angle of a liquid crystal display (“LCD”), various modes for the LCD, such as a patterned vertical alignment (“PVA”) mode in which liquid crystal molecules are aligned in a vertical direction, a multi-domain vertical alignment (“MVA”) mode in which the liquid crystal molecules are aligned in various directions in a pixel, and a super-patterned vertical alignment (“S-PVA”) mode, and various other modes have been developed.

In the S-PVA mode LCD, one pixel typically includes two sub-pixels to which different sub-voltages are applied, respectively. Since human eyes looking at the LCD only recognize an intermediate value between the two sub-voltages each applied to the sub-pixels of the one pixel, respectively, a lateral visibility is substantially improved.

Exemplary embodiments of the present invention provide a liquid crystal display (LCD) with an improved lateral visibility.

Exemplary embodiments of the present invention provide a method of driving the LCD.

Exemplary embodiments of the present invention provide a method of manufacturing the LCD.

Exemplary embodiment of an LCD includes a plurality of pixels, and each pixel of the plurality of pixels includes a gate line, a data line, a first sub-pixel, a second sub-pixel, a resistor, and a first sharing capacitor. In one exemplary embodiment, the LCD further includes a second sharing capacitor.

The first sub-pixel includes a first transistor connected to the gate line and the data line to output the data voltage in response to the gate signal and a first liquid crystal capacitor connected to the first transistor to receive the data voltage output from the first transistor. The second sub-pixel includes a second transistor to receive the data voltage output from the first transistor. The second sub-pixel includes a second transistor connected to the gate line and the data line to output the data voltage in response to the gate signal and a second liquid crystal capacitor connected to the second transistor to receive the data voltage output from the second transistor.

The resistor is connected in parallel with the second liquid crystal capacitor and receives the data voltage output from the second transistor. The first sharing capacitor is connected to the resistor to receive the data voltage through the resistor. In one exemplary embodiment, the second sharing capacitor is connected between the first sharing capacitor and the first liquid crystal capacitor and increases a voltage level of the first pixel voltage by a voltage coupling.

Exemplary embodiment of an LCD includes an array substrate including a first base substrate and a plurality of pixels disposed on the first base substrate, an opposite substrate including a second base substrate opposite to the first base substrate and a common electrode disposed on the second base substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate.

The array substrate includes a gate line receiving a gate signal, a data line receiving a data voltage, and a first transistor and a second transistor each connected to the gate line and the data line to output the data voltage in response to the gate signal. In addition, the array substrate includes a first pixel electrode connected to the first transistor to receive the data voltage output from the first transistor, a second pixel electrode connected to the second transistor to receive the data voltage output from the second transistor and spaced apart from the first pixel electrode, a resistor connected to the second transistor to receive the data voltage output from the second transistor, a first coupling electrode connected to the resistor to receive the data voltage through the resistor, and a first cap electrode opposite to the first coupling electrode.

Exemplary embodiment of a method of driving an LCD is provided as follows. The data voltage provided through the data line is output through the first and second transistors during a period of a high gate signal provided through the gate line. When the data voltage is received, the first liquid crystal capacitor is charged with a first pixel voltage and the second liquid crystal capacitor is charged with a second pixel voltage having a same voltage level as the first pixel voltage.

After the period of the high gate signal, an electric charge is shared by a first sharing capacitor and the second liquid crystal capacitor, which are connected to the resistor to allow the second pixel voltage charged in the second liquid crystal capacitor to be lower than the first pixel voltage by the electron sharing.

Additionally, after the period of the high gate signal, the first pixel voltage charged in the first liquid crystal capacitor increases by a second sharing capacitor connected between the first sharing capacitor and the first liquid crystal capacitor.

Exemplary embodiments of a method of manufacturing an LCD is provided as follows. An array substrate, an opposite substrate, and a liquid crystal layer are formed.

Particularly, the array substrate including a first base substrate on which a plurality of pixel areas is disposed is formed. First, a first transistor, a second transistor, and a first cap electrode are formed in each pixel area of the plurality of pixel areas, and a resistor connected to the second transistor is formed. Then, a first coupling electrode connected to the second transistor through the resistor and opposite to the first cap electrode is formed. In addition, a first pixel electrode connected to the first transistor and a second pixel electrode connected to the second transistor are formed.

A common electrode is formed on a second base substrate to form the opposite substrate. Then, a liquid crystal layer is formed between the array substrate and the opposite substrate.

According to above, a difference in voltages applied to the two sub-pixels is generated by using the resistor and the capacitor in each pixel of the plurality of pixels without using an additional switching device. Thus, a parasitic capacitance may be reduced and an aperture ratio may be substantially improved when compared to using the additional switching device. Also, the resistor includes amorphous silicon on the same layer as the active layer, therefore, additional processes are not necessary.

The above and other advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIG. 1 is an equivalent circuit diagram showing an exemplary embodiment of a pixel included in a liquid crystal display (“LCD”) according to the present invention;

FIGS. 2A and 2B are circuit diagrams showing an operation of a circuit of FIG. 1 in response to a gate signal;

FIG. 2C is a timing diagram showing a change of first and second pixel voltages according to the gate signal;

FIG. 3 is an equivalent circuit diagram showing another exemplary embodiment of a pixel of an LCD according to the present invention;

FIGS. 4A and 4B show circuit diagram showing an operation of the exemplary embodiment of a circuit of FIG. 3 in response to a gate signal;

FIG. 4C is a timing diagram showing a change of first and second pixel voltages according to the gate signal;

FIG. 5 is a top plan view showing the exemplary embodiment of a pixel of FIG. 1 ;

FIG. 6A is a cross-sectional view taken along line I-I′ of FIG. 5 ;

FIG. 6B is a cross-sectional view taken along line II-II′ of FIG. 5 ;

FIG. 7 is a top plan view showing a pixel of FIG. 3 ;

FIG. 8 is a cross-sectional view taken along line III-III′ of FIG. 7 ; and

FIGS. 9A to 9G are cross-sectional views showing an exemplary embodiment of a method of manufacturing an exemplary embodiment of an LCD according to the present invention.

The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms, “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes” and/or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments of the present invention are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. More over, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.

All methods described herein can be performed in a suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”), is intended merely to better illustrate the disclosure and does not pose a limitation on the scope thereof unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the embodiments as used herein.

Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 is an equivalent circuit diagram showing an exemplary embodiment of a liquid crystal display (“LCD”) according to the present invention.

In FIG. 1 , an equivalent circuit diagram showing an exemplary embodiment of one pixel among a plurality of pixels disposed on an LCD in a matrix configuration has been illustrated. Since the plurality of pixels may have a substantially similar structure and function as each other, for the convenience of explanation, one pixel will be described in detail and detailed descriptions of other pixels may be omitted.

Referring to FIG. 1 , an exemplary embodiment of a pixel 100 includes a gate line GL, a data line DL, a first sub-pixel P 1 , a second sub-pixel P 2 , a resistor R 1 , and a first sharing capacitor Cs 1 . The first sub-pixel P 1 includes a first transistor TR 1 and a first liquid crystal capacitor Clc_ 1 , and the second sub-pixel P 2 includes a second transistor TR 2 and a second liquid crystal capacitor Clc_ 2 . In one exemplary embodiment, the transistors may be thin-film transistors (“TFTs”).

Each of the first transistor TR 1 and the second transistor TR 2 is connected to the gate line GL and the data line DL to output a data voltage in response to a gate signal. The first liquid crystal capacitor Clc_ 1 is connected to the first transistor TR 1 to receive the data voltage output from the first transistor TR 1 and is charged with a first pixel voltage Vp 1 .

The second liquid crystal capacitor Clc_ 2 is connected to the second transistor TR 2 to receive the data voltage output from the second transistor TR 2 and is charged with a second pixel voltage Vp 2 .

The resistor R 1 receives the data voltage output from the second transistor TR 2 . The first sharing capacitor Cs 1 is connected to the resistor R 1 and receives the data voltage through the resistor R 1 .

FIGS. 2A and 2B are circuit diagrams showing an operation of the circuit of FIG. 1 in response to the gate signal, and FIG. 2C is a timing diagram showing a change of the first and second pixel voltages Vp 1 and Vp 2 according to the gate signal.

Referring to FIGS. 2A and 2C , the first liquid crystal capacitor Clc_ 1 and the second liquid crystal capacitor Clc_ 2 receive the data voltage to charge the first pixel voltage Vp 1 and the second pixel voltage Vp 2 , respectively, during a high period 1 H of the a gate signal Gs. Since the first sharing capacitor Cs 1 does not receive the data voltage during the period 1 H, the second pixel voltage Vp 2 has a same voltage level as the first pixel voltage Vp 1 .

Referring to FIGS. 2B and 2C , the first sharing capacitor Cs 1 is connected to the second liquid crystal capacitor Clc_ 2 after the period 1 H. Since no voltage is applied to the first sharing capacitor Cs 1 and the second liquid crystal capacitor Clc_ 2 from other sources, the first sharing capacitor Cs 1 and the second liquid crystal capacitor Clc_ 2 share an electric charge. Thus, the second pixel voltage Vp 2 has a voltage level that is lower than the first pixel voltage Vp 1 after the high period 1 H of the gate signal Gs. As described above, the first sub-pixel P 1 and the second sub-pixel P 2 are charged with different voltages and a user recognizes an intermediate value of the first pixel voltage Vp 1 and the second pixel voltage Vp 2 , thereby a lateral viewing angle of an LCD is substantially improved.

The first sharing capacitor Cs 1 is connected to the second liquid crystal capacitor Clc_ 2 after the period 1 H by the resistor R 1 . This is possible to impart the beneficial characteristics of a circuit which is composed of a resistor and a capacitor. More particularly, in a circuit composed of a resistor and a capacitor, a response time period for changing an output voltage or a current in response to an input voltage or a current may be adjusted according to the characteristics of the resistor and the capacitor. The response time period is referred to as a time constant, and a time constant of the second sub-pixel P 2 is as follows.

Rcdelay= R ×( ClcB+Cs )  <Equation 1>

In Equation 1, RCdelay represents the time constant of the second sub-pixel P 2 , ClcB represents a charge capacitance of the second liquid crystal capacitor Clc_ 2 , Cs represents a charge capacitance of the first sharing capacitor Cs 1 , and R represents a resistance value of the resistor R 1 .

In case that the time constant is longer than the high period 1 H of the gate signal Gs, the data voltage is not applied to the first sharing capacitor Cs 1 during the high period 1 H, and thus the first sharing capacitor Cs 1 is not charged. However, when the time constant is longer than a time period required to display one frame image, the first and second transistors TR 1 and TR 2 are turned on before the first sharing capacitor Cs 1 and the second liquid crystal capacitor Clc 2 share the electric charge. Therefore, the second liquid crystal capacitor Clc_ 2 does not share the electric charge with the first sharing capacitor Cs 1 . Consequently, the resistance value of the resistor R 1 may satisfy Equation 2 as follows.

1 H /( ClcB+Cs )< R< 1 F /( ClcB+Cs )  <Equation 2>

In Equation 2, 1 H represents the period 1 H of the high gate signal of Gs, and 1 F represents the time period required to display one frame image. In one exemplary embodiment, with reference to a 40-inch LCD TV (as measured across the diagonal thereof), the resistor R 1 has a resistance value within a range of 14 MΩ(14e6)<R<16 GΩ(16e9).

FIG. 3 is an equivalent circuit diagram showing another exemplary embodiment of a pixel of an LCD according to the present invention. In FIG. 3 , an exemplary embodiment of a pixel 200 has substantially the same structure and function as the pixel 100 of FIG. 1 except that the pixel 200 further includes a second sharing capacitor Cs 2 . Thus, detailed descriptions of elements of the pixel 200 which are similar to those previously described may be omitted.

Referring to FIG. 3 , the second sharing capacitor Cs 2 is connected between a first sharing capacitor Cs 1 and a first liquid crystal capacitor Clc_ 1 . In other words, the second sharing capacitor Cs 2 is connected to a first node N 1 and a third node N 3 . The second sharing capacitor Cs 2 increases a first pixel voltage Vp 1 charged in the first liquid crystal capacitor Clc_ 1 by a voltage coupling after a high period 1 H of a gate signal Gs.

FIGS. 4A and 4B are circuit diagram showing an operation of the circuit of FIG. 3 in response to a gate signal, and FIG. 4C is a timing diagram showing a change of the first and second pixel voltages according to the gate signal.

Referring to FIGS. 4A and 4C , the first sharing capacitor Cs 1 and the second sharing capacitor Cs 2 are connected to each other in series with reference to the first node N 1 during the high period of the gate signal Gs, and the first and second sharing capacitors Cs 1 and Cs 2 connected to each other in series are connected with the first liquid crystal capacitor Clc_ 1 in parallel.

The first liquid crystal capacitor Clc_ 1 receives the data voltage during the period 1 H to charge the first pixel voltage Vp 1 . Similarly, the first sharing capacitor Cs 1 and the second sharing capacitor Cs 2 are charged with a portion of the first pixel voltage Vp 1 in inverse proportion to the charge capacitance thereof, respectively. Also, the second liquid crystal capacitor Clc_ 2 receives the data voltage to charge a second pixel voltage Vp 2 having substantially the same voltage level as the first pixel voltage Vp 1 during the period 1 H.

Referring to FIGS. 4B and 4C , the second liquid crystal capacitor Clc_ 2 and the first sharing capacitor Cs 1 are connected to each other in parallel with reference to the third node N 3 after the period 1 H.

Since no voltage is applied to the first sharing capacitor Cs 1 and the second liquid crystal capacitor Clc_ 2 from other sources after the period 1 H, the second liquid crystal capacitor Clc_ 2 and the first sharing capacitor Cs 1 share an electric charge to decrease the second pixel voltage Vp 2 . Thus, the voltage level of the voltage charged in the first sharing capacitor Cs 1 increases according to the decrease of the second pixel voltage Vp 2 . Also, the second sharing capacitor Cs 2 is charged with a substantially similar voltage level as that of the first sharing capacitor Cs 1 due to a voltage coupling, thereby increasing the first pixel voltage Vp 1 . Consequently, the exemplary embodiment of the pixel 200 shown in FIG. 3 may have substantially improved light transmittance compared to the light transmittance of the exemplary embodiment of the pixel 100 shown in FIG. 1 .

FIG. 5 is a top plan view showing the pixel of FIG. 1 , FIG. 6A is a cross-sectional view taken along line I-I′ of FIG. 5 , and FIG. 6B is a cross-sectional view taken along line II-II′ of FIG. 5 .

Referring to FIGS. 5 to 6B , an LCD includes an array substrate 110 , an opposite substrate 120 facing the array substrate 110 , and a liquid crystal layer 130 disposed between the array substrate 110 and the opposite substrate 120 . The array substrate 110 includes a first base substrate 111 and a plurality of pixels disposed on the first base substrate 111 . Since the pixels have a substantially similar structure and function as each other, for the convenience of explanation, one pixel 101 will be described in detail, and detailed descriptions of other pixels may be omitted.

Referring to FIG. 5 , the pixel 101 includes a gate line GL and a data line DL. The gate line GL extends in a first direction D 1 , the data line DL extends in a second direction D 2 that is substantially perpendicular to the first direction D 1 , and the data line DL is insulated from the gate line GL while crossing the gate line GL. In one exemplary embodiment, the pixel 101 further includes a storage line SL receiving a storage voltage and disposed substantially in parallel with the gate line GL.

In addition, the pixel 101 includes the first and second transistors TR 1 and TR 2 , a first pixel electrode PE 1 , a first coupling electrode CE 1 , a second pixel electrode PE 2 , a resistor R 1 , and a first cap electrode CA 1 . In the present exemplary embodiment, the first and second transistors TR 1 and TR 2 are disposed adjacent to each other.

The first transistor TR 1 includes a first gate electrode GE 1 branched from the gate line GL, a first source electrode SE 1 branched from the data line DL, and a first drain electrode DE 1 spaced apart from the first source electrode SE 1 with a predetermined interval on the first gate electrode GE 1 . An active layer 113 is formed between the first gate electrode GE 1 and the first source electrode SE 1 and the first drain electrode DE 1 . The second transistor TR 2 includes a second gate electrode GE 2 branched from the gate line GL, a second source electrode SE 2 branched from the data line DL, and a second drain electrode DE 2 spaced apart from the second source electrode SE 2 with a predetermined interval on the second gate electrode GE 2 . The active layer 113 is also disposed between the second gate electrode GE 2 and the second source electrode SE 2 and the second drain electrode DE 2 .

The second drain electrode DE 2 is electrically connected to the resistor R 1 and partially covers the resistor R 1 . The first coupling electrode CE 1 is connected to the resistor R 1 and spaced apart from the second drain electrode DE 2 above the resistor R 1 . The first cap electrode CA 1 is disposed in an area where the storage line SL is extended and the first cap electrode CA 1 is disposed substantially opposite to the first coupling electrode CE 1 . The first coupling electrode CE 1 and the first cap electrode CA 1 form the first sharing capacitor Cs 1 .

The resistor R 1 includes a material having a conductivity but the material included in the resistor R 1 should not be limited to a metal material. In the present exemplary embodiment, the resistor R 1 includes an amorphous silicon and is formed on the same layer as the active layer 113 . The resistance value of the resistor R 1 may be changed in response to exposure to a light provided to the array substrate 110 . More particularly, the resistor R 1 includes the amorphous silicon having light transmission property as its photoconductivity is enhanced to transmit an electric charge when the amorphous silicon is exposed to the light. As an example, the light is provided from a backlight unit (not shown) included in the LCD.

The first pixel electrode PE 1 and the second pixel electrode PE 2 are disposed on a protective layer 114 and spaced apart from each other by a first opening OP 1 . The first pixel electrode PE 1 is electrically connected to the first drain electrode DE 1 through a first contact hole H 1 disposed through the protective layer 114 , and the second pixel electrode PE 2 is electrically connected to the second drain electrode DE 2 through a second contact hole H 2 .

Meanwhile, the opposite substrate 120 includes a second base substrate 121 facing the first base substrate 111 and a common electrode 123 disposed on the second base substrate 121 .

The common electrode 123 is disposed on the opposite substrate 120 . The common electrode 123 faces the first and second pixel electrodes PE 1 and PE 2 while the liquid crystal layer 130 is disposed therebetween. Thus, the common electrode 123 and the first pixel electrode PE 1 form the first liquid crystal capacitor Clc_ 1 , and the common electrode 123 and the second pixel electrode PE 2 form the second liquid crystal capacitor Clc_ 2 .

The common electrode 123 is provided with a second opening OP 2 formed therethrough to divide an area where the first and second pixel electrodes PE 1 and PE 2 are formed into a plurality of domains. Liquid crystal molecules of the liquid crystal layer 130 in one domain of the plurality of domains may be aligned in different directions from liquid crystal molecules of the liquid crystal layer 130 in another domain of the plurality of domains. In one exemplary embodiment, the second opening OP 2 may be desirable to be positioned at a center portion of each of the first and second pixel electrodes PE 1 and PE 2 in order to improve the number and/or arrangement of the plurality of domains.

FIG. 7 is a top plan view showing the exemplary embodiment of a pixel of FIG. 3 , and FIG. 8 is a cross-sectional view taken along line III-III′ of FIG. 7 .

In FIGS. 7 and 8 , a pixel 201 has a substantially similar structure and function as the pixel 101 shown in FIGS. 5 , 6 A, and 6 B except that the pixel 201 further includes a second coupling electrode CE 2 and a second cap electrode CA 2 . Thus, the same reference numerals denote the same elements in FIGS. 5 , 6 A, and 6 B, and thus the detailed descriptions of the same elements may be omitted.

Referring to FIGS. 7 and 8 , the second coupling electrode CE 2 is integrally formed with the first coupling electrode CE 1 . The second cap electrode CA 2 is integrally formed with the first pixel electrode PE 1 and disposed opposite to the second coupling electrode CE 2 . Therefore, the second coupling electrode CE 2 and the second cap electrode CA 2 form the second sharing capacitor Cs 2 .

FIGS. 9A to 9G are cross-sectional views showing an exemplary embodiment of a method of manufacturing an exemplary embodiment of an LCD according to the present invention. In the present exemplary embodiment, the first and second transistors TR 1 and TR 2 , the resistor R 1 , the first cap electrode CA 1 , and the first coupling electrode CE 1 may be formed through the following processes.

Referring to FIG. 9A , a gate metal layer is formed on the first base substrate 111 , and the gate metal layer is patterned to form the first gate electrode GE 1 , the second gate electrode GE 2 , and the first cap electrode CA 1 . In the exemplary embodiment, the first and second gate electrodes GE 1 and GE 2 are integrally formed with each other, although alternative exemplary embodiments include alternative configurations.

Referring to FIG. 9B , a gate insulating layer 112 is deposited on the first base substrate 111 to cover the first and second gate electrodes GE 1 and GE 2 and the first cap electrode CA 1 .

Referring to FIG. 9C , the active layer 113 is formed on the gate insulating layer 112 corresponding to an area where the first and second gate electrodes GE 1 and GE 2 are formed. The resistor R 1 is formed on the gate insulating layer 112 , similar to the active layer 113 . In one exemplary embodiment, the resistor R 1 may be substantially simultaneously formed with the active layer 113 .

Referring to FIG. 9D , a data metal layer is formed on the gate insulating layer 112 on which the active layer 113 and the resistor R 1 are formed. Then, the data metal layer is patterned to form the first and second source electrodes SE 1 and SE 2 and the first and second drain electrodes DE 1 and DE 2 that are spaced apart from each other on the active layer 113 .

A portion of the second drain electrode DE 2 is extended to be formed on the resistor R 1 during the manufacturing process of the source and drain electrodes SE 1 , SE 2 , DE 1 , and DE 2 , and the first coupling electrode CE 1 is formed while being spaced apart from the second drain electrode DE 2 . The first coupling electrode CE 1 is extended to be formed in an area facing the first cap electrode CA 1 . Thus, the first and second transistors TR 1 and TR 2 , the resistor R 1 , the first cap electrode CA 1 , and the first coupling electrode CE 1 are formed on the first base substrate 111 . In one exemplary embodiment, as shown in FIGS. 7 and 8 , the second coupling electrode CE 2 may be integrally formed with the first coupling electrode CE 1 . The first sharing capacitor Cs 1 is defined by the first cap electrode CA 1 and the first coupling electrode CE 1 .

Referring to FIGS. 6A , 6 B, and 9 E, the protective layer 114 including an inorganic insulating layer such as a silicon nitride layer (SiNx), for example, is formed on the first base substrate 111 to cover the first and second transistor TR 1 and TR 2 and the first coupling electrode CE 1 . The first and second contact holes H 1 and H 2 are formed through the protective layer 114 to connect the first and second pixel electrodes PE 1 and PE 2 and the first and second drain electrodes DE 1 and DE 2 , respectively. The first contact hole H 1 is formed above the first drain electrode DE 1 , and the second contact hole H 2 is formed above the second drain electrode DE 2 .

Referring to FIGS. 6A , 6 B, and 9 F, a transparent conductive layer including an indium tin oxide (ITO) or an indium zinc oxide (IZO), or other materials with similar characteristics is formed on the protective layer 114 . Then, the transparent conductive layer is patterned to form the first and second pixel electrodes PE 1 and PE 2 that are insulated from each other. The first opening OP 1 is provided between the first pixel electrode PE 1 and the second pixel electrode PE 2 , so that the first and second pixel electrodes PE 1 and PE 2 may be spaced apart from each other.

The first pixel electrode PE 1 is electrically connected to the first drain electrode DE 1 through the first contact hole H 1 , and the second pixel electrode PE 2 is electrically connected to the second drain electrode DE 2 through the second contact hole H 2 . As shown in FIGS. 7 and 8 , in one exemplary embodiment, the second cap electrode CA 2 may be integrally formed with the first pixel electrode PE 1 .

Referring to FIGS. 6A , 6 B, and 9 G, the common electrode 123 is formed on the second base substrate 121 . As shown in FIG. 6B , the second opening OP 2 is formed through the common electrode 123 in an area corresponding to the first and second pixel electrodes PE 1 and PE 2 . In one exemplary embodiment, the second opening OP 2 may be positioned at the center portion of each of the first and second pixel electrodes PE 1 and PE 2 as discussed above.

The liquid crystal layer 130 is disposed between the array substrate 110 and the opposite substrate 120 . In one exemplary embodiment, the liquid crystal layer 130 may include vertical alignment liquid crystal molecules.

According to above descriptions, a difference in voltages applied to the two sub-pixels is generated using the resistor and the capacitor in the pixel without using an additional switching device. Thus, a parasitic capacitance may be reduced and an aperture ratio may be substantially improved when compared to an alternative configuration using the additional switching device. Also, in one exemplary embodiment, the resistor may include amorphous silicon on the same layer as the active layer 113 . Therefore, additional processes are not necessary.

Although the exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one having ordinary skill in the art within the spirit and scope of the present invention as hereinafter claimed.