Interface circuit and electronic device using the same

1. Technical Field

The present disclosure relates to electronic devices, and particularly to an electronic device with an interface circuit.

2. Description of Related Art

Electronic devices, such as DVD players, usually include an interface circuit for peripherals. The interface circuit for a DVD player may includes two output units for respectively transmitting right channel audio signals and left channel audio signals to two speakers. When one output unit connects with one speaker and the other output unit does not connect with the other speaker a signal cross-disturbance exits between the two output units, thus one of the right channel audio signals or the left channel audio signals output by the unit unconnected with the speaker will disturb the other channels output.

Therefore, there is room for improvement in the art.

The components of the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiment of an electronic device with a mute control circuit. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the views.

FIG. 1 is a functional block diagram of an electronic device including an interface circuit according to an exemplary embodiment.

FIG. 2 is a detailed circuit diagram of the interface circuit of FIG. 1 in an initial state.

FIG. 3 is a detailed circuit diagram of the interface circuit of FIG. 1 in a working state.

Embodiments of the present disclosure will now be described in detail with reference to the drawings.

Referring to FIG. 1 , an electronic device 100 according to an exemplary embodiment is illustrated. In this embodiment, the electronic device 100 is a DVD player. The electronic device 100 includes a processing unit 10 , an interface circuit 30 , and two speakers 40 .

The processing unit 10 is used for generating audio signals including a right channel audio signal and a left channel audio signal. The processing unit 10 includes a first output port 11 and a second output port 13 . The first output port 11 is used to output the left channel audio signal. The second output port 13 is used to output the right channel audio signal.

The interface circuit 30 is electrically connected to the processing unit 10 . The interface circuit 30 is used for transmitting the right channel audio signal and the left channel audio signal to the two speakers 40 when the two speakers 40 are electrically connected to the interface circuit 30 . The two speakers 40 emit sounds according to the right channel audio signal and the left channel audio signal. Each speaker 40 includes a plug 41 for electrically connecting to the interface circuit 30 . Each plug 41 includes a first input port 410 and a second input port 412 .

The interface circuit 30 includes a first output unit 21 , a second output unit 23 , a first sub-circuit 31 , a second sub-circuit 33 , a third sub-circuit 35 , and a fourth sub-circuit 37 .

The first sub-circuit 31 and the third sub-circuit 35 are the same and are both used for processing the right channel audio signal from the second output port 13 , and for generating a processed right channel audio signal.

The second sub-circuit 33 and the fourth sub-circuit 37 are the same and are both used for processing the left channel audio signal from the first output port 11 , and for generating a processed left channel audio signal.

The first output unit 21 and the second output unit 21 are the same. The first output unit 21 is used for receiving the processed right channel audio signal from the first sub-circuit 31 and the processed left channel audio signal from the second sub-circuit 33 . It is further used for transmitting the processed right channel audio signal and the processed left channel audio signal to the speaker 40 , which is electrically connected to the first output unit 21 .

The first output unit 21 includes a first pin 213 , a second pin 214 , a third pin 211 , a fourth pin 212 , a fifth pin 215 , and a first anti jam member 216 . The third pin 211 is electrically grounded. The fourth pin 212 is electrically connected to the second output port 13 by the first sub-circuit 31 . The first pin 213 is detachably and is electrically connected to the fourth pin 212 . The first pin 213 is further electrically connected to the second pin 214 by the first anti-jam member 216 . The second pin 214 is detachably and is electrically connected to the fifth pin 215 . The fifth pin 215 is further electrically connected to the first output port 11 by the second sub-circuit 33 .

When the speaker 40 is connected to the first output unit 21 , the first pin 213 is detached from the fourth pin 212 , and the second pin 214 is detached from the fifth pin 215 . The first anti-jam member 216 is in an open circuit. The fourth pin 212 is electrically connected to the second input port 412 to transfer the processed right channel audio signal. The fifth pin 215 is electrically connected to the first input port 410 to transfer the processed left channel audio signal. Thus, the first anti jam member 216 does not affect the first output unit 21 to transmit the processed right channel audio signal and the processed left channel audio signal to the speaker 40 .

When the speaker 40 is independent from the first output unit 21 , the first pin 213 is electrically connected to the fourth pin 212 , and the second pin 214 is electrically connected to the fifth pin 215 . The first anti jam member 216 is in series with the fourth pin 212 and the fifth pin 215 . Thus, the first anti jam member 216 attenuates the processed right channel audio signal and the processed left channel audio signal.

The second output unit 23 is used for receiving the processed right channel audio signal from the third sub-circuit 35 and the processed left channel audio signal from the fourth sub-circuit 37 . The second output unit 23 is further used for transmitting the processed right channel audio signal and the processed left channel audio signal to one of the speakers 40 , which is electrically connected to the first output unit 21 .

The second output unit 23 includes a sixth pin 233 , a seventh pin 234 , an eighth pin 231 , a ninth pin 232 , a tenth pin 235 , and a second anti jam member 236 . The eighth pin 231 is electrically grounded. The ninth pin 232 is electrically connected to the second output port 13 by the third sub-circuit 35 . The ninth pin 232 is further detachably and is electrically connected to the sixth pin 233 . The sixth pin 233 is electrically connected to the seventh pin 234 by the second anti jam member 236 . The seventh pin 234 is detachably and is electrically connected to the tenth pin 235 . The tenth pin 235 is further electrically connected to the first output port 11 by the fourth sub-circuit 37 .

When the speaker 40 is connected to the second output unit 23 , the ninth pin 232 is detached from the sixth pin 233 , and the tenth pin 235 is detached from the seventh pin 234 . The second anti-jam member 236 is in an open circuit. The ninth pin 232 is electrically connected to the second input port 412 to transfer the processed right channel audio signal. The tenth pin 235 is electrically connected to the first input port 410 to transfer the processed left channel audio signal. Thus, the second anti jam member 236 does not affect the second output unit 23 to transmit the processed right channel audio signal and the processed left channel audio signal to the speaker 40 .

When the speaker 40 is independent from the second output unit 23 , the ninth pin 232 is electrically connected to the sixth pin 233 , and the tenth pin 235 is electrically connected to the seventh pin 234 . The second anti jam member 236 is connected in series with the ninth pin 232 and the tenth pin 235 . Thus, the second anti jam member 236 attenuates the processed right channel audio signal and the processed left channel audio signal.

Referring to FIG. 1 again, when the first output unit 21 electrically connects with the speaker 40 , and the second output unit 23 is independent from the speaker 40 . A loop circuit will be formed by the second output port 13 , the third sub-circuit 35 , the ninth pin 232 , the sixth pin 233 , the second anti jam member 236 , the seventh pin 234 , the tenth pin 235 , the fourth sub-circuit 37 , the second sub-circuit 33 , the fifth pin 215 , the second pin 214 , and the first input port 410 . Thus, the processed right channel audio signal will reach the first input port 410 through the loop circuit. The processed left channel audio signal of the first input port 410 is disturbed. However, as the second anti jam member 236 is in series with the loop circuit, it attenuates the processed right channel audio signal. After being attenuated, the processed right channel audio signal can not affect the processed left channel audio signal of the first input port 410 .

For the same reason, the processed left channel audio signal cannot affect the processed right channel audio signal of the second input port 412 . When the second output unit 23 is connected to the speaker 40 , and the first output unit 21 is independent from the speaker 40 . The processed right channel audio signal cannot affect the processed left channel audio signal of the first input port 410 , and the processed left channel audio signal cannot affect the processed right channel audio signal of the second input port 412 .

Further referring to FIG. 2 , in this embodiment, the first anti jam member 216 is a first resistor R 1 , and the second anti jam member 236 is a second resistor R 2 .

The first sub-circuit 31 is used for transmitting the right channel signal from the second output port 13 to the fourth pin 212 of the first output unit 21 . The first sub-circuit 31 includes a third resistor R 3 , a fourth resistor R 4 , a first inductor L 1 , and a first capacitor C 1 . One end of the third resistor R 3 is electrically connected to the second output port 13 , and the other end of the third resistor R 3 is electrically connected to the fourth pin 212 by the first inductor L 1 . One end of the fourth resistor R 4 is electrically connected between the third resistor R 3 and the first inductor L 1 , and the other end of the fourth resistor R 4 is electrically grounded. One end of the first capacitor C 1 is electrically connected to the fourth pin 212 , and the other end of the first capacitor C 1 is electrically grounded. The third resistor R 3 , the first inductor L 1 , and the first capacitor C 1 define a RLC filtering circuit for filtering signals. The fourth resistor R 4 is a pull down voltage resistor.

The second sub-circuit 33 is used for transmitting the left channel signal from the first output port 11 to the second pin 214 of the first output unit 21 . The second sub-circuit 33 includes a fifth resistor R 5 , a sixth resistor R 6 , a second inductor L 2 , and a second capacitor C 2 . One end of the fifth resistor R 5 is electrically connected to the first output port 11 , and the other end of the fifth resistor R 5 is electrically connected to the fifth pin 215 by the second inductor L 2 . One end of the sixth resistor R 6 is electrically connected between the fifth resistor R 5 and the second inductor L 2 , and the other end of the sixth resistor R 6 is electrically grounded. One end of the second capacitor C 2 is electrically connected to the fifth pin 215 , and the other end of the second capacitor C 2 is electrically grounded. The fifth resistor R 5 , the second inductor L 2 , and the second capacitor C 2 define a RLC filtering circuit for filtering signals. The sixth resistor R 6 is a pull down voltage resistor.

The third sub-circuit 35 is used for transmitting the right channel signal from the second output port 13 to the sixth pin 233 of the second output unit 23 . The third sub-circuit 35 includes a seventh resistor R 7 , an eighth resistor R 8 , a third inductor L 3 , and a third capacitor C 3 . One end of the seventh resistor R 7 is electrically connected to the second output port 13 , and the other end of the seventh resistor R 7 is electrically connected to the ninth pin 232 by the third inductor L 3 . One end of the eighth resistor R 8 is electrically connected between the seventh resistor R 7 and the third inductor L 3 , and the other end of the eighth resistor R 8 is electrically grounded. One end of the third capacitor C 3 is electrically connected to the ninth pin 232 , and the other end of the third capacitor C 3 is electrically grounded. The seventh resistor R 6 , the third inductor L 3 , and the third capacitor C 3 define a RLC filtering circuit for filtering signals. The eighth resistor R 8 is a pull down voltage resistor.

The fourth sub-circuit 37 is used for transmitting the left channel signal from the first output port 11 to the seventh pin 234 of the second output unit 23 . The fourth sub-circuit 33 includes a ninth resistor R 9 , a tenth resistor R 10 , a fourth inductor L 4 , and a fourth capacitor C 4 . One end of the ninth resistor R 9 is electrically connected to the first output port 11 , and the other end of the ninth resistor R 9 is electrically connected to the tenth pin 235 by the fourth inductor L 4 . One end of the tenth resistor R 10 is electrically connected between the ninth resistor R 9 and the fourth inductor L 4 , and the other end of the tenth resistor R 10 is electrically grounded. One end of the fourth capacitor C 4 is electrically connected to the tenth pin 235 , and the other end of the fourth capacitor C 4 is electrically grounded. The ninth resistor R 9 , the fourth inductor L 4 , and the fourth capacitor C 4 define a RLC filtering circuit for filtering signals. The tenth resistor R 10 is a pull down voltage resistor.

The third resistor R 3 , the fifth resistor R 5 , the seventh resistor R 7 , and the ninth resistor R 9 have the same resistance. Each resistance of the first resistor R 1 and the second resistor R 2 is far greater than that of the third resistor R 3 . In this embodiment, each resistance of the first resistor R 1 and the second resistor R 2 is about 3 to 10 times the third resistor R 3 .

Further referring to FIG. 3 , when the first output unit 21 is connected to the speaker 40 , and the second output unit 23 is independent from the speaker 40 , the first anti jam member 216 is in an open circuit, and the second anti jam member 236 is in series with the ninth pin 232 and the tenth pin 215 . The fourth pin 212 is electrically connected to the second input port 412 . The fifth pin 215 is electrically connected to the first input port 410 . As the second resistor R 2 has a great resistance, the second resistor R 2 attenuates the processed right channel audio signal to the first input port 410 or attenuates the processed left channel audio signal to the second input port 412 .

As discussed above, when only one speaker 40 is connected to one of the first output units 21 and the second output unit 23 of the electronic device 100 , the first output unit 21 and the second output unit 23 connected to the speaker 40 will not be affected by the other first output unit 21 and the second output unit 23 . Cross talk between the processed left channel audio signal and the processed right channel audio signal is reduced.

While various exemplary and preferred embodiments have been described, it is to be understood that the disclosure is not limited thereto. To the contrary, various modifications and similar arrangements (as would be apparent to those skilled in the art) are intended to also be covered. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.