Solid-state imaging device and frame data correcting method

The present invention relates to a solid-state imaging device comprising a plurality of photodetecting sections two-dimensionally arranged, and a frame data correcting method of correcting frame data outputted from the solid-state imaging device.

As a solid-state imaging device, those using the CMOS technique are known, and among these, a passive pixel sensor (PPS) type solid-state imaging device is known (see Patent Document 1). The PPS type solid-state imaging device has a structure in which PPS type pixel portions, each including a photodiode for generating charges of an amount corresponding to an incident light intensity, are arranged two-dimensionally in M rows and N columns. In each pixel portion, charges generated in the photodiode in response to light incidence are accumulated in a capacitive element of an integrating circuit, and a voltage value corresponding to the accumulated charge amount is outputted.

In general, output terminals of M pixel portions belonging to each column are connected to an input terminal of an integrating circuit provided corresponding to the column via a reading-out wiring provided corresponding to the column. In order from the first row to the M-th row, charges generated in the photodiodes of the pixel portions are inputted into the corresponding integrating circuit via the corresponding reading-out wiring, and a voltage value corresponding to the amount of charges is outputted from the integrating circuit.

The N pixel portions belonging to each row are respectively connected to a controlling section via a row selecting wiring provided corresponding to the row. According to a row selecting controlling signal transmitted from the controlling section via the row selecting wiring, the pixel portions output charges generated in the photodiodes to the reading-out wirings.

The PPS type solid-state imaging device is used for various purposes. For example, a PPS type solid-state imaging device is combined with a scintillator panel and used as an X-ray flat panel for a medical purpose or an industrial purpose. Further, a PPS type solid-state imaging device is used in an X-ray CT apparatus and a micro-focus X-ray inspection apparatus, etc. The solid-state imaging device to be used for these purposes comprises a large-area photodetecting section including M×N pixel portions two-dimensionally arrayed, and the photodetecting section may be integrated on a semiconductor substrate each side of which has a length over 10 cm. Therefore, in some cases, only one solid-state imaging device is produced from one semiconductor wafer.

Patent Document 1: Japanese Laid-Open Patent Application No. 2006-234557

Problems that the Invention is to Solve

The present inventors have examined conventional solid-state imaging device, and as a result, have discovered the following problems. That is, in a conventional solid-state imaging device, when a row selecting wiring corresponding to any one of the rows is disconnected in the middle of production, among N pixel portions belonging to this row, pixel portions positioned closer to the controlling section than the disconnection point are left connected to the controlling section by the row selecting wiring, however, the pixel portions farther from the controlling section than the disconnection point are disconnected from the controlling section.

Particularly, in a conventional solid-state imaging device, charges generated in photodiodes in response to light incidence in pixel portions positioned farther from the controlling section than the disconnection point are not reading-out to the integrating circuit, and are just accumulated in junction capacitance portions of the photodiodes. When the amount of charges accumulated in the junction capacitance portion of the photodiode exceeds a saturation level, charges over the saturation level overflow to the neighboring pixel portions.

Therefore, in a conventional solid-state imaging device, when one row selecting wiring is disconnected, this disconnection influences not only the pixel portions of the row connected to this row selecting wiring but also pixel portions of both rows neighboring the disconnected row, and eventually, pixel portions of consecutive three rows become defective lines.

On the other hand, when the defective lines are not consecutive and lines neighboring one defective line are normal lines, pixel data of the defective line can be interpolated by using pixel data of these neighboring normal lines. However, when pixel portions of consecutive three rows become defective lines, such interpolation is difficult. In particular, a solid-state imaging device having a photodetecting section with a large area as described above has a higher probability of disconnection due to long row selecting wirings.

In Patent Document 1 described above, a technique intended to solve this problem is proposed. That is, in accordance with the technique proposed in Patent Document 1, an average of all pixel data of a neighboring line neighboring a defective line and an average of all pixel data of further neighboring several normal lines are obtained. When a difference between these two averages is not less than a predetermined value, the neighboring line is also determined as defective and pixel data of the neighboring line is corrected, and further, based on the values after correction of the pixel data of the neighboring line, pixel data of the defective line is corrected.

In accordance with the technique proposed in Patent Document 1, at the time of correcting the pixel data of the neighboring line determined as defective, an average of two pixel data on normal lines on both sides of and nearest the neighboring line is obtained, and this average is set as pixel data of the neighboring line. At the time of correcting the pixel data of the defective line, an average of two pixel data on neighboring lines on both sides of the defective line is obtained, and this average is set as pixel data of the defective line.

However, in accordance with the technique proposed in Patent Document 1, processing of obtaining an average of two pixel data is repeated a plurality of times to correct pixel data of a defective line (and a line near the defective line and determined as defective), so that the resolution lowers near the defective line in a corrected image.

The present invention has been developed to eliminate the problems described above. It is an object of the present invention to provide a solid-state imaging device having a structure for making it possible to obtain an image with higher resolution by properly correcting pixel data even when any of the row selecting wirings disposed inside a photodetecting section is disconnected, and a frame data correcting method.

Means for Solving the Problems

A solid-state imaging device according to the present invention comprises: a photodetecting section including M×N pixel portions P 1,1 to P M,N two-dimensionally arrayed so as to constitute a matrix with M (integer not less than 2) rows and N (integer not less than 2) columns; a reading-out wiring L O,n connected to reading-out switches included in M pixel portions P 1,n to P M,n belonging to the n (integer not less than 1 and not more than N)-th column in the photodetecting section; a signal reading-out section connected to the reading-out wirings L O,1 to L O,N ; a controlling section controlling a voltage value output operation in the signal reading-out section by controlling opening and closing operations of the reading-out switches included in N pixel portions P m,1 to P m,N belonging to the m (integer not less than 1 and not more than M)-th row in the photodetecting section; and a row selecting wiring L V,m connected to reading-out switches included in N pixel portions P m,1 to P m,N belonging to the m-th row in the photodetecting section. The photodetecting section, the reading-out wiring L O,n , the signal reading-out section, the controlling section, and the row selecting wiring L V,m constitute one sensor element.

Each of the pixel portions P 1,1 to P M,N , which constitute the photodetecting section, includes a photodiode which generates charges of an amount corresponding to an incident light intensity, and a reading-out switch connected to the photodiode. The reading-out wiring L O,n reads out charges generated in a photodiode included in any one of the pixel portions P 1,n to P M,n via a corresponding reading-out switch. The signal reading-out section temporarily holds voltage values corresponding to the amounts of charges inputted through the reading-out wirings L O,n , and then successively outputs the held voltage values. The controlling section makes the signal reading-out section repeatedly output the voltage values corresponding to the amounts of charges generated in the photodiodes included in the M×N pixel portions P 1,1 to P M,N in the photodetecting section as frame data. The row selecting wiring L V,m transmits a signal for controlling opening and closing operations of these reading-out switches from the controlling section to the reading-out switches.

The solid-state imaging device according to the present invention comprises a correction processing section in addition to the above-described photodetecting section, reading-out wirings L O,n , signal reading-out section, controlling section, and row selecting wirings L V,m . Such a correction processing section acquires frame data repeatedly outputted from the signal reading-out section, and then performs correction processing. The frame data correcting method according to the present invention is for correcting frame data to be outputted from the solid-state imaging device (according to the present invention) having the above-described structure.

In particular, the correction processing section in the solid-state imaging device according to the present invention carries out the frame correction method according to the present invention. Particularly, when a pixel portion disconnected from the controlling section due to disconnection of the m1 (integer not less than 1 and not more than M)-th row selecting wiring L V,m1 of the row selecting wirings L V,1 to L V,M is defined as a pixel portion P m1,n1 (n1 is an integer not less than 1 and not more than N), and a pixel portion belonging to the m2 (integer not less than 1 and not more than M)-th row neighboring the m1-th row to which the pixel portion P m1,n1 belongs is defined as a pixel portion P m2,n1 , the correction processing section corrects a voltage value V k corresponding to the pixel portion P m2,n1 of frame data F k outputted k-th from the signal reading-out section based on voltage values V k , V k−1 , and V k−2 corresponding to the same pixel portion P m2,n1 of the frame data F k and at least two frame data F k−1 and F k−2 just before the frame data F k , and determines a voltage value corresponding to the pixel portion P m1,n1 of the frame data F k based on the corrected value of the voltage value corresponding to the pixel portion P m2,n1 .

Thus, in accordance with the correction processing section in the solid-state imaging device and the frame data correcting method, when correcting a voltage value V k corresponding to the pixel portion P m2,n1 on the m2-th row selecting wiring L V,m2 neighboring the disconnected m1-th row selecting wiring L V,m1 , it is not necessary to use a voltage value corresponding to the pixel portion on a normal line. Therefore, in comparison with the technique described in Patent Document 1, the resolution near a defective line in an image after correction becomes higher in the present invention.

Preferably, the correction processing section in the solid-state imaging device according to the present invention (the frame data correcting method according to the present invention) performs processing of subtracting values obtained by multiplying the voltage values V k , V k−1 , and V k−2 by predetermined coefficients from the voltage value V k as processing of correcting the voltage value V k corresponding to the pixel portion P m2,n1 of the frame data F k .

Preferably, when any plurality of row selecting wirings among the row selecting wirings L V,1 to L V,M are disconnected, the correction processing section in the solid-state imaging device according to the present invention (the frame data correcting method according to the present invention) corrects the voltage value V k corresponding to the pixel portion P m2,n1 of the frame data F k by setting the coefficients for each of the plurality of disconnected row selecting wirings.

The solid-state imaging device according to the present invention may comprise a plurality of sensor elements each having the same structure as that of a sensor element consisting of the above-described photodetecting section, reading-out wirings L O,n , signal reading-out section, and row selecting wirings L V,m . In this case, when any of row selecting wirings included in any one of the plurality of sensor elements is disconnected, preferably, the correction processing section in the solid-state imaging device (the frame data correcting method according to the present invention) obtains the coefficients based on voltage values of frame data corresponding to the photodetecting section in the sensor element including the disconnected row selecting wiring.

An X-ray CT apparatus according to the present invention comprises an X-ray output section, a solid-state imaging device having the above-described structure (solid-state imaging device according to the present invention), moving means, and an image analyzing section. The X-ray output section outputs X-rays to a subject. The solid-state imaging device images a subject by receiving X-rays reaching through the subject from the X-ray output section. The moving means moves the X-ray output section and the solid-state imaging device relative to the subject. The image analyzing section inputs frame data after correction processing which is outputted from the solid-state imaging device, and generates a tomographic image of the subject based on the frame data.

The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only and are not to be considered as limiting the present invention.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope of the invention will be apparent to those skilled in the art from this detailed description.

Effects of the Invention

In accordance with the solid-state imaging device and frame data correcting method according to the present invention, even when any one of the row selecting wirings is disconnected, an image with high resolution can be obtained by properly correcting pixel data.

FIG. 1 is a view showing a configuration of a first embodiment of a solid-state imaging device according to the present invention;

FIG. 2 is a circuit diagram of a pixel portion P m,n , an integrating circuit S n , and a holding circuit H n included in the solid-state imaging device according to the first embodiment;

FIG. 3 is a timing chart for describing operations of the solid-state imaging device according to the first embodiment;

FIG. 4 is a graph schematically showing temporal changes of voltage values corresponding to pixel portions of a normal line and a neighboring line of frame data outputted from the signal reading-out section shown in FIG. 1 ;

FIG. 5 is a graph showing a relationship between a change amount in voltage value corresponding to a pixel portion on a neighboring line of frame data outputted from the signal reading-out section shown in FIG. 1 and time;

FIG. 6 is a view showing a configuration of a second embodiment of the solid-state imaging device according to the present invention; and

FIG. 7 is a view showing a configuration of an embodiment of an X-ray CT apparatus according to the present invention.

1 , 2 : solid-state imaging device; 10 , 10 A, 10 B: photodetecting section; 20 , 20 A, 20 B: signal reading-out section; 30 : controlling section; 40 : correction processing section; P 1,1 to P M,N : pixel portion; PD: photodiode; SW 1 : reading-out switch; S 1 to S N : integrating circuit; C 2 : integrating capacitive element; SW 2 : discharge switch; A 2 : amplifier; H 1 to H N : holding circuit; C 3 : holding capacitive element; SW 31 : input switch; SW 32 : output switch; L V,m : m-th row selecting wiring; L H,n : n-th column selecting wiring; L O,u : n-th column reading-out wiring; L R : discharge controlling wiring; L H : hold controlling wiring; and L out : voltage output wiring.

In the following, embodiments of a solid-state imaging device and a frame data correction method according to the present invention will be described in detail with reference to FIGS. 1 to 7 . In the description of the drawings, identical or corresponding components are designated by the same reference numerals, and overlapping description is omitted.

First Embodiment

FIG. 1 is a view showing a configuration of a first embodiment of a solid-state imaging device according to the present invention. The solid-state imaging device 1 according to the first embodiment comprises a photodetecting section 10 , a signal reading-out section 20 , a controlling section 30 , and a correction processing section 40 . When it is used as an X-ray flat panel, a scintillator panel is overlaid on the photodetecting surface 10 of the solid-state imaging device 1 .

The photodetecting section 10 has M×N pixel portions P 1,1 to P M,N two-dimensionally arrayed in M rows and N columns. A pixel portion P m,n is a pixel portion positioned on the m-th row in the n-th column. Here, M and N are integers not less than 2, and m is an integer not less than 1 and not more than M, and n is an integer not less than 1 and not more than N. The pixel portions P m,n are the PPS type, and have a common configuration.

N pixel portions P m,1 to P m,N belonging to the m-th row are connected to the controlling section 30 via an m-th row selecting wiring L V,m . Output terminals of M pixel portions P 1,n to P M,n belonging to the n-th column are connected to the integrating circuit S n included in the signal reading-out section 20 via an n-th column reading-out wiring L O,n .

The signal reading-out section 20 includes N integrating circuits S 1 to S N and N holding circuits H 1 to H N . The integrating circuits S n have a common configuration. The holding circuits H n have a common configuration.

Each integrating circuit S n has an input terminal connected to the reading-out wiring L O,n , and temporarily accumulates charges inputted in the input terminal and then outputs a voltage value corresponding to the accumulated charge amount from an output terminal to the holding circuit H n . N integrating circuits S 1 to S N are connected to the controlling section 30 via a discharge controlling wiring L R .

Each holding circuit H n has an input terminal connected to the output terminal of the integrating circuit S n , and holds a voltage value inputted in the input terminal and outputs the held voltage value from an output terminal to an output wiring L out . N holding circuits H 1 to H N are connected to the controlling section 30 via a hold controlling wiring L H . Each holding circuit H n is connected to the controlling section 30 by an n-th column selecting wiring L H,n .

The controlling section 30 outputs an m-th row selecting controlling signal Vsel(m) to the m-th row selecting wiring L V,m to supply this m-th row selecting controlling signal Vsel(m) to N pixel portions P m,1 to P m,N belonging to the m-th row. M row selecting controlling signals Vsel( 1 ) to Vsel(M) are successively set to significant values. For successively setting M row selecting controlling signals Vsel( 1 ) to Vsel(M) to significant values and outputting these, the controlling section 30 includes a shift register.

The controlling section 30 outputs an n-th column selecting controlling signal Hsel(n) to the n-th column selecting wiring L H,n to supply this n-th column selecting controlling signal Hsel(n) to the holding circuit H n . N column selecting controlling signals Hsel( 1 ) to Hsel(N) are also successively set to significant values. For successively setting N column selecting controlling signals Hsel( 1 ) to Hsel(N) to significant values and outputting these, the controlling section 30 includes a shift register.

The controlling section 30 outputs a discharge controlling signal Reset to the discharge controlling wiring L R to supply this discharge controlling signal Reset to the N integrating circuits S 1 to S N . The controlling section 30 outputs a hold controlling signal Hold to the hold controlling wiring L H to supply this hold controlling signal Hold to the N holding circuits H 1 to H N .

As described above, the controlling section 30 controls opening and closing operations of the reading-out switches SW 1 included in N pixel portions P m,1 to P m,N belonging to the m-th row in the photodetecting section 10 , and controls voltage value holding operations and voltage value output operations in the signal reading-out section 20 . Accordingly, the controlling section 30 makes the signal reading-out section 20 repeatedly output voltage values corresponding to amounts of charges generated in photodiodes PD included in the M×N pixel portions P 1,1 to P M,N in the photodetecting section 10 as frame data.

The correction processing section 40 acquires frame data repeatedly outputted from the signal reading-out section 20 , applies correction processing to the frame data, and then outputs the frame data after correction processing. Details of the correction processing in the correction processing section 40 will be described in detail later.

FIG. 2 is a circuit diagram of a pixel portion P m,n , an integrating circuit S n , and a holding circuit H n included in the solid-state imaging device according to the first embodiment. In FIG. 2 , circuit diagrams of the pixel portion P m,n as a representative of the M×N pixel portions P 1,1 to P M,N , an integrating circuit S n as a representative of the N integrating circuits S 1 to S N , and a holding circuit H n as a representative of the N holding circuit H 1 to H N , are shown. That is, the circuit portions concerning a pixel portion P m,n in the n-th column on the m-th row and the n-th column reading-out wiring L O,n are shown in FIG. 2 .

The pixel portion P m,n includes a photodiode PD and a reading-out switch SW 1 . The anode terminal of the photodiode PD is grounded, and the cathode terminal of the photodiode PD is connected to the n-th column reading-out wiring L O,n via the reading-out switch SW 1 . The photodiode PD generates charges of an amount corresponding to an incident light intensity, and the generated charges are accumulated in a junction capacitance portion. The reading-out switch SW 1 is supplied with an m-th row selecting controlling signal which passed through the m-th row selecting wiring L V,m from the controlling section 30 . The m-th row selecting controlling signal is an electric signal which instructs opening and closing operations of the reading-out switches SW 1 included in the N pixel portions P m,1 to P m,N belonging to the m-th row in the photodetecting section 10 .

In the pixel portion P m,n , when the m-th row selecting controlling signal Vsel(m) is at low level, the reading-out switch SW 1 opens. In this case, charges generated in the photodiode PD are not outputted to the n-th column reading-out wiring L O,n but are accumulated in the junction capacitance portion. On the other hand, when the m-th row selecting controlling signal Vsel(m) is at high level, the reading-out switch SW 1 closes. In this case, charges generated in the photodiode PD and accumulated in the junction capacitance portion until then are outputted to the n-th column reading-out wiring L O,n through the reading-out switch SW 1 .

The n-th column reading-out wiring L O,n is connected to the reading-out switches SW 1 included in M pixel portions P 1,n to P M,n belonging to the n-th column in the photodetecting section 10 . The n-th column reading-out wiring L O,n reads out charges generated in the photodiode PD included in any of the M pixel portions P 1,n to P M,n via the reading-out switch SW 1 included in this pixel portion and transfers the charges to the integrating circuit S n .

The integrating circuit S n includes an amplifier A 2 , an integrating capacitive element C 2 , and a discharge switch SW 2 . The integrating capacitive element C 2 and the discharge switch SW 2 are connected in parallel to each other, and provided between an input terminal and an output terminal of the amplifier A 2 . The input terminal of the amplifier A 2 is connected to the n-th column reading-out wiring L O,n . The discharge switch SW 2 is supplied with a discharge controlling signal Reset which passed through the discharge controlling wiring L R from the controlling section 30 . The discharge controlling signal Reset is an electric signal which instructs opening and closing operations of the discharge switches SW 2 included in the N integrating circuits S 1 to S N .

In the integrating circuit S n , when the discharge controlling signal Reset is at high level, the discharge switch SW 2 closes. In this case, the integrating capacitive element C 2 is discharged, and accordingly, a voltage value to be outputted from the integrating circuit S n is initialized. When the discharge controlling signal Reset is at low level, the discharge switch SW 2 opens. In this case, charges inputted in the input terminal are accumulated in the integrating capacitive element C 2 , and a voltage value corresponding to the accumulated charge amount is outputted from the integrating circuit S n .

The holding circuit H n includes an input switch SW 31 , an output switch SW 32 , and a holding capacitive element C 3 . One end of the holding capacitive element C 3 is grounded. The other end of the holding capacitive element C 3 is connected to the output terminal of the integrating circuit S n via the input switch SW 31 , and connected to the voltage output wiring L out via the output switch SW 32 . The input switch SW 31 is supplied with a hold controlling signal Hold which passed through the hold controlling wiring L H from the controlling section 30 . The hold controlling signal Hold is an electric signal which instructs opening and closing operations of the input switches SW 31 included in N holding circuits H 1 to H N . The output switch SW 32 is supplied with an n-th column selecting controlling signal Hsel(n) which passed through the n-th column selecting wiring L H,n from the controlling section 30 . The n-th column selecting controlling signal Hsel(n) is an electric signal which instructs opening and closing operations of the output switch SW 32 included in the holding circuit H n .

In the holding circuit H n , when the hold controlling signal Hold switches from high level to low level, the input switch SW 31 switches from a closed state to an open state. At this time, a voltage value inputted in the input terminal is held in the holding capacitive element C 3 . When the n-th column selecting controlling signal Hsel(n) is at high level, the output switch SW 32 closes. At this time, the voltage value held in the holding capacitive element C 3 is outputted to the voltage output wiring L out .

When outputting voltage values corresponding to received light intensities in the N pixel portions P m,1 to P m,N belonging to the m-th row in the photodetecting section 10 , the controlling section 30 instructs temporary closing and then opening of the discharge switches SW 2 included in the N integrating circuits S 1 to S N by a discharge controlling signal Reset. Thereafter, the controlling section 30 instructs closing of the reading-out switches SW 1 included in the N pixel portions P m,1 to P m,N of the m-th row in the photodetecting section 10 for a predetermined period by an m-th row selecting controlling signal Vsel(m). In such a predetermined period, the controlling section 30 instructs switching of the input switches SW 31 included in the N holding circuits H 1 to H N from a closed state to an open state by a hold controlling signal Hold. Then, after the predetermined period elapses, the controlling section 30 instructs successive closing of the output switches SW 32 included in the N holding circuits H 1 to H N for a predetermined period by column selecting controlling signals Hsel( 1 ) to Hsel(N). The controlling section 30 performs this control for the respective rows in order.

Next, operations of the solid state imaging device 1 according to the first embodiment will be described. In the solid state imaging device 1 according to the first embodiment, under control by the controlling section 30 , M row selecting controlling signals Vsel( 1 ) to Vsel(M), the N column selecting controlling signals Hsel( 1 ) to Hsel(N), the discharge controlling signal Reset, and the hold controlling signal Hold change their levels at predetermined timings. Accordingly, light made incident on the photodetecting surface 10 can be imaged and frame data can be obtained, and further, frame data can be corrected by the correction processing section 40 .

FIG. 3 is a timing chart describing operations of the solid state imaging device 1 according to the first embodiment. FIG. 3 shows (a) the discharge controlling signal Reset for instructing opening and closing operations of the discharge switches SW 2 included in the N integrating circuits S 1 to S N , (b) the first row selecting controlling signal Vsel( 1 ) for instructing opening and closing operations of the reading-out switches SW 1 included in the N pixel portions P 1,1 to P 1,N belonging to the first row in the photodetecting section 10 , (c) the second row selecting controlling signal Vsel( 2 ) for instructing opening and closing operations of the reading-out switches SW 1 included in the N pixel portions P 2,1 to P 2,N belonging to the second row in the photodetecting section 10 , and (d) the hold controlling signal Hold for instructing opening and closing operations of the input switches SW 31 included in the N holding circuits H 1 to H N .

FIG. 3 further subsequently shows (e) the first column selecting controlling signal Hsel( 1 ) for instructing opening and closing operations of the output switch SW 32 included in the holding circuit H 1 , (f) the second column selecting controlling signal Hsel( 2 ) for instructing opening and closing operations of the output switch SW 32 included in the holding circuit H 2 , (g) the third column selecting controlling signal Hsel( 3 ) for instructing opening and closing operations of the output switch SW 32 included in the holding circuit H 3 , (h) the n-th column selecting controlling signal Hsel(n) for instructing opening and closing operations of the output switch SW 32 included in the holding circuit H n , and (i) the N-th column selecting controlling signal Hsel(N) for instructing opening and closing operations of the output switch SW 32 included in the holding circuit H N .

Charges generated in the photodiodes PD included in the N pixel portions P 1,1 to P 1,N belonging to the first row and accumulated in the junction capacitance portions are reading-out as follows.

That is, before the time t 10 , the M row selecting controlling signals Vsel( 1 ) to Vsel(M), the N column selecting controlling signals Hsel( 1 ) to Hsel(N), the discharge controlling signal Reset, and the hold controlling signal Hold are at low level. During a period from the time t 10 to t 11 , the discharge controlling signal Reset to be outputted from the controlling section 30 to the discharge controlling wiring L R becomes high level, and accordingly, in the N integrating circuits S 1 to S N , the discharge switches SW 2 close and the integrating capacitive elements C 2 are discharged. During a period from the time t 12 after the time t 11 to the time t 15 , the first row selecting controlling signal Vsel( 1 ) to be outputted from the controlling section 30 to the first row selecting wiring L V,1 becomes high level, and accordingly, the reading-out switches SW 1 included in the N pixel portions P 1,1 to P 1,N belonging to the first row in the photodetecting section 10 close.

In the period (t 12 to t 15 ), during a period from the time t 13 to the time t 14 , the hold controlling signal Hold to be outputted from the controlling section 30 to the hold controlling wiring L H becomes high level. Accordingly, the input switches SW 31 in the N holding circuits H 1 to H N close.

In the period (t 12 to t 15 ), while the reading-out switch SW 1 included in each pixel portion P 1,n belonging to the first row is closed, the discharge switch SW 2 of each integrating circuit S n is open. Therefore, charges generated in the photodiode PD of each pixel portion P 1,n and accumulated in the junction capacitance portion until then are transferred to the integrating capacitive element C 2 (accumulated in the integrating capacitive element C 2 ) of the integrating circuit S n through the reading-out switch SW 1 of the pixel portion P 1,n and the n-th column reading-out wiring L O,n . Then, a voltage value corresponding to the amount of charges accumulated in the integrating capacitive element C 2 of each integrating circuit S n is outputted from the output terminal of the integrating circuit S n .

At the time t 14 in the period (t 12 to t 15 ), the hold controlling signal Hold switches from high level to low level, and accordingly, in each of the N holding circuits H 1 to H N , the input switch SW 31 switches from a closed state to an open state. A voltage value outputted from the output terminal of the integrating circuit S n and inputted in the input terminal of the holding circuit H n at this time is held by the holding capacitive element C 3 .

Then, after the period (t 12 to t 15 ), column selecting controlling signals Hsel( 1 ) to Hsel(N) to be outputted from the controlling section 30 to the column selecting wirings L H,1 to L H,N successively become high level for a predetermined period. Accordingly, the output switches SW 32 included in the N holding circuits H 1 to H N successively close for the predetermined period. At this time, the voltage values held in the holding capacitive elements C 3 of the holding circuits H n are successively outputted to the voltage output wiring L out through the output switches SW 32 . The voltage values V out to be outputted to the voltage output wiring L out indicate the received light intensities received by the photodiodes PD included in the N pixel portions P 1,1 to P 1,N belonging to the first row. The voltage values V out to be outputted from the N holding circuits H 1 to H N to the voltage output wiring L out are inputted into the correction processing section 40 through the voltage output wiring L out .

Subsequently, charges generated in the photodiodes PD included in N pixel portions P 2,1 to P 2,N belonging to the second row and accumulated in the junction capacitance portions are reading-out as follows.

During the period from the time t 20 to the time t 21 , the discharge controlling signal Reset to be outputted from the controlling section 30 to the discharge controlling wiring L R becomes high level. Accordingly, in the N integrating circuits S 1 to S N , the discharge switches SW 2 close, and the integrating capacitive elements C 2 are discharged. During the period from the time t 22 after the time t 21 to the time t 25 , the second row selecting controlling signal Vsel( 2 ) to be outputted from the controlling section 30 to the second row selecting wiring L V,2 becomes high level. Accordingly, the reading-out switches SW 1 included in the N pixel portions P 2,1 to P 2,N belonging to the second row in the photodetecting section 10 close.

In the period (t 22 to t 25 ), during the period from the time t 23 to the time t 24 , the hold controlling signal Hold to be outputted from the controlling section 30 to the hold controlling wiring L H becomes high level. Accordingly, input switches SW 31 in the N holding circuits H 1 to H N close.

Then, after the period (t 22 to t 25 ), column selecting controlling signals Hsel( 1 ) to Hsel(N) to be outputted from the controlling section 30 to the column selecting wirings L H,1 to L H,N successively become high level for a predetermined period. Accordingly, the output switches SW 32 included in the N holding circuits H 1 to H N successively close for the predetermined period.

Thus, voltage values V out indicating the received light intensities received by the photodiodes PD included in the N pixel portions P 2,1 to P 2,N belonging to the second row are outputted to the voltage output wiring L out . Voltage values V out to be outputted from the N holding circuits H 1 to H N to the voltage output wiring L out are inputted into the correction processing section 40 through the voltage output wiring L out .

Subsequent to the above-described operation for the first row and the second row, the same operation is performed for the third to the M-th rows, and accordingly, frame data showing an image to be obtained by one imaging is obtained. When the operation for the M-th row is finished, the same operation is performed again in order from the first row, and accordingly, frame data showing the next image is obtained. By thus repeating the same operation with a predetermined period, voltage values V out indicating two-dimensional intensity distribution of an image of light received by the photodetecting section 10 are outputted to the voltage output wiring L out (frame data is repeatedly obtained). These frame data is inputted into the correction processing section 40 .

In the period during which the reading-out switches SW 1 included in the N pixel portions P m,1 to P m,N belonging to the m-th row are closed, charges generated in the photodiode PD of each pixel portion P m,n belonging to the m-th row and accumulated in the junction capacitance portion are transferred to the integrating capacitive element C 2 of the integrating circuit S n through the reading-out switch SW 1 of the pixel portion P m,n and the n-th column reading-out wiring L O,n . At this time, the accumulated charges in the junction capacitance portion of the photodiode PD of each pixel portion P m,n of the m-th row are initialized.

However, when a certain m-th row selecting wiring L V,m is disconnected at a point halfway, the m-th row selecting controlling signal Vsel(m) is not transmitted to pixel portions farther from the controlling section 30 than the disconnection point among N pixel portions P m,1 to P m,N belonging to the m-th column. Therefore, in the pixel portion influenced by the disconnection, the reading-out switch SW 1 is left open, and charges cannot be transferred to the integrating circuit S n . Namely, in pixel portions which are influenced by the disconnection, initialization of the accumulated charges in the junction capacitance portions of the photodiode PD by the charge transfer is impossible. In the case that this state continues, charges generated in the photodiode in response to light incidence in the pixel portion which is influenced by disconnection are only accumulated in the junction capacitance portion of the photodiode. When the charges exceed the saturation level, the charges overflow to the pixel portions on both neighboring rows, and defective lines occur in pixel portions on consecutive three rows.

Therefore, in the solid-state imaging device 1 according to the first embodiment, the correction processing section 40 acquires frame data repeatedly outputted from the signal reading-out section 20 , and applies the following correction processing (frame data correcting method according to the present invention) to each of the acquired frame data.

As a precondition for the following description, it is assumed that an m1-th row selecting wiring L V,m1 which is any one of the row selecting wirings L V,1 to L V,M is disconnected. A pixel portion on a defective line disconnected from the controlling section 30 due to disconnection of the m1-th row selecting wiring L V,m1 among N pixel portions P m1,1 to P m1,N belonging to the m1-th row is defined as a pixel portion P m1,n1 . A pixel portion on a neighboring line which belongs to the m2-th row neighboring the m1-th row and neighbors the pixel portion P m1,n1 is defined as a pixel portion P m2,n1 . Here, m1 and m2 are integers not less than 1 and not more than M, n1 is an integer not less than 1 and not more than N, and the difference between m1 and m2 is 1.

Frame data to be outputted k-th from the signal reading-out section 20 is expressed as F k . Namely, frame data to be inputted into the correction processing section 40 from the signal reading-out section 20 is . . . , F k−2 , F k−1 , F k , F k+1 , F k+2 , . . . in order. Here, k is an integer.

The correction processing section 40 corrects a voltage value V k corresponding to a pixel portion P m2,n1 on a neighboring line of the frame data F k based on voltage values V k , V k−1 , and V k−2 corresponding to the same pixel portion P m2,n1 the frame data F k and at least two frame data F k−1 and F k−2 just before the frame data F k .

At this time, as processing to correct the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line in the frame data F k , the correction processing section 40 may use a function such as a polynomial with the voltage values V k , V k−1 , and V k−2 as variables. However, preferably, the correction processing section performs processing of subtracting values obtained by multiplying the voltage values V k , V k−1 , and V k−2 by coefficients from the voltage value V k .

It is also preferable that, when any plurality of row selecting wirings among the row selecting wirings L V,1 to L V,M are disconnected, the correction processing section 40 sets the coefficients for each of the plurality of disconnected row selecting wirings, and corrects the voltage value V k corresponding to the pixel portion P m2,n1 in the frame data F k .

Further, the correction processing section 40 determines a voltage value corresponding to the pixel portion P m1,n1 on the defective line in the frame data F k based on a value after correction of the voltage value corresponding to the pixel portion P m2,n1 on the neighboring line. The determination is preferably made by interpolation calculation based on the voltage value corresponding to pixel portion P m2,n1 on the neighboring line.

Then, the correction processing section 40 outputs, as corrected frame data, frame data after correction as described above of the voltage values corresponding to the pixel portion P m2,n1 on the neighboring line and the pixel portion P m1,n1 on the defective line.

Hereinafter, correction processing to be applied to the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line is described in greater detail as follows.

FIG. 4 is a graph schematically showing temporal changes of the voltage values corresponding to pixel portions on a normal line and a neighboring line in frame data outputted from the signal reading-out section shown in FIG. 1 . In FIG. 4 , the period before the time t O is a period in which light with uniform intensity is made incident on the entire photodetecting section 10 . The period after t O is a period in which no light is made incident on the entire photodetecting section 10 . The normal line is neither a defective line the row selecting wiring of which is disconnected, nor a neighboring line into which charges flow from a pixel portion on the defective line.

As shown in FIG. 4 , when light with uniform intensity is made incident on the entire photodetecting section 10 before the time t O , in the frame data outputted from the signal reading-out section 20 , a voltage value corresponding to a pixel portion on the neighboring line is larger than a voltage value W corresponding to a pixel portion on the normal line. The reason for this is because charges generated in the photodiode of the pixel portion on the defective line in response to light incidence are not reading-out to the signal reading-out section 20 but are just accumulated in the junction capacitance portion of the photodiode. In other words, when the accumulated charge amount of charges generated in the photodiode in response to light incidence in the pixel portion on the defective line exceeds the saturation level, charges over the saturation level overflow to a pixel portion on the neighboring line.

When no light is made incident on the entire photodetecting section 10 after the time t O , both voltage values corresponding to the pixel portions on a normal line and a neighboring line in the frame data outputted from the signal reading-out section 20 gradually decrease, and converge to an initial value (a value indicating that no light is made incident) soon. However, in comparison with the change in the voltage value corresponding to the pixel portion on the normal line, the change in the voltage value corresponding to the pixel portion on the neighboring line has a time delay, and also has a slower decrease speed. The possible reason for this is because the leak of the charges from the pixel portion on the defective line to the pixel portion on the neighboring line takes time.

Based on the knowledge of the inventors of the present invention about the above-described phenomenon, the correction processing section 40 corrects the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line in the frame data F k outputted from the signal reading-out section 20 . In detail, the voltage value V k corresponding to the pixel portion P m2,n1 is corrected based on voltage values V k , V k−1 , and V k−2 corresponding to the same pixel portion P m2,n1 in frame data F k and at least two frame data F k−1 and F k−2 just before the frame data F k .

As shown in FIG. 4 , it is assumed that a voltage value corresponding to a pixel portion on the neighboring line in the frame data outputted from the signal reading-out section 20 has an amount of change B in the period from the time t A after the time t O to the time t B , an amount of change C in the period from the time t B to the time t C , an amount of change D in the period from the time t C to the time t D , and an amount of change E from the time t D to the time t E .

As shown in the following formulas (1a) to (1d), coefficients b, c, d, and e are obtained by dividing these amounts of changes B, C, D, and E by a voltage value W corresponding to a pixel portion on the normal line in frame data outputted from the signal reading-out section 20 when light with uniform intensity is made incident on the entire photodetecting section 10 before the time t O .

[Formula 1]

b=B/W   (1a)

c=C/W   (1b)

d=D/W   (1c)

e=E/W   (1d)

FIG. 5 is a graph showing the relationship between time and an amount of change in the voltage value corresponding to a pixel portion on the neighboring line in the frame data outputted from the signal reading-out section shown in FIG. 1 . As shown in FIG. 5 , the relationship between logarithmic values of the coefficients b, c, d, and e and the corresponding times t B , t C , t D , and t E is substantially linear. By using this, the coefficient a at the time t A is obtained by extrapolation.

Further, according to the relational expressions shown in the following formulas (2a) to (2e), the coefficients a to e are converted into coefficients a 1 to e 1 . That is, the coefficients a 1 to e 1 are obtained by multiplying the coefficients a to e by a fixed coefficient, and a sum of them becomes 1.

When the intervals between the times t O and t A to t E are equal to periods of frame data outputted from the signal reading-out section 20 , examples of the values obtained in this case of the coefficients a 1 to e 1 become as shown in the following formulas (3a) to (3e).

[Formula 3]

a 1 =0.5354  (3a)

b 1 =0.2647  (3b)

c 1 =0.1177  (3c)

d 1 =0.05633  (3d)

e 1 =0.02587  (3e)

Further, the coefficients a 1 to e 1 are converted into coefficients a 2 to e 2 according to the relational expressions shown in the following formulas (4a) to (4f). V ave1 in the formula (4f) is an average of voltage values corresponding to a pixel portion on a neighboring line in frame data outputted from the signal reading-out section 20 when light with uniform intensity is made incident on the entire photodetecting section 10 before the time t O . V ave2 is an average of voltage values corresponding to a pixel portion on a normal line in the frame data. That is, the parameter z in the formula (4f) indicates a rate of increase of the average V ave1 of the voltage values corresponding to the pixel portion on the neighboring line with respect to the average V ave2 of the voltage values corresponding to the pixel portion on the normal line.

Then, according to the relational expression shown in the following formula (5), the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line in the frame data F k is corrected based on the voltage values V k to V k−4 corresponding to the same pixel portion P m2,n1 in the frame data F k and four frame data F k−1 to F k−4 just before the frame data F k . Specifically, values obtained by multiplying the voltage values V k to V k−4 by the coefficients a 2 to e 2 are subtracted from the voltage value V k . Thus, the voltage value V kc after correction of the voltage value V k is obtained.

[Formula 5]

V kc =V k −a 2 V k −b 2 V k−1 −c 2 V k−2 −d 2 V k−3 −e 2 V k−4   (5)

The correction processing section 40 obtains the voltage value V kc after correction of the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line in the frame data F k outputted from the signal reading-out section 20 , and then determines a voltage value corresponding to the pixel portion P m1,n1 on the defective line based on the corrected voltage value V kc .

The correction processing section 40 preferably applies dark calibration in advance to the voltage values corresponding to pixel portions in the frame data F k outputted from the signal reading-out section 20 before the above-described processing. The correction processing section 40 may use analog processing to perform the above-described processing. Preferably, the correction processing section 40 performs digital processing after digitally converting the frame data F k outputted from the signal reading-out section 20 , and in this case, preferably has frame memories which store frame data of several frames as digital values.

Preferably, in order to perform the above-described processing, the correction processing section 40 includes a storage section which stores a disconnected row selecting wiring among the row selecting wirings L V,1 to L V,M and a disconnection point of the disconnected row selecting wiring in advance. Further, disconnection information obtained in inspection in the middle of or after production of the solid-state imaging device 1 according to the first embodiment may be stored in the storage section from the outside.

The correction processing section 40 may be provided integrally with the photodetecting section 10 , the signal reading-out section 20 , and the controlling section 30 . In this case, preferably, the entire solid-state imaging device 1 according to the first embodiment is integrated on a semiconductor substrate. While the photodetecting section 10 , the signal reading-out section 20 , and the controlling section 30 are integrated, the correction processing section 40 may be provided separately. In this case, the correction processing section 40 can be realized by, for example, a computer.

As described above, in the solid-state imaging device 1 according to the first embodiment or the method (the frame data correcting method according to the present invention) of correcting frame data F k outputted from the signal reading-out section 20 of the solid-state imaging device 1 , the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line in the frame data F k is corrected based on the voltage values V k to V k−4 corresponding to the same pixel portion P m2,n1 in the frame data F k and four frame data F k−1 to F k−4 just before the frame data F k . In other words, when correcting the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line, it is not necessary to use a voltage value corresponding to a pixel portion on the normal line. Therefore, in the first embodiment, the resolution near the defective line in the image after correction becomes higher than in the conventional technique described in Patent Document 1.

In the first embodiment, when correcting the voltage value V k corresponding to the pixel portion P m2,n1 on the neighboring line in the frame data F k , the voltage values V k to V k−4 corresponding to the same pixel portion P m2,n1 in the frame data F k and the four frame data F k−1 to F k−4 just before the frame data F k are used. However, as is understood from the formulas (3a) to (3e) and (4a) to (4f) given above, the values of the coefficients a 2 , b 2 , c 2 , d 2 , and e 2 decrease substantially by half in order. Therefore, in order to obtain resolution higher than in the conventional technique described in Patent Document 1, the voltage values V k is corrected based on the voltage values V k , V k−1 , and V K−2 corresponding to the same pixel portion P m2,n1 in the frame data F k to be corrected and at least two frame data F k−1 and F k−2 just before the frame data F k in the first embodiment.

The frame data output operation by the signal reading-out section 20 and the correction processing by the correction processing section 40 may be performed alternately, or performed in parallel. In the former case, after an operation for outputting the frame data F k by the signal reading-out section 20 , correction processing for the frame data F k by the correction processing section 40 is performed. Then, after the correction processing is finished, the next frame data F k+1 is outputted from the signal reading-out section 20 to the correction processing section 40 . On the other hand, in the latter case, after the operation for outputting the frame data F k by the signal reading-out section 20 , the correction processing for the frame data F k by the correction processing section 40 is performed. Then, in a period at least a part of which overlaps the period of the correction processing, the next frame data F k+1 is outputted from the signal reading-out section 20 to the correction processing section 40 .

The leakage of charges from a pixel portion on a defective line to a pixel portion on a neighboring line occurs so that the charges leak to pixel portions on neighboring lines on both sides of the defective line. Therefore, preferably, the pixel portions on neighboring lines on both sides of the defective line are corrected by using voltage values of previous frame data. However, in a case where a voltage value of a pixel portion on a neighboring line on one side of the defective line and a voltage value of a pixel portion on a normal line further neighboring the neighboring line on the same side are binned (summed) and reading-out, the correction using the voltage values of the previous frame data is applied to only the voltage value of the pixel portion on the neighboring line on the other side of the defective line. Even in this case, resolution higher than in the conventional technique described in Patent Document 1 is also obtained.

Second Embodiment

Next, a second embodiment of the solid-state imaging device according to the present invention will be described. FIG. 6 is a view showing a configuration of a second embodiment of a solid-state imaging device according to the present invention. The solid-state imaging device 2 according to the second embodiment comprises photodetecting sections 10 A and 10 B, signal reading-out sections 20 A and 20 B, a controlling section 30 , a correction processing section 40 , and buffer sections 50 A and 50 B. When it is used as an X-ray flat panel, a scintillator panel is overlaid on the photodetecting sections 10 A and 10 B of the solid-state imaging device 2 .

The photodetecting sections 10 A and 10 B constituting a part of the solid-state imaging device 2 according to the second embodiment have a structure similar to that of the photodetecting section 10 included in the solid-state imaging device 1 according to the first embodiment. The signal reading-out sections 20 A and 20 B constituting a part of the solid-state imaging device 2 according to the second embodiment also have a structure similar to that of the signal reading-out section 20 included in the solid-state imaging device 1 according to the first embodiment.

The controlling section 30 included in the solid-state imaging device 2 outputs an m-th row selecting controlling signal Vsel(m) to the m-th row selecting wiring L V,m to supply this m-th row selecting controlling signal Vsel(m) to the pixel portions P m1, to P m,N belonging to the m-th rows included in the photodetecting sections 10 A and 10 B. The controlling section 30 outputs an n-th column selecting controlling signal Hsel(n) which should be supplied to each holding circuit H n included in the signal reading-out section 10 A to the n-th column selecting wiring L HA,n , and outputs an n-th column selecting controlling signal Hsel(n) which should be supplied to each holding circuit H n included in the signal reading-out section 20 B to the n-th column selecting wiring L HB,n .

The controlling section 30 outputs a discharge controlling signal Reset which should be supplied to the respective integrating circuits S n included in the signal reading-out sections 20 A and 20 B to the discharge controlling wiring L R . The controlling section 30 outputs a hold controlling signal Hold which should be supplied to the respective holding circuits H n included in the signal reading-out sections 20 A and 20 B to the hold controlling wiring L H .

As described above, the controlling section 30 controls opening and closing operations of the reading-out switches SW 1 included in N pixel portions P m,1 to P m,N belonging to the m-th rows included in the photodetecting sections 10 A and 10 B, and controls voltage value holding operations and output operations in the signal reading-out sections 20 A and 20 B. Accordingly, the controlling section 30 makes the signal reading-out sections 20 A and 20 B repeatedly output voltage values corresponding to amounts of charges generated in the photodiodes PD included in M×N pixel portions P 1,1 to P M,N in the photodetecting sections 10 A and 10 B as frame data.

Thus, the solid-state imaging device 2 according to the second embodiment comprises a plurality of pairs of photodetecting sections and signal reading-out sections, and accordingly, the solid-state imaging device can expand the photodetecting region, or increase the number of pixels. In the solid-state imaging device 2 according to the second embodiment, the plurality of signal reading-out sections can be operated in parallel to each other, and high-speed readout of pixel data is possible.

The correction processing section 40 inputs voltage values which were successively outputted from the holding circuits H n included in the signal reading-out section 20 A to the voltage output wiring L out — A and passed through the buffer section 50 A, and inputs voltage values which were successively outputted from the holding circuits H n included in the signal reading-out section 20 B to the voltage output wiring L out — B and passed through the buffer section 50 B. Then, the correction processing section 40 applies correction processing to frame data repeatedly outputted from the signal reading-out sections 20 A and 20 B, and outputs frame data after correction processing.

The details of processing in this correction processing section 40 are as described above. However, the operation characteristics of the buffer section 50 A and the buffer section 50 B are not always equal to each other, and even when their input voltage values are the same, their output voltage values are different in some cases. Therefore, when a row selecting wiring of any of the rows included in the photodetecting section 20 A is disconnected, the correction processing section 40 preferably obtains the coefficients a 2 to e 2 based on voltage values of a neighboring line and a normal line in frame data corresponding to the photodetecting section 20 A. Similarly, when a row selecting wiring of any of rows included in the photodetecting section 20 B is disconnected, the correction processing section 40 preferably obtains the coefficients a 2 to e 2 based on voltage values of a neighboring line and a normal line in frame data corresponding to the photodetecting section 20 B.

(X-Ray CT Apparatus)

The solid-state imaging device 1 according to the first embodiment described above or the method for correcting frame data outputted from the signal reading-out section 20 of the solid-state imaging device 1 is preferably used in an X-ray CT apparatus. An X-ray CT apparatus including the solid-state imaging device 1 according to the first embodiment will be described next.

FIG. 7 is a view showing a configuration of an embodiment of an X-ray CT apparatus according to the present invention. In the X-ray CT apparatus 100 shown in FIG. 7 , an X-ray source 106 generates X-rays toward a subject. The radiation field of the X-rays generated from the X-ray source 106 is controlled by a primary slit plate 106 b . The X-ray source 106 includes an X-ray tube installed inside, and by adjusting the conditions such as a tube voltage, a tube current, and an energization time of the X-ray tube, the X-ray irradiation amount onto the subject is controlled. An X-ray imaging sensor 107 includes a CMOS solid-state imaging device having a plurality of pixel portions two-dimensionally arrayed, and detects an X-ray image which passed through the subject. In front of the X-ray imaging sensor 107 , a secondary slit plate 107 a which limits an X-ray incidence region is provided.

A swing arm 104 swings the X-ray source 106 and the X-ray imaging sensor 107 around a subject while holding these opposite to each other when performing panoramic tomography. The swing arm 104 is provided with a slide mechanism 113 for linearly displacing the X-ray imaging sensor 107 with respect to a subject when performing linear tomography. The swing arm 104 is driven by an arm motor 110 constituting a rotary table, and the rotation angle is detected by an angle sensor 112 . The arm motor 110 is loaded on a movable portion of an XY table 114 , and the rotation center thereof is arbitrarily adjusted within the horizontal plane.

An image signal outputted from the X-ray imaging sensor 107 is converted into digital data of, for example, 10 bits (=1024 level) by an AD converter 120 , and temporarily taken into a CPU (Central Processing Unit) 121 . Thereafter, the image signal from the X-ray imaging sensor 107 , converted into digital data, is stored in a frame memory 122 . From the image data stored in the frame memory 122 , a tomographic image along an arbitrary tomographic surface is reproduced by predetermined arithmetic processing. The reproduced tomographic image is outputted to a video memory 124 , converted into an analog signal by a DA converter 125 , and then displayed by an image display section 126 such as a CRT (Cathode-Ray Tube) (and used for various diagnoses).

To the CPU 121 , a work memory 123 necessary for signal processing is connected, and further, an operation panel 119 including a panel switch and an X-ray irradiation switch, etc., is connected. The CPU 121 is connected to a motor driving circuit 111 which drives the arm motor 110 , slit control circuits 115 and 116 which control aperture ranges of the primary slit plate 106 b and the secondary slit plate 107 a , and an X-ray control circuit 118 which controls the X-ray source 106 , and further, outputs a clock signal for driving the X-ray imaging sensor 107 .

The X-ray control circuit 118 can feedback-control the X-ray irradiation amount onto a subject based on a signal imaged by the X-ray imaging sensor 107 .

In the X-ray CT apparatus 100 configured as described above, the X-ray imaging sensor 107 is equivalent to the photodetecting section 10 , the signal reading-out section 20 , and the controlling section 30 of the solid-state imaging device 1 according to the first embodiment, and a scintillator panel is provided on the front surface of the photodetecting section 10 . The CPU 121 and the work memory 123 are equivalent to the correction processing section 40 of the solid-state imaging device 1 according to the first embodiment.

The X-ray CT apparatus 100 includes the solid-state imaging device 1 according to the first embodiment, and includes the CPU 121 as an image analyzing section which generates a tomographic image of a subject based on frame data after correction processing outputted from the solid-state imaging device 1 . With such a configuration, the X-ray CT apparatus 100 can obtain a tomographic image with high resolution near a defective line. Particularly, in the X-ray CT apparatus 100 , multiple (for example, 300 ) frame data is continuously acquired in a short period, and the incident light amount onto the photodetecting section 10 of the solid-state imaging device 1 changes by frame, so that the amount of charges which overflow from a pixel portion on a defective line to a pixel portion on a neighboring line changes by frame. In this X-ray CT apparatus 100 , by providing the solid-state imaging device 1 , effective correction can be applied to frame data. The X-ray CT apparatus 100 may include the solid-state imaging device 2 according to the second embodiment instead of the solid-state imaging device 1 according to the first embodiment.

From the invention thus described, it will be obvious that the embodiments of the invention may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended for inclusion within the scope of the following claims.