Current-mode analog baseband apparatus

This application claims the priority benefit of Taiwan application serial no. 99123835, filed on Jul. 20, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

1. Field of the Disclosure

The disclosure relates to a communication system. More particularly, the disclosure relates to a current-mode analog baseband apparatus.

2. Description of Related Art

In an ultra-wide band (UWB) wireless communication system, signal data is transmitted by orthogonal frequency division multiplexing (OFDM). To decode the signal data at a transceiver end, an analog baseband apparatus demultiplies the signal from radio frequency (RF) to baseband (0-250 MHz), and an analog to digital converter (ADC) is used to convert a baseband signal into a digital signal. During the above operations, a gain of the baseband must be consistent. However, in a present circuit design, a voltage-mode amplifier and a voltage-mode filter cannot be operated over 100 MHz. In a receiver of the UWB system, since the circuit is usually operated in a non-linear zone due to interference signals during a process of demultiplying the signal from the RF to the baseband, it is important to consider linearity. Moreover, with development of the semiconductor fabrication process, a circuit operation voltage becomes lower. Therefore, it is practical and necessary to design an analog baseband apparatus having features of rejecting interference signals, high linearity, and low operation voltage.

In a conventional intermediate frequency (IF) down-conversion design, design difficulties and power consumptions of a variable-gain amplifier and the voltage-mode filter are increased as bandwidths thereof are increased. Although the IF down-conversion can resolve a problem of direct current (DC) offset, other problems are encountered, for example, linearity and power consumption. Therefore, a direction-converter is still widely used in the UWB system. Anyway, in the present UWB system, the voltage-mode amplifier is used to implement the variable-gain amplifier. An input impedance of the voltage-mode amplifier is the greater the better (which preferably approaches infinity), and an output impedance thereof is the smaller the better (which preferably approaches 0). Contrary to the voltage-mode amplifier, an input impedance of a current-mode amplifier is the smaller the better (which preferably approaches 0), and an output impedance thereof is the greater the better (which preferably approaches infinity). In the present UWB system, the current-mode amplifier is not yet used to implement the variable-gain amplifier.

The disclosure is directed to an analog baseband apparatus, in which a current-mode structure is used to implement an analog baseband circuit.

The disclosure provides an analog baseband apparatus including a current-mode low-order filter, a first current-mode programmable gain amplifier (PGA) unit and a high-order filter. An input impedance is smaller than an output impedance in the current-mode low-order filter. An input terminal of the first current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the first current-mode PGA unit.

According to the above descriptions, regarding a broadband system, the smaller a load resistance is, the wider an operation bandwidth is, and the smaller the load resistance is, the better effect the current transmission is. Therefore, the current-mode low-order filter and the current-mode PGA unit are used to implement the analog baseband circuit, which may have characteristics of broadband and high linearity.

In order to make the aforementioned and other features and advantages of the disclosure comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a functional block schematic diagram of an analog baseband apparatus according to an exemplary embodiment of the disclosure.

FIG. 2 is a diagram illustrating an implementation of a high-order filter of FIG. 1 .

FIG. 3A is a diagram illustrating an implementation of a current-mode low-order filter of FIG. 1 .

FIG. 3B is a diagram illustrating an implementation of a current-mode amplifier of FIG. 3A .

FIG. 4 is a diagram illustrating another implementation of a current-mode low-order filter of FIG. 1 .

FIG. 5 is a diagram illustrating an implementation of a first current-mode PGA unit of FIG. 1 .

FIG. 6 is a circuit schematic diagram of a current-mode amplifier of FIG. 5 according to an exemplary embodiment of the disclosure.

FIG. 7 is a functional block schematic diagram of an analog baseband apparatus according to another exemplary embodiment of the disclosure.

FIG. 8 is a diagram illustrating a simulation result of input impedance of an analog baseband apparatus of FIG. 7 .

FIG. 9 is a gain frequency response diagram of a current-mode PGA in an analog baseband apparatus of FIG. 7 .

FIG. 10 is a diagram illustrating a frequency response simulation result of a current-mode low-order filter in an analog baseband apparatus of FIG. 7 .

FIG. 11 is a diagram illustrating a whole frequency response simulation and measurement result of an analog baseband apparatus of FIG. 7 .

FIG. 12 is a diagram illustrating a whole noise characteristic measurement result of an analog baseband apparatus of FIG. 7 .

A present complementary metal-oxide semiconductor (CMOS) amplifier has a high voltage gain. Regarding the amplifier with a fixed current consumption, a multiplication of a gain G and a bandwidth W thereof is a constant C (i.e. G×W=C). Therefore, to obtain a relatively high bandwidth W and relatively high gain G, power consumption has to be increased. However, a baseband requirement of ultra-wide band (UWB) cannot be reached regardless of how greater the power consumption is, so that a method of adding a zero pole to the amplifier is used to increase the multiplication of the gain and the bandwidth. However, when the bandwidth becomes greater (greater than 250 MHz), such method is inapplicable.

Most of the present analog baseband apparatus are constructed based on a circuit principle of V=I×R, and apply a voltage signal transmission mode without using a current signal transmission mode. In the present analog baseband apparatus, a current-mode amplifier is not yet used to implement a variable-gain amplifier and a filter.

Regarding a broadband system, the smaller a load resistance is, the wider an operation bandwidth is, and the smaller the load resistance is, the better effect the current transmission is. Therefore, in the following exemplary embodiments, a current-mode circuit structure is used to implement the UWB analog baseband apparatus. The analog baseband apparatus using the current-mode amplifier has characteristics of broadband and high linearity. Since an applicable bandwidth of the current-mode amplifier can be more than 1 GHz, the analog baseband apparatus can be very competitive in a future ultra-wide band application.

FIG. 1 is a functional block schematic diagram of an analog baseband apparatus 100 according to an exemplary embodiment of the disclosure. The analog baseband apparatus 100 includes a current-mode low-order filter 110 , a first current-mode programmable gain amplifier (PGA) unit 120 and a high-order filter 130 . An input terminal of the current-mode low-order filter 110 receives a current-mode radio frequency (RF) signal I in . An input impedance of the current-mode low-order filter 110 is smaller than an output impedance thereof. The input impedance of the current-mode low-order filter 110 is the smaller the better (which preferably approaches 0), and the output impedance thereof is the greater the better (which preferably approaches infinity).

An input terminal of the first current-mode PGA unit 120 is connected to an output terminal of the current-mode low-order filter 110 , and is used for receiving an output signal I 1 of the current-mode low-order filter 110 . An input impedance of the first current-mode PGA unit 120 is smaller than an output impedance thereof. The input impedance of the first current-mode PGA unit 120 is the smaller the better (which preferably approaches 0), and the output impedance thereof is the greater the better (which preferably approaches infinity).

An input terminal of the high-order filter 130 is connected to an output terminal of the first current-mode PGA unit 120 , and is used for receiving an output signal I 2 of the first current-mode PGA unit 120 . According to different implementations of the high-order filter 130 , an output signal I 3 can be a voltage-mode signal or a current-mode signal. The high-order filter 130 can be a current-mode filter or a voltage-mode filter of any type. For example, the high-order filter 130 can be a well-known gm-C low-pass filter.

FIG. 2 is a diagram illustrating an implementation of the high-order filter 130 of FIG. 1 . The high-order filter 130 may include a current-to-voltage converter 210 , a gm-C low-pass filter 220 and a voltage-to-current converter 230 . A current input terminal of the current-to-voltage converter 210 is connected to the output terminal of the first current-mode PGA unit 120 for receiving the current-mode output signal I 2 . An input terminal of the gm-C low-pass filter 220 is connected to a voltage output terminal of the current-to-voltage converter 210 for receiving a voltage-mode output signal. The gm-C low-pass filter 220 may perform a high-order (for example, 6-order) filtering. A voltage input terminal of the voltage-to-current converter 230 is connected to the output terminal of the gm-C low-pass filter 220 for receiving a voltage-mode filtering result. A current output terminal of the voltage-to-current converter 230 is connected to the output terminal of the high-order filter 130 for providing the current-mode output signal I 3 .

The high-order filter 130 can be a current-mode filter using current conveyors. For example, the current conveyors can be used to form an integrator, and the integrator is used to form the high-order current-mode filter. Such current-mode filter is a well-known technique, so that a detailed description thereof is not repeated herein. An article authored by C. M. Chang, entitled “ Multifunction biquadratic filters using current conveyors ” (IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 44, 956-958, 1997), or an article authored by Svoboda, J. A., entitled “ Comparison of RC OP - Amp. And RC current conveyor filter ” (Int. J. ELECTION., 76 (4), pp. 615-626, 1994), or an article authored by SOLIMAN A. M, entitled “ Current conveyor filters: classification and review ” (Microelectron. J., 29, pp. 133-149, 1998), etc. may all be used as references to implement the high-order filter 130 of FIG. 1 . The above documents are entirely incorporated by reference herein.

The current-mode low-order filter 110 of FIG. 1 can be a current-mode low-pass filter of any type, for example, a current-mode Sallen Key (SK) low-pass filter, etc. FIG. 3A is a diagram illustrating an implementation of the current-mode low-order filter 110 of FIG. 1 . In FIG. 3A , the circuit of the current-mode low-order filter 110 has a single-ended structure. The current-mode low-order filter 110 includes a current-mode amplifier 310 , an output capacitor C 1 , a feedback capacitor C 2 , a first resistor R 1 and a second resistor R 2 . The current-mode amplifier 310 can be a current-mode amplifier of any type. Ideally, an input terminal of the current-mode amplifier 310 can be equivalent to an input impedance r i , and an output terminal thereof can be equivalent to a current source 311 . If a current flowing through the input impedance r i is i 1 , a current of the current source 311 is F times greater than the current i 1 (i.e. F×i 1 ). The input impedance r i of the current-mode amplifier 310 is smaller than an output impedance thereof (an impedance of the current source 311 ). The input impedance r i of the current-mode amplifier 310 is the smaller the better (which preferably approaches 0). The smaller the input impedance r i is, the better effect the current transmission of the RF signal I in is, and the smaller the input impedance r i is, the wider an operation bandwidth is.

The input terminal of the current-mode amplifier 310 serves as the input terminal of the current-mode low-order filter 110 for receiving the RF signal I in . A first end of the feedback capacitor C 2 is connected to the input terminal of the current-mode amplifier 310 . A first end of the output capacitor C 1 and a first end of the first resistor R 1 are all connected to the output terminal of the current-mode amplifier 310 . A second end of the first resistor R 1 and a first end of the second resistor R 2 are all connected to a second end of the feedback capacitor C 2 . A second end of the second resistor R 2 serves as the output terminal of the current-mode low-order filter 110 .

FIG. 3B is a diagram illustrating an implementation of the current-mode amplifier 310 of FIG. 3A . Referring to FIG. 3B , the current-mode amplifier 310 includes a current source 312 , a current source 313 , a voltage-mode amplifier 314 , a voltage-mode amplifier 315 , and transistors T 1 -T 10 , wherein the transistors T 1 , T 4 , T 7 , T 8 and T 10 are P-channel metal oxide semiconductor (PMOS) transistors, and the other transistors are N-channel metal oxide semiconductor (NMOS) transistors. A first end of the current source 312 is connected to a drain of the transistor T 9 , and a second end of the current source 312 is connected to a power voltage VDD. A gate of the transistor T 9 is connected to the drain of the transistor T 9 , and a source of the transistor T 9 is connected to a source of the transistor T 10 . A gate of the transistor T 10 is connected to a drain of the transistor T 10 . A first end of the current source 313 is connected to the drain of the transistor T 10 , and a second end of the current source 313 is connected to a ground voltage.

Sources of the transistors T 1 and T 2 are connected to the input terminal of the current-mode amplifier 310 for receiving the RF signal A gate of the transistor T 2 is connected to the gate of the transistor 19 . A drain of the transistor T 7 is connected to a drain of the transistor T 2 . A source of the transistor T 7 is connected to the power voltage VDD. An output terminal of the voltage-mode amplifier 314 is connected to gates of the transistors T 7 and T 8 . A non-inverted input terminal of the voltage-mode amplifier 314 is connected to the drain of the transistor T 2 , and an inverted input terminal of the voltage-mode amplifier 314 is connected to a source of the transistor T 4 .

A gate of the transistor T 1 is connected to the gate of the transistor T 10 . A drain of the transistor T 5 is connected to a drain of the transistor T 1 , and a source of the transistor T 5 is coupled to the ground voltage. An output terminal of the voltage-mode amplifier 315 is connected to gates of the transistors T 5 and T 6 . A non-inverted input terminal of the voltage-mode amplifier 315 is connected to the drain of the transistor T 1 , and an inverted input terminal of the voltage-mode amplifier 315 is connected to a source of the transistor T 3 .

A gate of the transistor T 6 is connected to the gate of the transistor T 5 , a source of the transistor T 6 is connected to the ground voltage, and a drain of the transistor T 6 is connected to the source of the transistor T 3 . A gate of the transistor T 3 receives a bias voltage V b2 . The gate of the transistor T 8 is connected to the gate of the transistor T 7 . A source of the transistor T 8 is connected to the power voltage VDD, and a drain of the transistor T 8 is connected to the source of the transistor T 4 . A gate of the transistor T 4 receives a bias voltage V b1 . Drains of the transistor T 3 and T 4 are connected to the output terminal of the current-mode amplifier 310 for providing a current i o .

FIG. 4 is a diagram illustrating another implementation of the current-mode low-order filter 110 of FIG. 1 . In FIG. 4 , the circuit of the current-mode low-order filter 110 has a double-ended (a differential pair) structure. In the present exemplary embodiment, the RF signal I in of FIG. 1 includes a first RF signal I in+ and a second RF signal I 1− , and the output signal I 1 includes a first output signal I 1+ and a second output signal I 1− .

The current-mode low-order filter 110 includes a current-mode amplifier 400 , a first output capacitor C 1 , a second output capacitor C 3 , a first feedback capacitor C 2 , a second feedback capacitor C 4 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 and a fourth resistor R 4 . A first input terminal and a second input terminal of the current-mode amplifier 400 serve as the input terminal of the current-mode low-order filter 110 for respectively receiving the current-mode RF signals I in + and I in− . A first end of the first feedback capacitor C 2 and a first end of the second feedback capacitor C 4 are respectively connected to the first input terminal and the second input terminal of the current-mode amplifier 400 . A first end of the first output capacitor C 1 and a first end of the second output capacitor C 3 are respectively connected to a first output terminal and a second output terminal of the current-mode amplifier 400 . A first end of the first resistor R 1 and a first end of the third resistor R 3 are respectively connected to the first output terminal of the current-mode amplifier 400 . A second end of the first resistor R 1 and a second end of the third resistor R 3 are respectively connected to a second end of the first feedback capacitor C 2 and a second end of the second feedback capacitor C 4 . A first end of the second resistor R 2 and a first end of the fourth resistor R 4 are respectively connected to the second end of the first resistor R 1 and the second end of the third resistor R 3 . A second end of the second resistor R 2 and a second end of the fourth resistor R 4 respectively serve as the output terminal of the current-mode low-order filter 110 for respectively providing the output signals I 1+ and I 1− to the first current-mode PGA unit 120 .

The current-mode amplifier 400 includes a feedback circuit 410 , an input stage 420 and an output stage 430 . A first input terminal and a second input terminal of the input stage 420 respectively serve as the first input terminal and the second input terminal of the current-mode amplifier 400 for receiving the input currents I in+ and I in− . The input stage 420 generates corresponding inner currents I inner+ and I inner− according to the input currents I in+ and feedback currents I fb+ and I fb− of the feedback circuit 410 . The input stage 420 may use a common gate or common source complementary metal-oxide semiconductor (CMOS) amplifier in collaboration with the feedback circuit 410 to achieve an effect of reducing the input impedance. In other exemplary embodiments, the input stage 420 may use a common base bipolar junction transistor (BJT) amplifier in collaboration with the feedback circuit 410 to achieve the effect of reducing the input impedance.

The feedback circuit 410 is connected to the input stage 420 . The feedback circuit 410 generates the corresponding feedback currents I fb+ and I fb− according to the inner currents I inner+ and I inner− of the input stage 420 . In some exemplary embodiments, the feedback circuit 410 can be a trans-impedance amplifier (TIA). A relationship of the inner currents I inner+ and I inner− , the input currents I in+ and I in− , and the feedback currents I fb+ and I fb− is determined according to a design requirement. For example, the inner current I inner+ is a sum of the input current I in+ and the feedback current I fb+ , and the inner current I inner− is a sum of the input current I in− and the feedback current I fb− . The feedback circuit 410 may reduce the input impedance of the input stage 420 , so as to achieve a purpose of broadband.

A first input terminal and a second input terminal of the output stage 430 are connected to a first output terminal and a second output terminal of the input stage 420 . The output stage 430 may mirror the inner currents I inner+ and I inner− of the input stage 420 to internal of the output stage 430 . A first output terminal and a second output terminal of the output stage 430 respectively serve as the first output terminal and the second output terminal of the current-mode amplifier 400 .

In FIG. 4 , the input stage 420 includes a current source 421 , a current source 422 , a transistor M 1 , a transistor M 1 b , a transistor M 2 and a transistor M 2 b . In the present embodiment, the transistor M 1 and the transistor M 1 b are PMOS transistors, and the transistor M 2 and the transistor M 2 b are NMOS transistors.

A first end of the current source 421 is connected to a first end (for example, a source) of the transistor M 1 , and a second end of the current source 421 is connected to a first reference voltage (for example, the power voltage VDD). The first end of the transistor M 1 is further connected to the first input terminal of the input stage 420 , so that the first end of the transistor M 1 may receive a current I ss1 of the current source 421 and the first input current I in+ of the input stage 420 . A first end of the current source 422 is connected to a first end (for example, a source) of the transistor M 1 b , and a second end of the current source 422 is connected to the first reference voltage. The first end of the transistor M 1 b is further connected to the second input terminal of the input stage 420 , so that the first end of the transistor M 1 b may receive the current I ss2 of the current source 422 and the second input current I in− of the input stage 420 .

Control ends (for example, gates) of the transistor M 1 and the transistor M 1 b are controlled by the feedback circuit 410 . A second end (for example, a drain) of the transistor M 1 is connected to a first end (for example, a drain) of the transistor M 2 . A control end (for example, a gate) of the transistor M 2 is connected to the first end of the transistor M 2 . A common node of the transistor M 2 and the transistor M 1 is connected to the first output terminal of the input stage 420 for providing a first inner signal 401 to the output stage 430 . A second end (for example, a drain) of the transistor M 1 b is connected to a first end (for example, a drain) of the transistor M 2 b . A control end (for example, a gate) of the transistor M 2 b is connected to the first end of the transistor M 2 b . A common node of the transistor M 2 b and the transistor M 1 b is connected to the second output terminal of the input stage 420 for providing a second inner signal 402 to the output stage 430 . Second ends (for example, sources) of the transistor M 2 and the transistor M 2 b are connected to a second reference voltage (for example, the ground voltage).

The feedback circuit 410 includes impedances 411 and 412 , a transistor M 3 and a transistor M 3 b . The impedance 411 and the impedance 412 can be impedance devices such as resistors, transistors, or diodes, etc. In the present exemplary embodiment, the impedance 411 includes a transistor M 4 , and the impedance 412 includes a transistor M 4 b . In the present exemplary embodiment, the transistor M 3 , the transistor M 3 B, the transistor M 4 and the transistor M 4 b are NMOS transistors.

A first end (for example, a drain) of the transistor M 4 is connected to the first reference voltage, and a second end (for example, a source) of the transistor M 4 is connected to the control end of the transistor M 1 . A first end (for example, a drain) of the transistor M 3 is connected to the second end of the transistor M 4 , a second end (for example, a source) of the transistor M 3 is connected to the second reference voltage, and a control end (for example, a gate) of the transistor M 3 is connected to the first end of the transistor M 2 . The transistor M 2 and the transistor M 3 form a current mirror, so that the feedback circuit 410 can generate the corresponding feedback current I fb+ according to the inner current I inner+ of the input stage 420 . The transistor M 4 may convert the feedback current I fb+ into a corresponding control voltage to control the transistor M 1 , so as to reduce the input impedance of the input stage 420 and achieve the purpose of broadband. By adjusting a bias VB n1 , a gain of the feedback current I fb+ can be changed. In the present exemplary embodiment, a relationship of the inner current I inner+ , the input current I in+ and the feedback current I fb+ is I inner+ =I in+ +I fb+ .

A first end (for example, a drain) of the transistor M 4 b is connected to the first reference voltage, and a second end (for example, a source) of the transistor M 4 b is connected to the control end of the transistor M 1 b . A first end (for example, a drain) of the transistor M 3 b is connected to the second end of the transistor M 4 b , a second end (for example, a source) of the transistor M 3 b is connected to the second reference voltage, and a control end (for example, a gate) of the transistor M 4 b is connected to the first end of the transistor M 2 b . The transistor M 2 b and the transistor M 3 b form a current mirror, so that the feedback circuit 410 can generate a corresponding feedback current I fb− according to the inner current I inner− of the input stage 420 . The transistor M 4 b may convert the feedback current I fb− into a corresponding control voltage to control the transistor M 1 b , so as to reduce the input impedance of the input stage 420 and achieve the purpose of broadband. By adjusting the bias VB n1 , a gain of the feedback current I fb− can be changed. In the present exemplary embodiment, a relationship of the inner current I inner− , the input current I in− and the feedback current I fb− is I inner− =I in− +I fb− .

The output stage 430 includes a transistor M 9 , a transistor M 10 , a transistor M 11 , a transistor M 12 , a transistor M 13 and a transistor M 14 . In the present exemplary embodiment, the transistors M 9 and M 10 are PMOS transistors, and the transistors M 11 , M 12 , M 13 and M 14 are NMOS transistors. A first end (for example, a drain) of the transistor M 9 is connected to the first output terminal of the output stage 430 . A first end (for example, a drain) of the transistor M 10 is connected to the second output terminal of the output stage 430 . Control ends (for example, gates) of the transistors M 9 and M 10 receive a first bias VB p2 . Second ends (for example, sources) of the transistors M 9 and M 10 are connected to the first reference voltage (for example, the power voltage VDD).

A first end (for example, a drain) of the transistor M 13 is connected to the first end of the transistor M 9 , and a second end (for example, a source) of the transistor M 13 is connected to a first end (for example, a drain) of the transistor M 11 . A first end (for example, a drain) of the transistor M 14 is connected to the first end of the transistor M 10 , and a second end (for example, a source) of the transistor M 14 is connected to a first end of the transistor M 12 . Control ends (for example, gates) of the transistors M 13 and M 14 receive a bias VB n2 . A control end (for example, a gate) of the transistor M 11 is connected to the first input terminal of the output stage 430 for receiving the first inner signal 401 . A control end (for example, a gate) of the transistor M 12 is connected to the second input terminal of the output stage 430 for receiving the second inner signal 402 . Second ends (for example, sources) of the transistors M 11 and M 12 are connected to the second reference voltage (for example, the ground voltage).

The transistors M 2 , M 2 b , M 3 , M 3 b , M 11 and M 12 form the current mirror structure 405 . The transistors M 2 and M 11 form a current minor, wherein channel aspect ratios (or channel width/length ratios W/L) of the transistors M 2 and M 11 are 1:F. According to the first inner signal 401 , the output stage 430 can mirror the inner current I inner+ of the input stage 420 to internal of the output stage 430 by a multiplication factor of F. Similarly, the transistors M 2 b and M 12 form another current minor, wherein channel aspect ratios (or channel width/length ratios W/L) of the transistors M 2 b and M 12 are 1:F. According to the second inner signal 402 , the output stage 430 can mirror the inner current I inner− of the input stage 420 to internal of the output stage 430 by a multiplication factor of F. By determining the proportional relation of 1:F, a current gain of the output stage 430 can be set. Now, the output stage 430 outputs a first output current signal I out+ and a second output current signal I out− according to the inner currents I inner+ and I inner− with reference of the above current gain. After the resistors R 1 , R 2 , R 3 and R 4 , and the capacitors C 1 , C 2 , C 3 and C 4 filter the current signals I out+ and I out− , signals I 1+ and I 1− (i.e. the signal I 1 of FIG. 1 ) are output to the first current-mode PGA unit 120 .

In summary, based on a local feedback mode of the feedback circuit 410 , a low impedance input stage is implemented by the transistors M 1 , M 2 , M 1 b and M 2 b . The inner currents I inner+ and I inner− of the input stage 420 are respectively transmitted (mirrored) to the output stage 430 by a predetermined multiplication factor by using the current mirror structure 405 . An input impedance Z in of the current-mode amplifier 400 of FIG. 4 in an s-domain can be represented by a following equation (1):

Z in = 1 g m ⁢ ⁢ 1 · s 2 ⁢ C A ⁢ C B + S ⁡ ( C A ⁢ g m ⁢ ⁢ 2 + C B ⁢ g m ⁢ ⁢ 4 ) + ( g m ⁢ ⁢ 4 ⁢ g m ⁢ ⁢ 2 - g m ⁢ ⁢ 1 ⁢ g m ⁢ ⁢ 3 ) s 3 ⁢ C A ⁢ C B ⁢ C in g m ⁢ ⁢ 1 + s 2 ⁡ [ C A ⁢ C B + C in g m ⁢ ⁢ 1 ⁢ ( C A ⁢ g m ⁢ ⁢ 2 + C B ⁢ g m ⁢ ⁢ 4 ) ] + s ⁡ [ C A ⁢ g m ⁢ ⁢ 2 + C B ⁢ g m ⁢ ⁢ 4 + C in g m ⁢ ⁢ 1 ⁢ ( g m ⁢ ⁢ 4 ⁢ g m ⁢ ⁢ 2 - g m ⁢ ⁢ 1 ⁢ g m ⁢ ⁢ 3 ) ] + g m ⁢ ⁢ 4 ⁢ g m ⁢ ⁢ 2 equation ⁢ ⁢ ( 1 )

Wherein, g m1 , g m2 , g m3 and g m4 respectively represent conductances of the transistors M 1 , M 2 , M 3 and M 4 . C in represents a parasitic capacitance of the first input terminal of the input stage 420 . A parasitic capacitance C A =C gs4 C ds4 C ds3 , wherein C gs4 represents a parasitic capacitance from the gate to the source of the transistor M 4 , C ds4 represents a parasitic capacitance from the drain to the source of the transistor M 4 , and C ds3 represents a parasitic capacitance from the drain to the source of the transistor M 3 . A parasitic capacitance C B =C gs2 C ds2 C gs3 , wherein C gs2 represents a parasitic capacitance from the gate to the source of the transistor M 2 , C ds2 represents a parasitic capacitance from the drain to the source of the transistor M 2 , and C gs3 represents a parasitic capacitance from the gate to the source of the transistor M 3 . In case of a low frequency, the equation (1) can be simplified as:

Therefore, the input impedance can be reduced through the feedback circuit 410 , so as to achieve the purpose of broadband.

In other exemplary embodiments, the transistors M 13 and M 14 can be omitted, so that the first end of the transistor M 11 and the first end of the transistor M 12 are respectively connected to the first end of the transistor M 9 and the first end of the transistor M 10 , directly. Moreover, in other exemplary embodiments, the transistors M 1 , M 1 b , M 9 and M 10 show in FIG. 4 can be NMOS transistors, and the other transistors can be PMOS transistors. The drains of the transistor M 4 and M 4 b , the sources of the transistors M 9 and M 10 , and the current sources 421 and 422 can be connected to the ground voltage. The sources of the transistors M 3 , M 3 b , M 2 , M 2 b , M 11 and M 12 can be connected to the power voltage VDD.

FIG. 5 is a diagram illustrating an implementation of the first current-mode PGA unit 120 of FIG. 1 . In FIG. 5 , a single current-mode amplifier is used to implement the first current-mode PGA unit 120 . In other exemplary embodiments, the first current-mode PGA unit 120 can be implemented by a plurality of current-mode amplifiers mutually connected in series.

As shown in FIG. 5 , the first current-mode PGA unit 120 includes a feedback circuit 510 , an input stage 520 and an output stage 530 . The input stage 520 has an input terminal for receiving an input current (the output signal I 1 of the current-mode low-order filter 110 ). The input stage 520 generates a corresponding inner current according to the signal I 1 and a feedback current of the feedback circuit 510 . The input stage 520 may use a common source complementary metal-oxide semiconductor (CMOS) amplifier in collaboration with the feedback circuit 510 to achieve an effect of reducing the input impedance. In other exemplary embodiments, the input stage 520 may use a common base bipolar junction transistor (BJT) amplifier in collaboration with the feedback circuit 510 to achieve the effect of reducing the input impedance.

The feedback circuit 510 is connected to the input stage 520 . The feedback circuit 510 generates the corresponding feedback current according to the inner current of the input stage 520 . In some exemplary embodiments, the feedback circuit 510 can be a trans-impedance amplifier (TIA). A relationship of the inner current, the input current I 1 and the feedback current is determined according to a design requirement. For example, the inner current is a sum of the input current I 1 and the feedback current. The feedback circuit 510 may reduce the input impedance of the input stage 520 , so as to achieve a purpose of broadband.

An input terminal of the output stage 530 is connected to an output terminal of the input stage 520 . An output terminal of the output stage 530 serves as an output terminal of the current-mode amplifier. The output stage 530 generates a corresponding output current (the output signal I 2 ) according to the inner current of the input stage 520 . The output stage 530 has one or a plurality of gain circuits, for example, K gain circuits 530 - 1 , 530 - 2 , . . . , 530 -K shown in FIG. 5 . According to a gain requirement, by controlling a bias voltage of each of the gain circuits 530 - 1 ˜ 530 -K, a part of the gain circuits is enabled, and the other gain circuits are disabled. By enabling and disabling the gain circuits 530 - 1 ˜ 530 -K, a gain of the current-mode amplifier is adjusted, so as to achieve a variable gain effect.

FIG. 6 is a circuit schematic diagram of the current-mode amplifier of FIG. 5 according to an exemplary embodiment of the disclosure. In the present exemplary embodiment, the input current I 1 includes a first input current I 1+ and a second input current I 1− , and the output current I 2 includes a first output current I 2+ and a second output current I 2− . In FIG. 6 , two gain circuits 530 - 1 and 530 - 2 connected in parallel are used to implement the output stage 530 , though a number of the gain circuits can be determined according to an actual design requirement. For example, the gain circuit 530 - 2 can be omitted, or more gain circuit 530 - 2 can be applied.

The input terminal of the input stage 520 includes a first input terminal used for receiving the first input current I 1+ and a second input terminal used for receiving the second input current I 2− . The output terminal of the input stage 520 include a first output terminal used for providing a first inner signal 601 and a second output terminal used for providing a second inner signal 602 . Based on a current mirror structure 610 , the input stage 520 may convert a first inner current I′ inner+ and a second inner current I′ inner− into the corresponding first inner signal 601 and the second inner signal 602 . The output stage 530 can mirror the inner currents I′ inner+ and I′ inner− of the input stage 520 to internal of the output stage 530 according to the first inner signal 601 and the second inner signal 602 .

The input stage 520 includes a first current source 521 , a second current source 522 , a transistor Q 1 , a transistor Q 1 b , a transistor Q 2 and a transistor Q 2 b . In the present exemplary embodiment, the transistors Q 1 and Q 1 b are PMOS transistors, and the transistors Q 2 and Q 2 b are NMOS transistors. A first end of the current source 521 is connected to a first end (for example, a source) of the transistor Q 1 , a second end of the current source 521 is connected to the first reference voltage (for example, the power voltage VDD). The first end of the transistor Q 1 is further connected to the first input terminal of the input stage 520 , so that the first end of the transistor Q 1 may receive a current Iss of the current source 521 and the first input current I 1+ of the input stage 520 . A first end of the current source 522 is connected to a first end (for example, a source) of the transistor Q 1 b , and a second end of the current source 522 is connected to the first reference voltage. The first end of the transistor Q 1 b is further connected to the second input terminal of the input stage 520 , so that the first end of the transistor Q 1 b may receive the current Iss of the current source 522 and the second input current I 1− of the input stage 520 .

Control ends (for example, gates) of the transistor Q 1 and the transistor Q 1 b are controlled by the feedback circuit 510 . A second end (for example, a drain) of the transistor Q 1 is connected to a first end (for example, a drain) of the transistor Q 2 . A control end (for example, a gate) of the transistor Q 2 is connected to the first end of the transistor Q 2 . A common node of the transistor Q 2 and the transistor Q 1 is connected to the first output terminal of the input stage 520 for providing the first inner signal 601 . A second end (for example, a drain) of the transistor Q 1 b is connected to a first end (for example, a drain) of the transistor Q 2 b . A control end (for example, a gate) of the transistor Q 2 b is connected to the first end of the transistor Q 2 b . A common node of the transistor Q 2 b and the transistor Q 1 b is connected to the second output terminal of the input stage 520 for providing the second inner signal 502 . Second ends (for example, sources) of the transistor Q 2 and the transistor Q 2 b are connected to the second reference voltage (for example, the ground voltage).

The feedback circuit 510 includes a first impedance 511 , a second impedance 512 , a transistor Q 3 and a transistor Q 3 b . The first impedance 511 and the second impedance 512 can be impedance devices such as resistors, transistors, or diodes, etc. In the present exemplary embodiment, the first impedance 511 includes a transistor Q 4 , and the second impedance 512 includes a transistor Q 4 b . In the present exemplary embodiment, the transistor Q 3 , the transistor Q 3 B, the transistor Q 4 and the transistor Q 4 b are NMOS transistors.

A first end (for example, a drain) of the transistor Q 4 is connected to the first reference voltage, and a second end (for example, a source) of the transistor Q 4 is connected to the control end of the transistor Q 1 . A first end (for example, a drain) of the transistor Q 3 is connected to the second end of the transistor Q 4 , a second end (for example, a source) of the transistor Q 3 is connected to the second reference voltage, and a control end (for example, a gate) of the transistor Q 3 is connected to the first end of the transistor Q 2 . The transistor Q 2 and the transistor Q 3 form a current mirror, so that the feedback circuit 510 can generate a corresponding feedback current I′ fb+ according to the inner current I′ inner+ of the input stage 520 . The transistor Q 4 may convert the feedback current I′ fb+ into a corresponding control voltage to control the transistor Q 1 , so as to reduce the input impedance of the input stage 520 and achieve the purpose of broadband. By adjusting the bias VB n1 , a gain of the feedback current I′ fb+ can be changed. In the present exemplary embodiment, a relationship of the inner current I′ inner+ , the input current I 1+ and the feedback current I′ fb+ is F inner+ =I 1+ +I′ fb+ .

A first end (for example, a drain) of the transistor Q 4 b is connected to the first reference voltage, and a second end (for example, a source) of the transistor Q 4 b is connected to the control end of the transistor Q 1 b . A first end (for example, a drain) of the transistor Q 3 b is connected to the second end of the transistor Q 4 b , a second end (for example, a source) of the transistor Q 3 b is connected to the second reference voltage, and a control end (for example, a gate) of the transistor Q 3 b is connected to the first end of the transistor Q 2 b . The transistor Q 2 b and the transistor Q 3 b form a current mirror, so that the feedback circuit 510 can generate a corresponding feedback current I′ fb− according to the inner current I′ inner− of the input stage 520 . The transistor Q 4 b may convert the feedback current I′ fb− into a corresponding control voltage to control the transistor Q 1 b , so as to reduce the input impedance of the input stage 520 and achieve the purpose of broadband. By adjusting the bias VB n1 , a gain of the feedback current I′ fb− can be changed. In the present exemplary embodiment, a relationship of the inner current I′ inner− , the input current I 1− and the feedback current I′ fb− is I′ inner− =I 1− +I′ fb− .

The input terminal of the output stage 530 includes a first input terminal used for receiving the first inner signal 601 and a second input terminal used for receiving the second inner signal 602 , and the output terminal of the output stage 530 includes a first output terminal used for providing the first output current I 2+ and a second output terminal used for providing the second output current I 2− . The gain circuit 530 - 1 of the output stage 530 includes a transistor Q 9 , a transistor Q 10 , a transistor Q 11 , a transistor Q 12 , a transistor Q 13 and a transistor Q 14 . In the present exemplary embodiment, the transistors Q 9 and Q 10 are PMOS transistors, and the transistors Q 11 , Q 12 , Q 13 and Q 14 are NMOS transistors. A first end (for example, a drain) of the transistor Q 9 is connected to the first output terminal of the output stage 530 and a first end (for example, a drain) of the transistor Q 13 . A control end (for example, a gate) of the transistor Q 9 receives a first bias VB. A first end (for example, a drain) of the transistor Q 10 is connected to the second output terminal of the output stage 530 and a first end (for example, a drain) of the transistor Q 14 . Second ends (for example, sources) of the transistors Q 9 and Q 10 are connected to the first reference voltage (for example, the power voltage VDD). A control end (for example, a gate) of the transistor Q 10 receives the first bias VB. The first bias VB can be a band-gap reference voltage or a common-mode feedback (CMFB) voltage or other fixed voltages.

Control ends (for example, gates) of the transistors Q 13 and Q 14 receive the second bias VB n2 . The second bias VB n2 can be a band-gap reference voltage or other fixed voltages. A second end (for example, a source) of the transistor Q 13 is connected to a first end (for example, a drain) of the transistor Q 11 . A second end (for example, a source) of the transistor Q 14 is connected to a first end (for example, a drain) of the transistor Q 12 . A control end (for example, a gate) of the transistor Q 11 is connected to the first input terminal of the output stage 530 for receiving the first inner signal 601 . A control end (for example, a gate) of the transistor Q 12 is connected to the second input terminal of the output stage 530 for receiving the second inner signal 602 . Second ends (for example, sources) of the transistors Q 11 and Q 12 are connected to the second reference voltage (for example, the ground voltage).

The gain circuit 530 - 2 of the output stage 530 includes a first switch SWp, a second switch SWn, a transistor Q 15 , a transistor Q 16 , a transistor Q 17 , a transistor Q 18 , a transistor Q 19 and a transistor Q 20 . In the present exemplary embodiment, the transistors Q 15 and Q 16 are PMOS transistors, and the transistors Q 17 , Q 18 , Q 19 and Q 20 are NMOS transistors. A first end (for example, a drain) of the transistor Q 15 is connected to the first output terminal of the output stage 530 and a first end (for example, a drain) of the transistor Q 19 . A first end (for example, a drain) of the transistor M 16 is connected to the second output terminal of the output stage 530 and a first end (for example, a drain) of the transistor Q 20 . Second ends (for example, sources) of the transistors Q 15 and Q 16 are connected to the first reference voltage (for example, the power voltage VDD). The first bias VB or the first reference voltage (for example, the power voltage VDD) is selected and transmitted to control ends (for example, gates) of the transistors Q 15 and Q 16 through the first switch SWp.

A second end (for example, a source) of the transistor Q 19 is connected to a first end (for example, a drain) of the transistor Q 17 . A second end (for example, a source) of the transistor Q 20 is connected to a first end (for example, a drain) of the transistor Q 18 . The second bias VB n2 or the second reference voltage (for example, the ground voltage) is selected and transmitted to control ends (for example, gates) of the transistors Q 19 and Q 20 through the second switch SWn. A control end (for example, a gate) of the transistor Q 17 is connected to the first input terminal of the output stage 530 for receiving the first inner signal 601 . A control end (for example, a gate) of the transistor Q 18 is connected to the second input terminal of the output stage 530 for receiving the second inner signal 602 . Second ends (for example, sources) of the transistors Q 17 and Q 18 are connected to the second reference voltage (for example, the ground voltage).

When the first bias VB is selected and transmitted to the control ends of the transistors Q 15 and Q 16 through the first switch SWp, and the second bias VB n2 is selected and transmitted to the control ends of the transistors Q 19 and Q 20 through the second switch SWn, a circuit structure of the gain circuit 530 - 2 is similar to that of the gain circuit 530 - 1 . The transistors Q 2 , Q 2 b , Q 11 , Q 12 , Q 17 and Q 18 form the current mirror structure 610 . The transistors Q 2 , Q 11 and Q 17 form a current mirror, wherein channel aspect ratios (or channel width/length ratios W/L) of the transistors Q 2 , Q 11 and Q 17 are 1:M:N. According to the first inner signal 601 , the gain circuits 530 - 1 and the 530 - 2 can respectively mirror the inner current I′ inner+ of the input stage 520 to internals of the gain circuits 530 - 1 and 530 - 2 by multiplication factors of M and N. The transistors Q 2 b , Q 12 and Q 18 form another current mirror, wherein channel aspect ratios (or channel width/length ratios W/L) of the transistors Q 2 b , Q 12 and Q 18 are 1:M:N. According to the second inner signal 602 , the gain circuits 530 - 1 and the 530 - 2 can respectively mirror the inner current I′ inner− to internals of the gain circuits 530 - 1 and 530 - 2 by multiplication factors of M and N. By determining the proportional relation of 1:M:N, current gains of the gain circuits 530 - 1 and 530 - 2 can be set. Now, the gain circuits 530 - 1 and 530 - 2 commonly provide the first output current I 2+ and the second output current I 2− , namely, the current-mode amplifier has a relatively great output gain.

When the power voltage VDD is selected and transmitted to the control ends of the transistors Q 15 and Q 16 through the first switch SWp, and the ground voltage is selected and transmitted to the control ends of the transistors Q 19 and Q 20 through the second switch SWn, the transistors Q 15 , Q 16 , Q 19 and Q 20 are turned off, which is equivalent to a situation that the gain circuit 530 - 2 is disabled. By turning off the transistors Q 15 , Q 16 , Q 19 and Q 20 , it can be ensured that the disabled gain circuit 530 - 2 does not influence the output currents I 2+ and I 2− of the output stage 530 . Now, the first output current I 2+ and the second output current I 2− are provided by the gain circuit 530 - 1 alone, namely, the current-mode amplifier has a relatively small output gain. Therefore, by controlling the first switch SWp and the second switch SWn, the gain of the current-mode amplifier can be changed, so as to achieve an effect of a variable gain amplifier (VGA).

In other exemplary embodiments, the second switch SWn, the transistors Q 13 , Q 14 , Q 19 and Q 20 can be omitted, so that the drains of the transistors Q 11 , Q 12 , Q 17 and Q 18 can be respectively connected to the drains of the transistors Q 9 , Q 10 , Q 15 and Q 16 , directly. Moreover, in other exemplary embodiments, the transistors Q 1 , Q 1 b , Q 9 , Q 10 , Q 15 and Q 16 of FIG. 6 can be NMOS transistors, and the other transistors thereof can be PMOS transistors. The drains of the transistors Q 4 and Q 4 b , the sources of the transistors Q 9 , Q 10 , Q 15 and Q 16 , and the current sources 521 and 522 can be connected to the ground voltage, and the sources of the transistors Q 3 , Q 3 b , Q 2 , Q 2 b , Q 11 , Q 12 , Q 17 and Q 18 can be connected to the power voltage VDD.

The analog baseband apparatus 100 of FIG. 1 can used to implement an analog baseband structure of a UWB wireless transceiver system, as that shown in FIG. 7 . FIG. 7 is a functional block schematic diagram of an analog baseband apparatus 700 according to another exemplary embodiment of the disclosure. The analog baseband apparatus 700 can be widely applied to various wireless/cable broadband systems, and can be used to implement an analog baseband circuit in the broadband system for adjusting a magnitude of a received signal and filter interference signals outside the channels.

The analog baseband apparatus 700 has an in-phase component signal path and a quadrature-phase component signal path. The in-phase component signal path includes the current-mode low-order filter 110 , the first current-mode PGA unit 120 , the high-order filter 130 , a current-mode second PGA unit 740 , a current-to-voltage converter 760 and a buffer 780 . The in-phase component signal path directly demultiplies a current-mode RF signal pair I in+ I and I in− I to a voltage-mode baseband signal pair V out+ I and V out− I .

The current-mode low-order filter 110 receives the current-mode RF signal pair I in+ I and I in− I . Implementations of the current-mode low-order filter 110 , the first current-mode PGA unit 120 , and the high-order filter 130 of FIG. 7 are as that described in the exemplary embodiment of FIG. 1 , so that detailed descriptions thereof are not repeated. An input terminal of the second current-mode PGA unit 740 is connected to the output terminal of the high-order filter 130 . A current input terminal of the current-to-voltage converter 760 is connected to an output terminal of the second current-mode PGA unit 740 . An input terminal of the buffer 780 is connected to a voltage output terminal of the current-to-voltage converter 760 . The voltage output terminal of the current-to-voltage converter 760 provides the voltage-mode baseband signal pair V out+ I and V out− I .

The first current-mode PGA unit 120 and the second current-mode PGA unit 740 can be respectively implemented by one or a plurality of current-mode programmable gain amplifiers (PGAs). The current-mode PGAs can be current-mode amplifiers of any type, for example, the current-mode amplifiers shown in FIG. 3B and FIG. 5 or other types of the current amplifiers, etc. Implementation of the first current-mode PGA unit 120 can be the same to that of the second current-mode PGA unit 740 . In other exemplary embodiments, implementation of the first current-mode PGA unit 120 can be different to that of the second current-mode PGA unit 740 . Moreover, implementation of the current-to-voltage converter 760 is not limited by the disclosure, and any circuit/device capable of converting a current-mode signal into a voltage-mode signal can be used to implement the current-to-voltage converter 760 . For example, a current-mode signal may flow through a resistor, and the resistor can be used to convert the current-mode signal into a voltage-mode signal.

The quadrature-phase component signal path includes a second current-mode low-order filter 710 , a third current-mode PGA unit 720 , a second high-order filter 730 , a fourth current-mode PGA unit 750 , a second current-to-voltage converter 770 and a second buffer 790 . The quadrature-phase component signal path directly demultiplies a current-mode RF signal pair I in+ Q and I in− Q to a voltage-mode baseband signal pair V out− Q and I out− Q . Implementations of the second current-mode low-order filter 710 , the third current-mode PGA unit 720 , the second high-order filter 730 , the fourth current-mode PGA unit 750 , the second current-to-voltage converter 770 and the second buffer 790 are the same as that of the current-mode low-order filter 110 , the first current-mode PGA unit 120 , the high-order filter 130 , the second current-mode PGA unit 740 , the current-to-voltage converter 760 and the buffer 780 .

The current-mode low-order filters 110 and 710 first provide a preliminary filtering of the interference signals outside the channels, so as to relax a linearity requirement of the post-stage current-mode PGA units 120 and 720 . High-order filtering of the interference signals outside the channels is performed through the high-order filters 130 and 730 in the analog baseband apparatus 700 . Based on such configuration, noise and linearity characteristic performance of the whole analog baseband apparatus 700 are simultaneously taken into consideration, so as to achieve an optimal signal-to-noise ratio characteristic.

It is assumed that the current-mode low-order filters 110 and 710 of the analog baseband apparatus 700 are current-mode Sallen-Key (SK) low-pass filters, and the high-order filters 130 and 730 are gm-C low-pass filters. FIG. 8 is a diagram illustrating a simulation result of the input impedance of the analog baseband apparatus 700 of FIG. 7 . In FIG. 8 , a vertical axis represents the input impedances, and a horizontal axis represents frequencies. According to FIG. 8 , it is known that the bandwidth of the analog baseband apparatus 700 may reach 1 GHz.

FIG. 9 is a gain frequency response diagram of the current-mode PGA (for example, the current-mode amplifiers of FIG. 5 and FIG. 6 ) of the current-mode PGA unit in the analog baseband apparatus 700 of FIG. 7 . In FIG. 9 , a vertical axis represents gains, and a horizontal axis represents frequencies. According to FIG. 9 , it is known that under different gain modulations, the current-mode amplifier may still maintain the bandwidth of 1 GHz.

FIG. 10 is a diagram illustrating a frequency response simulation result of the current-mode low-order filter 110 in the analog baseband apparatus 700 of FIG. 7 . Here, the current-mode low-order filter 110 is a current-mode SK low-pass filter. In FIG. 10 , a vertical axis represents gains, and a horizontal axis represents frequencies. According to FIG. 10 , it is known that the current-mode low-order filter 110 may preliminarily filter the interference signals outside the channels.

FIG. 11 is a diagram illustrating a whole frequency response simulation and measurement result of the analog baseband apparatus 700 of FIG. 7 . In FIG. 11 , a vertical axis represents signal magnitudes, and a horizontal axis represents frequencies. Wherein, a curve 1103 is a whole simulation frequency response curve of the analog baseband apparatus 700 in case that the current-mode low-order filters 110 and 710 are omitted, and the gm-C low-pass filters are used to implement the high-order filters 130 and 730 . A curve 1102 is a whole simulation frequency response curve of the analog baseband apparatus 700 in case that the current-mode SK low-pass filters are used to implement the current-mode low-order filters 110 and 710 , and the gm-C low-pass filters are used to implement the high-order filters 130 and 730 . A curve 1101 is an actual measurement frequency response curve of the analog baseband apparatus 700 in case of a same condition of the curve 1102 . According to FIG. 11 , it is known that the analog baseband apparatus 700 performs the high-order filtering to the interference signals outside the channels.

FIG. 12 is a diagram illustrating a whole noise characteristic measurement result of the analog baseband apparatus 700 of FIG. 7 . In FIG. 12 , a vertical axis represents a noise figure, and a horizontal axis represents frequencies. According to FIG. 12 , it is known that the analog baseband apparatus 700 has a low noise characteristic.

In summary, signals within 250 MHz are amplified according to a broadband feature of the current-mode amplifiers of the above exemplary embodiments, so as to overcome a technical difficulty that the voltage-mode amplifier cannot be operated over 100 MHz. Moreover, a gain control of the current-mode amplifier of the exemplary embodiments is achieved by controlling a current mirror, so that a problem of a gain error influenced by a fabrication variation can be resolved. The analog baseband apparatus of the disclosure is used to amplify the signal received by a receiver to a full-scale of an analog-to-digital converter, so as to reduce a demand for a dynamic range of the analog-to-digital converter, and filter the interference signals outside the channels. The analog baseband apparatus of the disclosure is adapted to be implemented by a circuit with a low operation voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.