Current-mode amplifier

This application claims the priority benefit of Taiwan application serial no. 99123838, filed on Jul. 20, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

1. Field of the Disclosure

The disclosure relates to an amplifier. More particularly, the disclosure relates to a current-mode amplifier.

2. Description of Related Art

In an ultra-wideband (UWB) wireless transceiver system, signal data is transmitted by orthogonal frequency division multiplexing (OFDM). To decode the signal data at a transceiver end, during a process of reducing signal from a radio frequency (RF) to a baseband (0-240 MHz), and an operation of an analog to digital converter (ADC), a gain of the baseband must be consistent. However, in a present circuit design, a voltage-mode amplifier cannot be operated over 100 MHz. In a receiver of the UWB system, since the circuit is usually operated in a non-linear zone due to interference signals during a process of reducing the signal from the RF to the baseband, a linearity consideration is very important. In the UWB system, a variable gain amplifier must have a good linearity, an optimal direct current (DC) offset and an acceptable anti-noise function.

In a conventional IF down-conversion design, design difficulties and power consumptions of the variable gain amplifier and a filter are increased as a bandwidth thereof is increased. Also the IF down-conversion can resolve the problem of DC offset, other problems are encountered, for example, linearity and power consumption. Therefore, a direction-converter is still widely used in the UWB system. Anyway, in the present UWB system, the voltage-mode amplifier is used to implement the variable gain amplifier. An input impedance of the voltage-mode amplifier is the greater the better (which preferably approaches infinity), and an output impedance thereof is the smaller the better (which preferably approaches 0). Contrary to the voltage-mode amplifier, an input impedance of a current-mode amplifier is the smaller the better (which preferably approaches 0), and an output impedance thereof is the greater the better (which preferably approaches infinity). In the present UWB system, the current-mode amplifier is not yet used to implement the variable gain amplifier.

The disclosure is directed to a current-mode amplifier, which can be used to implement a variable gain amplifier of an ultra-wideband (UWB) system.

An exemplary embodiment of the disclosure provides a current-mode amplifier including an input stage, a feedback circuit and an output stage. The input stage has an input terminal for receiving an input current of the current-mode amplifier. The input stage generates a corresponding inner current according to the input current and a feedback current of the feedback circuit. The feedback circuit is connected to the input stage. The feedback circuit generates the corresponding feedback current according to the inner current of the input stage. An input terminal of the output stage is connected to an output terminal of the input stage. An output terminal of the output stage serves as an output terminal of the current-mode amplifier.

According to the above descriptions, an exemplary embodiment of the disclosure provides a current-mode amplifier, which can be used to implement a variable gain amplifier in a UWB wireless transceiver system. A baseband signal is amplified according to a broadband property of the current-mode amplifier, so as to overcome a limitation that the voltage-mode amplifier cannot be operated over 100 MHz. In the disclosure, a gain control/change of the current-mode amplifier is achieved by controlling a current mirror, so that a problem of gain error influenced by fabrication variation can be resolved.

In order to make the aforementioned and other features and advantages of the disclosure comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a functional block diagram illustrating a current-mode amplifier according to an exemplary embodiment of the disclosure.

FIG. 2 is a circuit schematic diagram of a current-mode amplifier of FIG. 1 according to an exemplary embodiment of the disclosure.

FIG. 3 is a circuit schematic diagram illustrating a common-mode feedback amplifier according to an exemplary embodiment of the disclosure.

FIG. 4 is a circuit schematic diagram illustrating a current-mode amplifier of FIG. 1 according to another exemplary embodiment of the disclosure.

FIG. 5 is a diagram illustrating a simulation result of an input impedance of a feedback circuit of FIG. 4 .

FIG. 6 is a gain frequency response diagram of a current-mode amplifier of FIG. 4 .

FIG. 7 is a circuit schematic diagram illustrating a current-mode amplifier 100 of FIG. 1 according to still another exemplary embodiment of the disclosure.

FIG. 8 is a circuit schematic diagram illustrating a common-mode feedback amplifier according to another exemplary embodiment of the disclosure.

FIG. 9 is a circuit schematic diagram illustrating a current-mode amplifier of FIG. 1 according to yet another exemplary embodiment of the disclosure.

An amplifier fabricated according to a complementary metal-oxide semiconductor (CMOS) process has a high voltage gain. Regarding the amplifier with a fixed current consumption, multiplication of a gain G and a bandwidth W thereof is a constant C (i.e. G×W=C). Therefore, to obtain a relatively high bandwidth W and relatively high gain G, power consumption has to be increased. However, a baseband requirement of ultra-wideband (UWB) cannot be reached regardless of how greater the power consumption is, so that a method of adding a zero pole to the amplifier is used to increase the multiplication of the gain and the bandwidth. However, when the bandwidth becomes greater (greater than 250 MHz), such method is inapplicable.

A conventional analog baseband circuit structure generally uses a voltage-mode transmission approach without using a current-mode transmission approach. Regarding a broadband system, the smaller a load resistance is, the wider an operation bandwidth is, and the smaller the load resistance is, the better effect the current transmission is. Such characteristic avails applying a current-mode amplifier to a present or a future UWB system.

FIG. 1 is a functional block diagram illustrating a current-mode amplifier 100 according to an exemplary embodiment of the disclosure. As shown in FIG. 1 , the current-mode amplifier 100 includes a feedback circuit 110 , an input stage 120 and an output stage 130 . The input stage 120 has an input terminal for receiving an input current I in of the current-mode amplifier 100 . The input stage 120 generates a corresponding inner current according to the input current I in and a feedback current of the feedback circuit 110 . The input stage 120 may use a common gate complementary metal-oxide semiconductor (CMOS) amplifier in collaboration with the feedback circuit 110 to achieve an effect of reducing an input impedance. In other exemplary embodiment, the input stage 120 may use a common base bipolar junction transistor (BJT) amplifier in collaboration with the feedback circuit 110 to achieve the effect of reducing the input impedance.

The feedback circuit 110 is connected to the input stage 120 . The feedback circuit 110 generates the corresponding feedback current according to the inner current of the input stage 120 . In some exemplary embodiments, the feedback circuit 110 can be a trans-impedance amplifier (TIA). A relationship of the inner current, the input current I in and the feedback current is determined according to a design requirement. For example, the inner circuit is a sum of the input current I in and the feedback current. The feedback circuit 110 may reduce the input impedance of the input stage 120 , so as to achieve a purpose of broadband.

An input terminal of the output stage 130 is connected to an output terminal of the input stage 120 . An output terminal of the output stage 130 serves as an output terminal of the current-mode amplifier 100 . The output stage 130 generates a corresponding output current I out according to the inner current of the input stage 120 . The output stage 130 has one or a plurality of gain circuits, for example, K gain circuits 130 - 1 , 130 - 2 , . . . , 130 -K shown in FIG. 1 . According to a gain requirement, each of the gain circuits 130 - 1 ˜ 130 -K can enable a part of the gain circuits by controlling a bias voltage thereof, and disable the other gain circuits. By enabling and disabling the gain circuits 130 - 1 ˜ 130 -K, a gain of the current-mode amplifier 100 is adjusted, so as to achieve a variable gain effect.

FIG. 2 is a circuit schematic diagram of the current-mode amplifier 100 of FIG. 1 according to an exemplary embodiment of the disclosure. In the present exemplary embodiment, the input current I in includes a first input current I in+ and a second input current I in− , and the output current I out includes a first output current I out+ and a second output current I out− . In FIG. 2 , two gain circuits 130 - 1 and 130 - 2 connected in parallel are used to implement the output stage 130 , though a number of the gain circuits can be determined according to an actual design requirement. For example, the gain circuit 130 - 2 can be omitted, or more gain circuit 130 - 2 can be applied.

The input terminal of the input stage 120 includes a first input terminal used for receiving the first input current I in+ and a second input terminal used for receiving the second input current I in− . The output terminal of the input stage 120 include a first output terminal used for providing a first inner signal 101 and a second output terminal used for providing a second inner signal 102 . Based on a current mirror structure 210 , the input stage 120 may convert a first inner current I inner+ and a second inner current I inner− into the corresponding first inner signal 101 and the second inner signal 102 . The output stage 130 can mirror the inner currents I inner+ and I inner− of the input stage 120 to internal of the output stage 130 according to the first inner signal 101 and the second inner signal 102 .

The input stage 120 includes a first current source 121 , a second current source 122 , a first transistor M 1 , a second transistor M 1 b , a third transistor M 2 and a fourth transistor M 2 b . A first end of the first current source 121 is connected to a first end (for example, a source) of the first transistor M 1 , a second end of the first current source 121 is connected to a first reference voltage (for example, a power voltage VDD). The first end of the first transistor M 1 is further connected to the first input terminal of the input stage 120 , so that the first end of the first transistor M 1 may receive a current Iss of the first current source 121 and the first input current I in+ of the input stage 120 . A first end of the second current source 122 is connected to a first end (for example, a source) of the second transistor M 1 b , and a second end of the second current source 122 is connected to the first reference voltage. The first end of the second transistor M 1 b is further connected to the second input terminal of the input stage 120 , so that the first end of the second transistor M 1 b may receive the current Iss of the second current source 122 and the second input current I in− of the input stage 120 .

Control ends (for example, gates) of the first transistor M 1 and the second transistor M 1 b are controlled by the feedback circuit 110 . A second end (for example, a drain) of the first transistor M 1 is connected to a first end (for example, a drain) of the third transistor M 2 . A control end (for example, a gate) of the third transistor M 2 is connected to the first end of the third transistor M 2 . A common node of the third transistor M 2 and the first transistor M 1 is connected to the first output terminal of the input stage 120 for providing the first inner signal 101 . A second end (for example, a drain) of the second transistor M 1 b is connected to a first end (for example, a drain) of the fourth transistor M 2 b . A control end (for example, a gate) of the fourth transistor M 2 b is connected to the first end of the fourth transistor M 2 b . A common node of the fourth transistor M 2 b and the second transistor M 1 b is connected to the second output terminal of the input stage 120 for providing the second inner signal 102 . Second ends (for example, sources) of the third transistor M 2 and the fourth transistor M 2 b are connected to a second reference voltage (for example, a ground voltage).

In the present exemplary embodiment, the first transistor M 1 and the second transistor M 1 b are P-channel metal oxide semiconductor (PMOS) transistors, and the third transistor M 2 and the fourth transistor M 2 b are N-channel metal oxide semiconductor (NMOS) transistors.

The feedback circuit 110 includes a first impedance 111 , a second impedance 112 , a fifth transistor M 3 and a sixth transistor M 3 b . The first impedance 111 and the second impedance 112 can be impedance devices such as resistors, transistors, or diodes, etc. In the present exemplary embodiment, the first impedance 111 includes a seventh transistor M 4 , and the second impedance 112 includes an eighth transistor M 4 b . In the present exemplary embodiment, the fifth transistor M 3 , the sixth transistor M 3 B, the seventh transistor M 4 and the eighth transistor M 4 b are NMOS transistors.

A first end (for example, a drain) of the seventh transistor M 4 is connected to the first reference voltage, and a second end (for example, a source) of the seventh transistor M 4 is connected to the control end of the first transistor M 1 . A first end (for example, a drain) of the fifth transistor M 3 is connected to the second end of the seventh transistor M 4 , a second end (for example, a source) of the fifth transistor M 3 is connected to the second reference voltage, and a control end (for example, a gate) of the fifth transistor M 3 is connected to the first end of the third transistor M 2 . The third transistor M 2 and the fifth transistor M 3 form a current mirror, so that the feedback circuit 110 can generate a corresponding feedback current I fb+ according to the inner current I inner+ of the input stage 120 . The seventh transistor M 4 may convert the feedback current I fb+ into a corresponding control voltage to control the first transistor M 1 , so as to reduce the input impedance of the input stage 120 and achieve the purpose of broadband. By adjusting a bias VB n1 , a gain of the feedback current I fb+ can be changed. In the present exemplary embodiment, a relationship of the inner current I inner+ , the input current I in+ and the feedback current I fb+ is I inner+ =I in+ +I fb+ .

A first end (for example, a drain) of the eighth transistor M 4 b is connected to the first reference voltage, and a second end (for example, a source) of the eighth transistor M 4 b is connected to the control end of the second transistor M 1 b . A first end (for example, a drain) of the sixth transistor M 3 b is connected to the second end of the eighth transistor M 4 b , a second end (for example, a source) of the sixth transistor M 3 b is connected to the second reference voltage, and a control end (for example, a gate) of the sixth transistor M 4 b is connected to the first end of the fourth transistor M 2 b . The fourth transistor M 2 b and the sixth transistor M 3 b form a current mirror, so that the feedback circuit 110 can generate a corresponding feedback current I fb− according to the inner current I inner− of the input stage 120 . The eighth transistor M 4 b may convert the feedback current I fb− into a corresponding control voltage to control the second transistor M 1 b , so as to reduce the input impedance of the input stage 120 and achieve the purpose of broadband. By adjusting the bias VB n1 , a gain of the feedback current I fb− can be changed. In the present exemplary embodiment, a relationship of the inner current I inner− , the input current I in− and the feedback current I fb− is I inner− =I in− +I fb− .

The input terminal of the output stage 130 includes a first input terminal used for receiving the first inner signal 101 and a second input terminal used for receiving the second inner signal 102 , and the output terminal of the output stage 130 includes a first output terminal used for providing the first output current I out+ and a second output terminal used for providing the second output current I out− . The gain circuit 130 - 1 of the output stage 130 includes a ninth transistor M 9 , a tenth transistor M 10 , an eleventh transistor M 11 and a twelfth transistor M 12 . In the present exemplary embodiment, the ninth transistor M 9 and the tenth transistor M 10 are PMOS transistors, and the eleventh transistor M 11 and the twelfth transistor M 12 are NMOS transistors. A first end (for example, a drain) of the ninth transistor M 9 is connected to the first output terminal of the output stage 130 , and a control end (for example, a gate) of the ninth transistor M 9 receives a first bias VB. A first end (for example, a drain) of the tenth transistor M 10 is connected to the second output terminal of the output stage 130 , and a control end (for example, a gate) of the tenth transistor M 10 receives the first bias VB. Second ends (for example, sources) of the transistors M 9 and M 10 are connected to the first reference voltage (for example, the power voltage VDD).

A first end (for example, a drain) of the eleventh transistor M 11 is connected to the first end of the ninth transistor M 9 , and a control end (for example, a gate) of the eleventh transistor M 11 is connected to the first input terminal of the output stage 130 for receiving the first inner signal 101 . A first end (for example, a drain) of the twelfth transistor M 12 is connected to the first end of the tenth transistor M 10 , and a control end (for example, a gate) of the twelfth transistor M 12 is connected to the second input terminal of the output stage 130 for receiving the second inner signal 102 . Second ends (for example, sources) of the transistors M 11 and M 12 are connected to the second reference voltage (for example, the ground voltage).

The gain circuit 130 - 2 of the output stage 130 includes a first switch SWp, a thirteenth transistor M 13 , a fourteenth transistor M 14 , a fifteenth transistor M 15 and a sixteenth transistor M 16 . In the present exemplary embodiment, the thirteenth transistor M 13 and the fourteenth transistor M 14 are PMOS transistors, and the fifteenth transistor M 15 and the sixteenth transistor M 16 are NMOS transistors. A first end (for example, a drain) of the thirteenth transistor M 13 is connected to the first output terminal of the output stage 130 . A first end (for example, a drain) of the fourteenth transistor M 14 is connected to the second output terminal of the output stage 130 . Second ends (for example, sources) of the transistors M 13 and M 14 are connected to the first reference voltage (for example, the power voltage VDD).

A first end (for example, a drain) of the fifteenth transistor M 15 is connected to the first end of the thirteenth transistor M 13 , and a control end (for example, a gate) of the fifteenth transistor M 15 is connected to the first input terminal of the output stage 130 for receiving the first inner signal 101 . A first end (for example, a drain) of the sixteenth transistor M 16 is connected to the first end of the fourteenth transistor M 14 , and a control end (for example, a gate) of the sixteenth transistor M 16 is connected to the second input terminal of the output stage 130 for receiving the second inner signal 102 . Second ends (for example, sources) of the transistors M 15 and M 16 are connected to the second reference voltage (for example, the ground voltage).

The first bias VB or the first reference voltage (for example, the power voltage VDD) can be selected and transmitted to the control ends (the gates) of the thirteenth transistor M 13 and the fourteenth transistor M 14 through the first switch SWp. When the first bias VB is selected and transmitted to the control ends of the transistors M 13 and M 14 through the first switch SWp, a circuit structure of the gain circuit 130 - 2 is similar to that of the gain circuit 130 - 1 . The transistors M 2 , M 2 b , M 11 , M 12 , M 15 and M 16 form the current mirror structure 210 . The transistors M 2 , M 11 and M 16 form a current mirror, wherein channel aspect ratios (or channel width/length ratios W/L) of the transistors M 2 , M 11 and M 15 are 1:M:N. According to the first inner signal 101 , the gain circuits 130 - 1 and the 130 - 2 can respectively mirror the inner current I inner+ to internals of the gain circuits 130 - 1 and 130 - 2 by multiplication factors of M and N. The transistors M 2 b , M 12 and M 16 form another current mirror, wherein channel aspect ratios (or channel width/length ratios W/L) of the transistors M 2 b , M 12 and M 16 are 1:M:N. According to the second inner signal 102 , the gain circuits 130 - 1 and the 130 - 2 can respectively mirror the inner current I inner− to internals of the gain circuits 130 - 1 and 130 - 2 by multiplication factors of M and N. By determining the proportional relation of 1:M:N, current gains of the gain circuits 130 - 1 and 130 - 2 can be set. Now, the gain circuits 130 - 1 and 130 - 2 commonly provide the first output current I out+ and the second output current I out− .

When the power voltage VDD is selected and transmitted to the control ends of the transistors M 13 and M 14 through the first switch SWp, the transistors M 13 and M 14 are turned off, which is equivalent to a situation that the gain circuit 130 - 2 is disabled. Now, the first output current I out+ and the second output current I out− are provided by the gain circuit 130 - 1 alone. Therefore, by controlling the first switch SWp, the gain of the current-mode amplifier 100 can be changed, so as to achieve an effect of a variable gain amplifier (VGA).

The first bias VB is determined according to an actual design requirement. For example, the first bias VB can be a band-gap reference voltage or a common-mode feedback (CMFB) voltage. FIG. 3 is a circuit schematic diagram illustrating a common-mode feedback amplifier 300 according to an exemplary embodiment of the disclosure. The common-mode feedback amplifier 300 includes a PMOS transistor M 21 , a PMOS transistor M 22 , an NMOS transistor M 23 , an NMOS transistor M 24 , an NMOS transistor M 25 and a capacitor C 1 . Sources of the transistors M 21 and M 22 are connected to the power voltage VDD. Gates of the transistors M 21 and M 22 are connected to a drain of the transistor M 22 , a drain of the transistor M 24 and a first end of the capacitor C 1 . A drain of the transistor M 21 is connected to a drain of the transistor M 23 and a second end of the capacitor C 1 , and outputs the first bias VB to the output stage 130 . A drain of the transistor M 25 is connected to sources of the transistors M 23 and M 24 , and a source of the transistor M 25 is connected to the ground. Gates of the transistors M 23 and M 24 respectively receive a common-mode voltage and a feedback voltage of the system. A gate of the transistor M 25 is connected to a bias VB n3 . The bias VB n3 can be a band-gap reference voltage or other fixed voltages.

In the above exemplary embodiment, a broadband gain variable current-mode amplifier structure is introduced. Such structure can be widely applied to various wireless/cable broadband systems, and can be used to implement an analog baseband circuit in the broadband system for adjusting strength of a received signal.

FIG. 4 is a circuit schematic diagram illustrating a current-mode amplifier according to another exemplary embodiment of the disclosure. The current-mode amplifier 100 of FIG. 4 is similar to the current-mode amplifier 100 of FIG. 2 , and a difference there between is that the output stage 130 of FIG. 4 further includes a second switch SWn, a seventeenth transistor M 17 , an eighteenth transistor M 18 , a nineteenth transistor M 19 and a twentieth transistor M 20 . In the present exemplary embodiment, the transistors M 17 , M 18 , M 19 and M 20 are NMOS transistors.

The first end of the ninth transistor M 9 is connected to the first output terminal of the output stage 130 and a first end (for example, a drain) of the seventeenth transistor M 17 . The first end of the tenth transistor M 10 is connected to the second output terminal of the output stage 130 and a first end (for example, a drain) of the eighteenth transistor M 18 . A second end (for example, a source) of the seventeenth transistor M 17 is coupled to the first end of the eleventh transistor M 11 . A second end (for example, a source) of the eighteenth transistor M 18 is connected to the first end of the twelfth transistor M 12 . Control ends (for example, gates) of the transistors M 17 and M 18 receive the second bias VB n2 . The second bias VB n2 can be a band-gap reference voltage or other fixed voltages.

The first end of the thirteenth transistor M 13 is connected to the first output terminal of the output stage 130 and a first end (for example, a drain) of the nineteenth transistor M 19 . The first end of the fourteenth transistor M 14 is connected to the second output terminal of the output stage 130 and a first end (for example, a drain) of the twentieth transistor M 20 . A second end (for example, a source) of the nineteenth transistor M 19 is coupled to the first end of the fifteenth transistor M 15 . A second end (for example, a source) of the twentieth transistor M 20 is connected to the first end of the sixteenth transistor M 16 . The second bias VB n2 or the second reference voltage (for example, the ground voltage) is selected and transmitted to the control ends (the gates) of the transistors M 19 and M 20 through the second switch SWn.

When the first bias VB is selected and transmitted to the control ends of the transistors M 13 and M 14 through the first switch SWp, and the second bias VB n2 is selected and transmitted to the control ends (the gates) of the transistors M 19 and M 20 through the second switch SWn, the circuit structure of the gain circuit 130 - 2 is similar to that of the gain circuit 130 - 1 . Now, the gain circuits 130 - 1 and 130 - 2 commonly provide the first output current I out+ and the second output current I out− , namely, the current-mode amplifier 100 has a relatively great output gain.

When the power voltage VDD is selected and transmitted to the control ends of the transistors M 13 and M 14 through the first switch SWp, and the ground voltage is selected and transmitted to the control ends of the transistors M 19 and M 20 through the second switch SWn, the transistors M 13 , M 14 , M 19 and M 20 are turned off, so as to ensure that the disabled gain circuit 130 - 2 does not influence the output currents I out+ and I out− of the current-mode amplifier 100 . Now, the first output current I out+ and the second output current I out− are provided by the gain circuit 130 - 1 alone, namely, the current-mode amplifier 100 has a relatively small output gain.

In summary, based on a local feedback mode of the feedback circuit 110 , a low impedance input stage is implemented by the transistors M 1 , M 2 , M 1 b and M 2 b . The inner currents I inner+ and I inner− of the input stage 120 are respectively transmitted (mirrored) to a plurality of gain circuits of the output stage 130 by a predetermined multiplication factor by using the current structure 210 . By enabling/disabling the gain circuits, a tunable current gain stage of the output stage 130 is implemented. An input impedance Z in of the current-mode amplifier 100 of FIG. 4 in an s-domain can be represented as a following equation (1):

Wherein, g m1 , g m2 , g m3 and g m4 respectively represent conductances of the transistors M 1 , M 2 , M 3 and M 4 . C in represents a parasitic capacitance of the first input terminal of the input stage 120 . A parasitic capacitance C 1 =C gs4 +C ds4 +C ds3 , wherein C gs4 represents a parasitic capacitance from the gate to the source of the transistor M 4 , C ds4 represents a parasitic capacitance from the drain to the source of the transistor M 4 , and C ds3 represents a parasitic capacitance from the drain to the source of the transistor M 3 . A parasitic capacitance C 2 =C gs2 +C ds2 +C gs3 , wherein C gs2 represents a parasitic capacitance from the gate to the source of the transistor M 2 , C ds2 represents a parasitic capacitance from the drain to the source of the transistor M 2 , and C gs3 represents a parasitic capacitance from the gate to the source of the transistor M 3 . In case of a low frequency, the equation (1) can be simplified as:

Therefore, the input impedance can be reduced through the feedback circuit 110 , so as to achieve the purpose of broadband.

FIG. 5 is a diagram illustrating a simulation result of the input impedance of the feedback circuit 110 of FIG. 4 . According to FIG. 5 , it is known that an input bandwidth of the feedback circuit 110 may reach 1 GHz. FIG. 6 is a gain frequency response diagram of the current-mode amplifier 100 of FIG. 4 . A vertical axis of FIG. 6 represents gains, i.e. ratios of the output current I out and the input current I in . According to FIG. 6 , it is known that under different gain modulations, the current-mode amplifier 100 may still maintain the bandwidth of 1 GHz.

FIG. 7 is a circuit schematic diagram illustrating the current-mode amplifier 100 of FIG. 1 according to still another exemplary embodiment of the disclosure. The current-mode amplifier 100 of FIG. 7 is similar to the current-mode amplifier 100 of FIG. 2 , and a difference there between is that the transistors M 2 , M 2 b , M 3 , M 3 b , M 11 , M 12 , M 15 and M 16 of FIG. 7 are PMOS transistors, and the transistors M 1 , M 1 b , M 4 , M 4 b , M 9 , M 10 , M 13 and M 14 of FIG. 7 are NMOS transistors. In the present embodiment, the first reference voltage connected to the transistors M 1 , M 1 b , M 3 , M 4 b , M 9 , M 10 , M 13 , M 14 and the switch SWp is the ground voltage, and the second reference voltage connected to the transistors M 2 , M 2 b , M 3 , M 3 b , M 11 , M 12 , M 15 and M 16 is the power voltage VDD.

FIG. 8 is a circuit schematic diagram illustrating a common-mode feedback amplifier 800 according to another exemplary embodiment of the disclosure. The common-mode feedback amplifier 800 of FIG. 8 is similar to the common-mode feedback amplifier 300 of FIG. 3 , and a difference there between is that transistors M 23 , M 24 and M 25 of the common-mode feedback amplifier 800 are PMOS transistors, and transistors M 21 and M 22 of the common-mode feedback amplifier 800 are NMOS transistors. In the present exemplary embodiment, the first reference voltage connected to the transistors M 21 and M 22 is the ground voltage, and the second reference voltage connected to the transistor M 25 is the power voltage VDD. The common-mode feedback amplifier 800 may generate the first bias VB to the output stage 130 of FIG. 7 .

FIG. 9 is a circuit schematic diagram illustrating the current-mode amplifier 100 of FIG. 1 according to yet another exemplary embodiment of the disclosure. The current-mode amplifier 100 of FIG. 9 is similar to the current-mode amplifiers 100 of FIG. 4 and FIG. 7 .

In summary, the disclosure provides a variable gain amplifier, which can be applied to a UWB wireless transceiver system. Signals within a baseband range (0-250 MHz) are amplified according to a broadband property of the current-mode amplifier 100 , so as to overcome a limitation that a voltage-mode amplifier cannot be operated over 100 MHz. Moreover, a gain control of the current-mode amplifier 100 is achieved by controlling a current mirror, so that a problem of a gain error influenced by fabrication variation can be resolved. An applicable bandwidth of the current-mode amplifier 100 can be more than 1 GHz, which can be very competitive in a future ultra-wideband application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.