Temperature protection circuit

1. Technical Field

The present disclosure relates to protection circuits.

2. Description of Related Art

When a temperature of an electronic device exceeds a rated maximum, the device may be damaged or perform erratically. Therefore, there is room for improvement in the art.

Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block diagram of an exemplary embodiment of a temperature protection circuit connected between a power circuit and an operating circuit.

FIG. 2 is a circuit diagram of the temperature protection circuit of FIG. 1 .

The disclosure, including the drawings is illustrated by way of example and not by limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to FIG. 1 , an exemplary embodiment of a temperature protection circuit 100 is housed in an electronic device 200 . The temperature protection circuit 100 is connected between a power circuit 60 and an operating circuit 70 of the electronic device 200 , and prevents output voltage of the power circuit 60 from reaching the operating circuit 70 when the temperature of the electronic device 200 exceeds a rated maximum. The temperature protection circuit 100 includes a detection circuit 20 , a comparison circuit 30 , a switching circuit 40 , and a control circuit 50 .

The detection circuit 20 determines a temperature of the electronic device 200 and outputs a detected temperature signal to the comparison circuit 30 . The comparison circuit 30 receives the detected temperature signal and compares the received detected temperature signal with a reference temperature signal, and outputs a control signal to the switching circuit 40 , to open or close the switching circuit 40 . When the switching circuit 40 is open, the control circuit 50 receives a high level signal and directs the power circuit 60 to provide a voltage to the operating circuit 70 . When the switching circuit 40 is closed, the control circuit 50 receives a low level signal and directs the power circuit 60 to stop supplying voltage to the operating circuit 70 .

Referring to FIG. 2 , the detection circuit 20 includes first power source VCC 1 and second power source VCC 2 and resistors R 1 -R 4 . The first power source VCC 1 is grounded via the resistors R 1 and R 2 . The second power source VCC 2 is grounded via the resistors R 3 and R 4 . The comparison circuit 30 is connected to a node between the resistors R 1 and R 2 , and also to a node between the resistors R 3 and R 4 . In one embodiment, the resistor R 4 is a negative temperature coefficient thermal resistor. A node voltage between the resistors R 1 and R 2 is a reference voltage, corresponding to a preset temperature value for the electronic device 200 . The reference voltage can be regulated by varying/changing resistances of the resistors R 1 and R 2 .

The comparison circuit 30 includes a comparator U 1 and a third power source VCC 3 . A non-inverting input terminal of the comparator U 1 is connected to a node between the resistors R 1 and R 2 . An inverting input terminal of the comparator U 1 is connected to a node between the resistors R 3 and R 4 . A voltage terminal of the comparator U 1 is connected to the third power source VCC 3 . A ground terminal of the comparator U 1 is grounded. An output terminal of the comparator U 1 is connected to the switching circuit 40 .

The switching circuit 40 includes an electronic switch, such as a field effect transistor (FET) Q 1 and a resistor R 5 . A gate of the FET Q 1 is connected to the output terminal of the comparator U 1 via the resistor R 5 . A source of the FET Q 1 is grounded. A drain of the FET Q 1 is connected to the control circuit 50 . In one embodiment, the FET Q 1 is an n-channel FET.

The control circuit 50 includes a pulse generator U 2 , capacitors C 1 -C 9 , resistors R 6 -R 8 , diodes D 1 and D 2 , inductors L 1 and L 2 , and electronic switches, such as FETs Q 2 and Q 3 . An input pin COMEN of the pulse generator U 2 is connected to the drain of the FET Q 1 and also to a feedback pin FB of the pulse generator U 2 via the resistor R 8 and the capacitor C 2 . A voltage pin PGOOD of the pulse generator U 2 is connected to the power circuit 60 via the resistor R 6 . The voltage pin VCC is grounded via the capacitor C 1 and also to the power circuit 60 via the resistor R 7 . The power circuit 60 is connected to anodes of the diodes D 1 and D 2 . Cathodes of the diodes D 1 and D 2 are connected to an input/output (I/O) pin BOOT of the pulse generator U 2 . The I/O pin BOOT of the pulse generator U 2 is connected to an I/O pin PHASE of the pulse generator U 2 via the resistor R 14 and the capacitor C 5 . An I/O pin UGATE of the pulse generator U 2 is connected to a gate of the FET Q 2 via the resistor R 15 . A drain of the FET Q 2 is connected to the power circuit 60 via the inductor L 1 . The capacitor C 6 is connected between the drain of the FET Q 2 and ground. The capacitor C 7 is parallel to the capacitor C 6 . A source of the FET Q 2 is connected to a drain of the FET Q 3 . A gate of the FET Q 3 is connected to an I/O pin LGATE of the pulse generator U 2 . A source of the FET Q 3 is grounded. The drain of the FET Q 3 is connected to a first end of the inductor L 2 . A second end of the inductor L 2 is connected to the operating circuit 70 . The capacitor C 9 is connected between the second end of the inductor L 2 and ground. The resistor R 18 and the capacitor C 8 are connected between the drain of the FET Q 3 and ground. The I/O pin PHASE of the pulse generator U 2 is connected to a node between the source of the FET Q 2 and the drain of the FET Q 3 . The resistor R 16 is connected between the I/O pin PHASE of the pulse generator U 2 and the gate of the FET Q 2 . The resistor R 17 is connected between the gate of the FET Q 3 and ground. Ground pins GND and EPAD of the pulse generator U 2 are grounded. An I/O pin VOS of the pulse generator U 2 is grounded via the resistor R 10 . The second end of the inductor L 2 is connected to the I/O pin VOS of the pulse generator U 2 via the resistor R 11 . The input pin COMEN of the pulse generator U 2 is grounded via the capacitor C 3 and the resistor R 9 . The second terminal of the inductor L 2 is connected to a node between the capacitor C 3 and the resistor R 9 via the resistor R 12 . The resistor R 13 is connected to the capacitor C 4 in series, and then connected to the resistor R 12 in parallel. In one embodiment, the FETs Q 2 and Q 3 are n-channel FETs.

In use, when the temperature of the electronic device 200 is below the preset temperature value, the resistance of the resistor R 4 exceeds the normal resistance of the resistor R 4 . A voltage of the inverting input terminal of the comparator U 1 exceeds the reference voltage of the non-inverting input terminal of the comparator U 1 . The output terminal of the comparator U 1 outputs a low level signal to the FET Q 1 . The FET Q 1 is turned off. The input pin COMEN of the pulse generator U 2 receives a high level signal to initialize the pulse generator U 2 to operate normally. The pulse generator U 2 alternately outputs a high level signal and a low level signal. When the I/O pin UGATE of the pulse generator U 2 outputs a high level signal and the I/O pin LGATE of the pulse generator U 2 outputs a low level signal, the FET Q 2 is turned on and the FET Q 3 is turned off. The power circuit 60 provides a voltage to the operating circuit 70 via the FET Q 2 . At the same time, the inductor L 2 stores charges. When the I/O pin UGATE of the pulse generator U 2 outputs a low level signal and the I/O pin LGATE of the pulse generator U 2 outputs a high level signal, the FET Q 2 is turned off and the FET Q 3 is turned on. The inductor L 2 powers the operating circuit 70 . Thus, the electronic device 200 operates normally.

When the temperature of the electronic device 200 exceeds the preset temperature value, the resistance of the resistor R 4 is below the normal resistance of the resistor R 4 . A voltage of the inverting input terminal of the comparator U 1 is below the reference voltage of the non-inverting input terminal of the comparator U 1 . The output terminal of the comparator U 1 outputs a high level signal to the FET Q 1 . The FET Q 1 is turned on. The input pin COMEN of the pulse generator U 2 receives a low level signal from the drain of the FET Q 1 , and the pulse generator U 2 stops. The FET Q 2 and Q 3 receive low level signals and are turned off. The power circuit 60 does provide no voltage to the operating circuit 70 .

Accordingly, the temperature protection circuit 100 protects the electronic device 200 from damage when the temperature thereof exceeds a preset temperature value.

The temperature protection circuit 100 detects the temperature of the electronic device 200 and outputs a control signal to prevent the output voltage of the power circuit 60 from reaching the operating circuit 70 of the electronic device 200 when the temperature of the electronic device 200 exceeds the preset temperature value.

It is to be understood, however, that even though numerous characteristics and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.