Semiconductor integrated circuit

The present application claims priority of Korean Patent Application No. 10-2010-0049585, filed on May 27, 2010, which is incorporated herein by reference in its entirety.

Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit.

In general, packaging technology for semiconductor integrated circuits has been continuously developed to satisfy demands for miniaturization and mounting reliability. As demand increases for high-performing, miniature electronic products, a variety of technologies for a stack package are being developed.

In the semiconductor industry, “stack” means vertically stacking two or more semiconductor chips or packages. When a stack package is applied to a semiconductor memory device, a product having a memory capacity two or more times larger than a memory capacity which can be fabricated by a semiconductor integration process may be realized. Furthermore, the stack package not only increases the memory capacity, but also offers advantages in terms of packaging density and the efficient use of the mounting area.

The stack package may be fabricated by the following methods. First, individual semiconductor chips may be stacked, and then packaged at once. Second, packaged individual semiconductor chips may be stacked. The individual semiconductor chips of the stacked semiconductor package may be coupled through metallic wires or through silicon vias (TSV). The stack package using TSVs may have such a structure that the physical and electrical coupling between semiconductor chips is vertically achieved by TSVs formed in the respective semiconductor chips.

FIG. 1 is a perspective view illustrating the configuration of a stack package semiconductor integrated circuit.

Referring to FIG. 1 , the semiconductor integrated circuit 100 includes first to third semiconductor chips 110 to 130 , which are vertically stacked, and a plurality of TSVs 140 to 160 , which are formed through the first to third semiconductor chips 110 to 130 and configured to transmit signals and power among the first to third semiconductor chips 110 to 130 .

The first to third semiconductor chips 110 to 130 may be categorized as a master chip and slave chips, depending on their functions. For example, the third semiconductor chip 130 may serve as the master chip, and the first and second semiconductor chips 110 and 120 may serve as the slave chips. In this case, the third semiconductor chip 130 may receive signals and power from outside, transfer the signals and power to the first and second semiconductor chips 110 and 120 , and control the first and second semiconductor chips 110 and 120 .

The plurality of TSVs 140 to 160 configured to transmit signals and powers may be formed of a metal, for example, Cu. Each of the semiconductor chips 110 to 130 may include several hundred to several thousand TSVs formed therethrough.

Exemplary embodiments of the present invention are directed to a semiconductor integrated circuit having a power coupling structure, which is capable of reducing a voltage drop.

In accordance with an exemplary embodiment of the present invention, a semiconductor integrated circuit includes a plurality of first power supply through-chip vias formed through a semiconductor chip to be in a line in a first direction of the semiconductor chip, a plurality of second power supply through-chip vias formed through the semiconductor chip to be in a line in the first direction, a plurality of first power lines arranged in a second direction, wherein each of the plurality of first power lines is coupled to each of the first power supply through-chip vias, and a plurality of second power lines arranged in the second direction, wherein each of the plurality of second power lines is coupled to each of the second power supply through-chip vias.

In accordance with another embodiment of the present invention, a semiconductor integrated circuit includes a plurality of first and second power supply through-chip vias formed through a semiconductor chip and alternately arranged in a first area of the semiconductor chip to be in a line in a first direction, another plurality of first and second power supply through-chip vias alternately arranged in a second area of the semiconductor chip to be in a line in the first direction and having an arrangement sequence which is opposite to the arrangement sequence of the first and second power supply through-chip vias arranged in the first area, a plurality of first power lines arranged in a second direction, wherein each of the plurality of first power lines is coupled to each of the first power supply through-chip vias, and a plurality of second power lines arranged in the second direction, wherein each of the plurality of second power lines is coupled to each the second power supply through-chip vias.

FIG. 1 is a perspective view illustrating the configuration of a conventional semiconductor integrated circuit having a stack package structure.

FIG. 2 is a plan view of the semiconductor integrated circuit in accordance with an embodiment of the present invention.

FIG. 3 is a diagram illustrating a portion Q of FIG. 2 .

FIG. 4 is a plan view of a semiconductor integrated circuit in accordance with another exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating a portion Q′ of FIG. 4 .

FIG. 6 is a plan view of a semiconductor integrated circuit in accordance with yet another exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a portion Q″ of FIG. 6 .

Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

For convenience of description, one semiconductor chip including a plurality of TSVs formed therethrough will be taken as an example in a semiconductor integrated circuit in accordance with exemplary embodiments of the present invention. However, the semiconductor integrated circuit may include a plurality of stacked semiconductor chips as illustrated in FIG. 1 .

FIG. 2 is a plan view of the semiconductor integrated circuit in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 2 , the plurality of TSVs 145 which vertically pass through the semiconductor chip 147 are arranged in a lattice shape in the semiconductor chip 147 . That is, the TSVs 145 passing through the semiconductor chip 147 may be arranged at even intervals in columns and rows.

Meanwhile, the plurality of TSVs may be divided into signal TSVs 142 for transferring signals and power supply TSVs 144 for supplying power. Here, for example, less power supply TSVs 144 may be formed than the number of signal TSVs 142 . Further, the power supply TSVs 144 may be uniformly arranged in order to stably supply power to the semiconductor chip 147 . In other words, a plurality of first areas A may include the signal TSVs 142 arranged in one or more lines, while a plurality of second areas B may include the power supply TSVs 144 arranged in two lines. Moreover, as shown in FIG. 2 , the first areas A and the second areas B may be alternately formed.

FIG. 3 illustrates a portion Q of FIG. 2 , in order to describe the semiconductor integrated circuit of FIG. 2 in more detail.

Referring to FIG. 3 , the semiconductor integrated circuit includes the first and second areas A and B which are alternately formed as described above. In particular, the second area B may be divided into a third area B 1 and a fourth area B 2 . The third area B 1 includes power supply voltage (VDD) TSVs 146 A to 146 E arranged in one line, and the fourth area B 2 includes ground voltage (VSS) TSVs 148 A to 148 E arranged in another line. In other words, the power supply TSVs 144 are divided into the power supply voltage TSVs 146 A to 146 E and the ground voltage TSVs 148 A to 148 E.

Furthermore, the semiconductor integrated circuit includes plural pairs of first power lines 170 A and 170 B and plural pairs of second power lines 180 A and 180 B which are alternately arranged with the signal TSVs 142 A to 142 E, the power supply voltage TSVs 146 A to 146 E, and the ground voltage TSVs 148 A to 148 E, which are adjacent to each other in a direction. For example, the pair of first power lines 170 A and 170 B are arranged in such a manner that the signal TSVs 142 A, 142 C, or 142 E, the power supply voltage TSV 146 A, 146 C, or 146 E, and the ground voltage 148 A, 148 C, or 148 E, which are arranged adjacent to each other in an odd number line in the row direction, are interposed between the pair of first power lines 170 A and 170 B. Furthermore, the pair of second power lines 180 A and 180 B are arranged in such a manner that the signal TSVs 142 B or 142 D, the power supply voltage TSV 146 B or 146 D, and the ground voltage TSV 148 B or 148 D, which are arranged adjacent to each other in an even number line in the row direction, are interposed between the pair of second power lines 180 A and 180 B. Here, the first power lines 170 A and 170 B for the power supply voltage VDD are coupled to the power supply voltage TSVs 146 A, 146 C, and 146 E. The second power lines 180 A and 180 B for the ground voltage VSS are coupled to the ground voltage TSVs 148 B and 148 D. Meanwhile, although not illustrated in detail, the TSVs 146 B, 146 D, 148 A, 148 C, and 148 E, which are not coupled to the first power lines 170 A and 170 B and the second power lines 180 A and 180 B, may be coupled to a lower metal layer, when it is assumed that the layer illustrated in FIG. 3 is an upper metal layer. The lower metal layer may be separated from the upper metal layer by an interlayer dielectric layer.

Meanwhile, the semiconductor integrated circuit includes a plurality of signal lines 190 coupled to the signal TSVs 142 A to 142 E.

Referring to FIG. 3 , both the first power lines 170 A and 170 B and the second power lines 180 A and 180 B are arranged in uneven intervals. For example, the first power lines 170 A and 1708 are arranged in such a manner that a distance D 1 between an arbitrary pair of first power lines 170 A and 170 B is set to be different from a distance D 2 between an adjacent pair of first power lines 170 B and 170 A (D 1 ≠D 2 ). Also, the second power lines 180 A and 180 B are arranged in the same manner. If the first power lines 170 A and 1708 and the second power lines 180 A and 1808 are arranged in uneven intervals, a voltage drop may occur, and thus, the power supply may be unstable.

Furthermore, among the power supply TSVs 144 , the power supply voltage TSVs 146 B and 146 D and the ground voltage TSVs 148 A, 148 C, and 148 E are not coupled to the first power lines 170 A and 170 B or the second power lines 180 A and 180 B. Accordingly, there may be a limit to which the power supply TSVs 144 can stably supplying power to the power lines 170 A and 170 B and the second power lines 180 A and 180 B.

FIG. 4 is a plan view of a semiconductor integrated circuit in accordance with another exemplary embodiment of the present invention.

Referring to FIG. 4 , the semiconductor integrated circuit 200 includes a semiconductor chip 210 and a plurality of TSVs 240 passing through the semiconductor chip 210 .

The semiconductor chip 210 refers to a typical silicon substrate including a variety of devices, for example, a MOS transistor and so on.

The plurality of TSVs 240 may transmit data signals or power supply signals between the stacked semiconductor chips which are not illustrated. Therefore, the plurality of TSVs 240 may be formed of a metal, for example, Cu. Each of the semiconductor chips may include several hundred to several thousand TSVs formed through the semiconductor chip. The plurality of TSVs 240 may be divided into signal TSVs 242 for transferring data signals and power supply TSVs 244 for supplying power. Here, for example, the number of power supply TSVs 244 may be set to be smaller than the number of signal TSVs 242 . Further, the power supply TSVs 244 may be uniformly arranged throughout the entire semiconductor chip 210 , in order to stably supply power to the entire region of the semiconductor chip 210 . For example, a plurality of first areas A′ each may include the signal TSVs 242 arranged in one or more lines, while a plurality of second areas B′ may each include the power supply TSVs 244 arranged in two lines. Moreover, as shown in FIG. 4 , the first areas A′ and the second areas B′ may be alternately formed.

FIG. 5 illustrates a portion Q′ of FIG. 4 , in order to describe the semiconductor integrated circuit 200 of FIG. 4 in more detail.

Referring to FIG. 5 , the first area A′ includes a plurality of signal TSVs 242 A to 242 E arranged to form one or more lines.

The second area B′ includes a plurality of power supply voltage (VDD) TSVs 246 A to 246 E arranged to be in a line in the column direction and a plurality of ground voltage (VSS) TSVs 248 A to 248 E arranged to be in a line parallel to the power supply voltage TSVs 246 A to 246 E. In other words, the second area B′ may be divided into an area 13 ′ 1 and an area B′ 2 . Here, for example, the plurality of power supply voltage TSVs 246 A to 246 E are arranged in the area B′ 1 , and the plurality of ground voltage TSVs 248 A to 248 E are arranged in the area B′ 2 . In other words, the power supply TSVs 244 may be divided into the plurality of power supply voltage TSVs 246 A to 246 E and the plurality of ground voltage TSVs 248 A to 248 E.

Meanwhile, the semiconductor integrated circuit 200 includes a plurality of first power lines 270 A to 270 E disposed in parallel to each other at one side of the signal TSVs 242 A to 242 E, the power supply voltage TSVs 246 A to 246 E, and the ground voltage TSVs 248 A to 248 E. More specifically, the first power lines 270 A to 270 E are parallel to each other in the row direction of the semiconductor chip 210 . For example, the first power line 270 A is disposed along one side of the signals TSV 242 A, the power supply voltage TSV 246 A, and the ground voltage TSV 248 A, which are adjacent to each other in the row direction. The other first power lines 270 B to 270 E are disposed in a similar manner. The plurality of power lines 270 A to 270 E for power supply voltage VDD are electrically coupled to the power supply voltage TSVs 246 A to 246 E, respectively. Furthermore, the first power lines 270 A to 270 E are arranged at the same distance D 3 from each other, and thus, have a uniform arrangement structure.

The semiconductor integrated circuit 200 includes a plurality of second power lines 280 A to 280 E disposed in parallel to each other at the other side of the signal TSVs 242 A to 242 E, the power supply voltage TSVs 246 A to 246 E, and the ground voltage TSVs 248 A to 248 E. More specifically, the second power lines 280 A to 280 E are parallel to each other in the row direction of the semiconductor chips 210 . For example, the second power line 280 A is disposed along the other side, from the first power line 270 A, of the signals TSV 242 A, the power supply voltage TSV 246 A, and the ground voltage TSV 248 A, which are arranged adjacent to each other in the row direction. The other second power lines 280 B to 280 E are disposed in a similar manner. The plurality of second power lines 280 A to 280 E for ground voltage VDD are electrically coupled to the ground voltage TSVs 248 A to 248 E, respectively. Furthermore, the second power lines 280 A to 280 E are arranged at the same distance D 3 from each other, and thus, have a uniform arrangement structure.

In other words, the first power lines 270 A to 270 E and the second power lines 280 A to 280 E, respectively, are disposed to form a pair of power lines for supplying power to the signal TSVs, the power supply voltage TSV, and the ground voltage TSV, which are arranged adjacent to each other in the row direction. Therefore, signal TSVs, power supply voltage TSVs, and ground voltage TSVs are interposed between the first power lines 270 A to 270 E and the second power lines 280 A to 280 E, respectively. For example, the first power line 270 A and the second power line 280 A form a pair of power lines for supplying power to the signal TSVs 242 A, the power supply voltage TSV 246 A, and the ground voltage TSV 248 A interposed between the first power line 270 A and the second power line 280 A. Therefore, the power supply voltage TSVs 246 A to 246 E and the ground voltage TSVs 248 A to 248 E, which are arranged to be in a line in the column direction, may be coupled to the corresponding first power lines 270 A to 270 E and the corresponding second power lines 280 A to 280 E, respectively.

In accordance with this exemplary embodiment of the present invention, the first power lines 270 A to 270 E are arranged at the substantially same distance D 3 from each other. Likewise, the second power lines 280 A to 280 E are arranged at the substantially same distance D 3 from each other. Further, the power supply voltage TSVs 246 A to 246 E and the ground voltage TSVs 248 A to 248 E are coupled to the corresponding first power lines 270 A to 270 E and the corresponding second power lines 280 A to 280 E. Therefore, the entire power supply of the semiconductor chip 210 may be stabilized.

FIG. 6 is a plan view of a semiconductor integrated circuit in accordance with yet another exemplary embodiment of the present invention.

Referring to FIG. 6 , the semiconductor integrated circuit 300 includes a semiconductor chip 310 and a plurality of TSVs 340 passing through the semiconductor chip 310 .

The semiconductor chip 310 refers to a typical silicon substrate including a variety of devices, for example, a MOS transistor and so on.

The plurality of TSVs 340 are configured to transmit signals or power between stacked semiconductor chips which are not illustrated. Therefore, the plurality of TSVs 340 may be formed of a metal, for example, Cu. Each of the semiconductor chips may include several hundred to several thousand TSVs formed therethrough. The plurality of TSVs 340 may be divided into signal TSVs 342 for transferring signals and power supply TSVs 344 for supplying power. Here, for example, the number of power supply TSVs 344 may be set to be smaller than the number of signal TSVs 342 . Further, the power supply TSVs 344 may be uniformly arranged throughout the entire semiconductor chip 310 , in order to stably supply power to the entire region of the semiconductor chip 310 . For example, a plurality of first areas A″ each may include the signal TSVs 342 arranged in one or more lines, while a plurality of second areas B″ may each include the power supply TSVs 344 arranged in one line. Moreover, as shown in FIG. 6 , the first areas A″ and the second areas B″ may be alternately formed.

FIG. 7 illustrates a portion Q″ of FIG. 6 , in order to describe the semiconductor integrated circuit 300 of FIG. 6 in more detail.

Referring to FIG. 7 , the first area A″ includes a plurality of signal TSVs 342 A to 342 E arranged to be in multiple lines in a column direction.

The second area B″ includes a plurality of power supply TSVs 344 arranged to be in a line in the column direction. Here, the power supply TSVs 344 may include power supply voltage (VDD) TSVs 344 A and ground voltage (VSS) TSVs 344 B. The power supply voltage TSVs 344 A and the ground voltage TSVs 344 B are alternately arranged in the second area B″. In this case, the arrangement sequence of the power supply voltage TSVs 344 A and the ground voltage TSVs 344 B which are arranged in an arbitrary second area B″ may be opposite to the arrangement sequence of the power supply voltage TSVs 344 A and the ground voltage TSVs 344 B which are arranged in another arbitrary second area B″ adjacent to the arbitrary second area B″. For example, the arrangement sequence of the arbitrary second area B″ positioned in the right side of FIG. 7 may be set in such a manner that the power supply voltage TSVs 334 A and the ground voltage TSVs 344 B are alternately arranged in a state in which one of power supply voltage TSVs 344 A is positioned in a first row. In this case, the arrangement sequence of the second area B″ adjacent to the arbitrary second area B″ (e.g., adjacent arbitrary second area B″ positioned in the left side of the FIG. 7 ) may be set in such a manner that the ground voltage TSVs 344 B and the power supply voltage TSVs 344 A are alternately arranged in a state in which one of ground voltage TSVs 344 B is positioned in the first row. In such an arrangement, a parasitic capacitor is formed between the power supply voltage TSV 344 A and the ground voltage TSV 344 B which are arranged adjacent to each other in the column direction. In this case, although noise is introduced into the power supply voltage TSVs 344 A and the ground voltage TSVs 344 B, the parasitic capacitor formed in such a manner has a strong characteristic against the noise. The parasitic capacitor may play the same role as a reservoir capacitor.

Meanwhile, the semiconductor integrated circuit 300 includes a plurality of power lines 370 A to 370 E disposed in parallel to each other at one side of the power supply voltage TSVs 344 A and the ground voltage TSVs 344 B which are arranged in a line in the row direction of the semiconductor chip 310 . For example, the first power line 370 A is disposed in parallel to one side of the ground voltage TSV 344 B and the power supply voltage TSV 344 A which are arranged in the line in the row direction. The first power lines 370 A to 370 E for power supply voltage VDD are electrically coupled to the respective power supply voltage TSVs 344 A arranged in the second area B″. Furthermore, the first power lines 370 A to 370 E are arranged at the substantially same distance D 4 from each other, and thus, have a uniform arrangement structure.

Furthermore, the semiconductor integrated circuit 300 includes a plurality of second power lines 380 A to 380 E disposed in parallel to each other at the other side of the power supply voltage TSVs 344 A and the ground voltage TSV 344 B which are arranged adjacent to each other in the row direction of the semiconductor chip 310 . For example, the second power line 380 A is disposed along the other side, from the first power line 370 A, of the ground voltage TSV 344 B and the power supply voltage TSV 344 A which are arranged adjacent to each other in the row direction. The second power lines 380 A to 380 E for ground voltage VSS are electrically coupled to the respective ground voltage TSV 344 B arranged in the second area B″. Furthermore, the second power lines 380 A to 380 E are arranged at the substantially same distance D 4 from each other as in the first power lines 370 A to 370 E, and thus, have a uniform arrangement structure.

In other words, the first power lines 370 A to 370 E and the second power lines 380 A to 380 E, respectively, are arranged to form a pair of power lines for supplying power to the ground voltages TSV 344 B and the power supply voltages TSV 344 A, which are arranged adjacent to each other in the row direction, and interposed between the first power lines 370 A to 370 E and the second power lines 380 A to 380 E, respectively. For example, the first power line 370 A and the second power line 380 A are arranged to form a pair of power lines for supplying power to the ground voltage TSV 344 B and the power supply voltage TSV 344 A interposed between the first power line 370 A and the second power line 380 A. Therefore, the power supply voltage TSVs 344 A and the ground voltage TSVs 344 B which are alternately arranged in the column direction may be coupled to the corresponding first power lines 370 A to 370 E and the corresponding second power lines 380 A to 380 E, respectively.

In accordance with this exemplary embodiment of the present invention, since the first power lines 370 A to 370 E and the second power lines 380 A to 380 E are arranged at the same distance D 4 from each other, the entire power supply of the semiconductor chip 210 may be stabilized, and may have a strong characteristic against noise, due to the parasitic capacitor.

In accordance with the exemplary embodiments of the present invention, the first and second power lines, respectively, are arranged at the same distance from each other to substantially prevent a voltage drop. Therefore, the power supply may be stabilized.

Furthermore, since the plurality of power supply TSVs are all coupled to the corresponding power lines, the power supply may be stabilized and a power distribution may be effective.

Furthermore, since corresponding power lines are arranged at the same distance from each other, the number of power supply TSVs may be reduced and therefore, chip area may be more effectively utilized.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.