Scanning circuit and scanning method for keyboard

1. Technical Field

The present disclosure relates to device scanning and, particularly, to a scanning circuit and a scanning method thereof for a keyboard.

2. Description of Related Art

Referring to FIG. 1 , a frequently used scanning circuit 100 used in a keyboard (not shown) usually includes sixteen keys. The scanning circuit 100 includes four rows R 1 ˜R 4 and four columns C 1 ˜C 4 , constituting a switch matrix (not labeled) including sixteen intersections. Sixteen switches C 1 R 1 ˜C 4 R 4 are set at the intersections respectively, with two contacts of each switch electrically connected to a corresponding row and a corresponding column respectively, for example one contact of a switch C 1 R 1 is electrically connected to a row R 1 and the other contact of the switch C 1 R 1 is electrically connected to a column C 1 . Each of the sixteen switches is normally open until a key is pressed, and then a corresponding switch, for example, C 1 R 1 , closes, and the row R 1 and the column C 1 are electrically connected. When the key is released, the corresponding switch opens. Furthermore, four input ports P 1 ˜P 4 are electrically connected to ends of the columns C 1 ˜C 4 respectively, and four output ports P 5 ˜P 8 are electrically connected to the rows R 1 ˜R 4 respectively. A power source is electrically connected to the other end of each column via a resistor.

During scanning, voltage of each input port P 1 ˜P 4 is sequentially set to low. When the voltage of one of the input ports P 1 ˜P 4 is set to low, the voltages of the remaining input ports P 1 ˜P 4 are set to high. The output ports are checked to determine whether any switches are closed, and thereby pressed keys corresponding to the switches can be identified.

As an example, if the voltage of the input port P 1 electrically connected to the column C 1 is set to be low, the voltage of the output port P 5 electrically connected to the row R 1 is also low, then the switch C 1 R 1 is determined to be closed. Consequently, a pressed key corresponding to the switch C 1 R 1 can be determined.

In practice, the input ports and the output ports are generally provided by a single-chip microprocessor. However, providing a microprocessor with so many ports is a waste.

Therefore, it is desirable to provide a scanning circuit and a scanning method capable of using fewer ports, which can overcome the limitations described.

The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure.

FIG. 1 is a schematic diagram showing a conventional scanning circuit.

FIG. 2 is a schematic diagram of a keyboard in accordance with an exemplary embodiment.

FIG. 3 is a schematic diagram of a scanning circuit in the keyboard of FIG. 2 .

FIG. 4 is an example of the scanning circuit in FIG. 3 with four rows and four columns.

FIG. 5 is a flowchart of a scanning method implemented by the scanning circuit in FIG. 3 in accordance with an exemplary embodiment.

Referring to FIG. 2 , a keyboard 10 in accordance with an exemplary embodiment is illustrated. The keyboard 10 includes a processing unit 100 , a scanning circuit 200 , and a scanning application 300 . The processing unit 100 includes n I/O ports 110 . The n I/O ports 110 are configured to electrically connect the scanning circuit 200 to the processing unit 100 . The scanning application 300 , pre-stored in a memory (not shown) of the keyboard 10 is implemented by the processing unit 100 to determine which key (not shown) in the keyboard 10 is pressed.

The processing unit 100 may be a single-chip microprocessor, which further includes a power pin 101 electrically connected to a power supply VCC, and a ground pin 102 electrically connected to ground. The I/O ports 110 can be set to input ports and output ports. When one of the I/O ports 110 is set to input port, the voltage thereof is determined by a connected external input source. That is, if the voltage of the external input source is low, the voltage of the one I/O port 110 is low. If the voltage of the external input source is high, the voltage of the one I/O port 110 is high. When one of the I/O ports 110 is used as output port, the voltage of the one I/O port 110 is determined by the processing unit 100 .

FIG. 3 is a schematic diagram of the scanning circuit 200 in the keyboard 10 of FIG. 2 . The scanning circuit 200 includes n rows L 1 ˜Ln and n columns P 1 - 1 ˜P 1 - n . In the embodiment, n is a natural number not less than two. The n rows L 1 ˜Ln and n columns P 1 - 1 ˜P 1 - n cooperatively form a switch matrix 200 a including n*n switches S 1 - 1 ˜Sn-n. An end of each of the switches in the same row is electrically connected to one of the n I/O ports K 1 ˜Kn, respectively. Another end of each of the switches in the same column is electrically connected to ground via one resistor R 1 - 1 ˜R 1 - n , respectively. The resistances of the resistors R 1 - 1 ˜R 1 - n are similar to each other or the same, and quite low.

The scanning circuit 200 further includes n columns P 2 - 1 ˜P 2 - n . Each of the columns P 2 - 1 ˜P 2 - n intersects one of the rows L 1 ˜Ln and one of the columns P 1 - 1 ˜P 1 - n . Each of the columns P 2 - 1 ˜P 2 - n includes one resistor R 2 - 1 ˜R 2 - n , respectively. One end of each one of the resistors R 2 - 1 ˜R 2 - n is electrically connected to one of the I/O ports K 1 ˜Kn, and another end of the resistors R 2 - 1 ˜R 2 - n is electrically connected to ground via one of the resistors R 1 - 1 ˜R 1 - n . For example, one end of the resistor R 2 - 2 is electrically connected to the I/O port K 2 and the other end is electrically connected to ground via the resistor R 1 - 2 . The resistance of the resistors R 2 - 1 ˜R 2 - n are similar to each other or the same. The resistance of the resistors R 2 - 1 ˜R 2 - n exceeds those of resistors R 1 - 1 ˜R 1 - n.

In use, the processing unit 100 sets all the I/O ports K 1 ˜Kn to input ports. The states of the I/O ports K 1 ˜Kn are detected. If one of the keys is pressed, the voltage of the I/O port connected to the switch corresponding to the pressed key is changed to low. In the embodiment, each of the I/O ports K 1 ˜Kn is connected to the ends of at least two switches in the same row. Therefore, the processing unit 100 can only determine that one of the switches in the row corresponding to the I/O port the voltage of which has been changed to low is pressed, but cannot determine which it is.

In order to determine which of the switches in the row is pressed, the processing unit 100 then sets all the I/O ports K 1 ˜Kn to output ports. The voltage of the I/O port the voltage of which has been changed to low is set to high, and the voltages of the other I/O ports are set to low. In the embodiment, when the voltage of the I/O port the voltage of which has been changed to low is set to high, the voltage of one of the resistors R 2 - 1 ˜R 2 - n electrically connected to the pressed switch is accordingly changed to high. Therefore, the voltage of the I/O port electrically connected to the one of the resistors R 2 - 1 ˜R 2 - n is changed to high. The processing unit 100 resets all the I/O ports K 1 ˜Kn to input ports. The processing unit 100 then re-checks the states of the I/O ports K 1 ˜Kn. The processing unit 100 determines that the switch, with one end in the row electrically connected to the one I/O port the voltage of which is set to high and another end in the column electrically connected to the one I/O port via one of the n resistors R 2 - 1 ˜R 2 - n the voltage of which is changed to high or remains high if voltages of the I/O ports are not changed, is pressed. In the embodiment, the scanning circuit 200 employs n I/O ports K 1 ˜Kn to determine which of the n*n switches is pressed. Compared to a scanning circuit employing n input ports and n output ports, n ports are conserved.

In a preferred embodiment, while determining which switch is pressed, the processing unit 100 first records a first key value if the voltage of one of the I/O ports K 1 ˜Kn is changed to low when all the I/O ports K 1 ˜Kn are set to input ports. The first key value consists of n numbers. In the embodiment, the numbers are 0 and 1. The number 0 indicates the voltage of one of the I/O ports is changed to low, and the number 1 indicates the voltage of one of the I/O ports is changed to high. For the first key value, the order of the n numbers are arranged according to an order of the n I/O ports K 1 ˜Kn. In the embodiment, for the first key value, the number corresponding to the I/O port K 1 is in the first position from left to right. Accordingly, the number corresponding to the I/O port Kn is in the n position from left to right. In an alternative embodiment, the number corresponding to the I/O port Kn can be placed in the first position from left to right, and the number corresponding to the I/O port K 1 can be placed in the n position from left to right.

The processing unit 100 records a second key value after all the I/O ports K 1 ˜Kn are reset to input ports. The second key value consists of n numbers. In the embodiment, the numbers are 0 and 1. The number 0 indicates the voltage of one of the I/O ports is low, and the number 1 indicates the voltage of one of the I/O ports is high. For the second key value, the order of the n numbers are arranged according to an order of the n I/O ports K 1 ˜Kn. In the embodiment, for the second key value, the number corresponding to the I/O port K 1 is in the first position from left to right. Accordingly, the number corresponding to the I/O port Kn is in the n position from left to right. In an alternative embodiment, the number corresponding to the I/O port Kn can be in the first position from left to right, and the number corresponding to the I/O port K 1 can be in the n position from left to right.

The processing unit 100 records a third key value according to the first key value and the second key value. The third key value consists of 2n numbers. In the embodiment, the first n numbers from left to right are the same as the first key value and the remaining numbers from left to right are the same as the second key value. In an alternative embodiment, the first n numbers from left to right can be the same as the second key value and the remaining numbers from left to right can be the same as the first key value.

In the embodiment, a key table is also pre-stored in the memory of the keyboard 10 which records relationships between third key values and the switches. In the key table, each switch corresponds to one third key value. The processing unit 100 consults the key table to determine which switch is pressed according to the determined third key value. For example, when n is equal to 4, the table appears as follows. For the first key value, the number corresponding to the I/O port K 1 is in the first position from left to right. For the second key value, the number corresponding to the I/O port K 1 is in the first position from left to right. For the third key value, first four numbers from left to right are the same as the first key value, and the last four numbers from left to right are the same as the second key value.

Referring to FIG. 4 , compared with FIG. 3 , four I/O ports K 1 , K 2 , K 3 , and K 4 are provided in the scanning circuit 201 with sixteen switches S 1 - 1 ˜S 4 - 4 in a switch matrix 201 a.

Referring to FIG. 5 , the scanning application 300 is implemented by the processing unit 100 for scanning the keyboard 10 to determine which key is pressed, as follows.

In Step 501 , the processing unit 100 sets the I/O ports K 1 ˜Kn to input ports. In Step 502 , the processing unit 100 determines whether one of the I/O ports K 1 ˜Kn is changed to low. If so, Step 503 is implemented, and if not, Step 501 is repeated. In Step 503 , the processing unit 100 records a first key value. In Step 504 , the processing unit 100 sets all the I/O ports K 1 ˜Kn to output ports, and sets the voltage of the I/O port the state of which has been changed to low to high and the voltages of other I/O ports to low. In Step 505 , the processing unit 100 resets all the I/O ports K 1 ˜Kn to input ports, checks the I/O ports K 1 ˜Kn, and records a second key value. In Step 506 , the processing unit 100 determines a third key value according to the first key value and the second key value. In Step 507 , the processing unit 100 consults the key table to determine which switch is pressed according to the third key value.

It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being or exemplary embodiments of the present disclosure.