Charge pump and display driving system including the same

This U.S. non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0109691, filed on Nov. 13, 2009, in the Korean Intellectual Property Office (KIPO), the entire contents of which are hereby incorporated herein by reference.

1. Field

Example embodiments of the inventive concepts relate to a boosting voltage generating technology. More particularly, example embodiments relate to a charge pump used in a semiconductor integrated circuit and a display driving system including the charge pump.

2. Description of Conventional Art

Many circuits requiring a high operational voltage may exist in a semiconductor integrated circuit. If circuits which are used with a device requiring a high operating voltage or which require a high operating voltage exist in a semiconductor integrated circuit, it may be necessary to generate a voltage higher than a power voltage in the integrated circuit. Charge pumps are boosting devices that use capacitors and perform based on the law of conversation of electric charge. Charge pumps that are configured to generate a voltage higher than a supplied power voltage are widely used in electronic devices, such as memories, flat panel displays, etc. Nonvolatile memories, such as electrically erasable programmable read only memories (EEPROMs) and flash memories, use a high voltage to read and write data, and flat panel displays use a high voltage to drive an organic light emitting diode (OLED) or a thin film transistor (TFT)-liquid crystal display (LCD).

In order for a charge pump to be applied to a mobile display driving circuit, a high driving current is needed. Since a higher voltage is also needed, the charge pump increasing a voltage from a lower supplied power voltage is needed. Also, since power is supplied from a portable battery, power efficiency is very important. In general, charge pumps receive a phase (or clock) signal that is an operation reference signal to boost a voltage using a capacitor. Then, the charge pumps send the boosted voltage to an output terminal through a switch. The output terminal may suffer from current consumption due to an external load connected to the output terminal. The output terminal may also suffer from current consumption because an output voltage is decreased from the boosted voltage if the current consumption is increased. Accordingly, charge pumps should be designed to constantly supply a boosted voltage despite current consumption.

Example embodiments of the inventive concepts provide a charge pump having improved current driving capability.

According to an embodiment of the inventive concepts, there is provided a display driving system including a charge pump having improved current driving capability.

According to another embodiment of the inventive concepts, there is provided a charge pump including. The charge pump includes a first converting unit configured to receive a first voltage in response to a first clock signal to generate a first pumping voltage. The first converting unit may also be configured to alternately output the first pumping voltage to a first terminal and a second terminal. The charge pump may also include a second converting unit configured to receive the first pumping voltage through the first terminal or the second terminal in response to a second clock signal and a third clock signal respectively, to generate a second pumping voltage. The second converting unit may also be configured to provide the second pumping voltage to an output terminal, wherein the second converting unit is configured to provide the second pumping voltage to the output terminal for at least half of a period of the second clock signal or the third clock signal.

According to another aspect of the present invention, there is provided a display driving system including. The display may include a display panel having a plurality of scan lines and a plurality of data lines vertically intersecting each other and switching elements and pixel electrodes arranged at intersections between the plurality of scan lines and the plurality of data lines. The display driving system may include a scan driving unit configured to provide a scan signal to the plurality of scan lines of the display panel. The display driving system may include a data driving unit configured to provide gradation information to the plurality of data lines of the display panel. The display driving system may further include a timing controller configured to scan driving unit and the data driving unit. The display driving system may also include a charge pump configured to provide a driving voltage to at least one of the display panel, the scan driving unit, the data driving unit, and the timing controller. The charge pump may include a first converting unit configured to receive a first voltage in response to a first clock signal to generate a first pumping voltage. The first converting unit is also configured to alternately output the first pumping voltage to a first terminal and a second terminal. The charge pump includes a second converting unit configured to receive the first pumping voltage through the first terminal or the second terminal in response to a second clock signal and a third clock signal respectively, to generate a second pumping voltage. The second converting unit is configured to provide the second pumping voltage to an output terminal, wherein the second converting unit is configured to provide the third voltage to the output terminal for half of a period of the second clock signal and for half of a period of the third clock signal.

Exemplary embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1A is a circuit diagram of a charge pump which outputs a voltage that is 3 times higher than a power voltage;

FIG. 1B is a timing diagram illustrating the operation of the charge pump of FIG. 1A in a steady state;

FIG. 2 is a block diagram of a charge pump according to an embodiment of the inventive concepts;

FIG. 3 is a circuit diagram of a positive charge pump according to an embodiment of the inventive concepts;

FIG. 4 is a timing diagram illustrating the operation of the positive charge pump of FIG. 3 in a steady state;

FIG. 5 is a circuit diagram illustrating the operation of the positive charge pump of FIG. 3 in a φ 11 interval of FIG. 4 ;

FIG. 6 is a circuit diagram illustrating the operation of the positive charge pump of FIG. 3 in a φ 12 interval of FIG. 4 ;

FIG. 7 is a circuit diagram illustrating the operation of the positive charge pump of FIG. 3 in a φ 21 interval of FIG. 4 ;

FIG. 8 is a circuit diagram illustrating the operation of the positive charge pump of FIG. 3 in a φ 22 interval of FIG. 4 ;

FIG. 9 is a circuit diagram of a negative charge pump according to an embodiment of the inventive concepts;

FIG. 10 is a timing diagram illustrating the operation of the negative charge pump of FIG. 9 in a steady state;

FIG. 11 is a circuit diagram illustrating the operation of the negative charge pump of FIG. 9 in a φ 11 interval of FIG. 10 ;

FIG. 12 is a circuit diagram illustrating the operation of the negative charge pump of FIG. 9 in a φ 12 interval of FIG. 10 ;

FIG. 13 is a circuit diagram illustrating the operation of the negative charge pump of FIG. 9 in a φ 21 interval of FIG. 10 ;

FIG. 14 is a circuit diagram illustrating the operation of the negative charge pump of FIG. 9 in a φ 22 interval of FIG. 10 ;

FIG. 15 is a circuit diagram of a positive charge pump according to another embodiment of the inventive concepts;

FIG. 16 is a timing diagram illustrating the operation of the positive charge pump of FIG. 15 which generates a voltage of 2VDD in a steady state;

FIG. 17 is a circuit diagram illustrating the operation of the positive charge pump of FIG. 15 which generates a voltage of 2VDD in a φ 1 interval of FIG. 16 ;

FIG. 18 is a circuit diagram illustrating the operation of the positive charge pump of FIG. 15 which generates a voltage of 2VDD in a φ 2 interval of FIG. 16 ;

FIG. 19 is a circuit diagram of a negative charge pump according to another embodiment of the inventive concepts;

FIG. 20 is a timing diagram illustrating the operation of the negative charge pump of FIG. 19 which generates a voltage of −VDD in a steady state;

FIG. 21 is a circuit diagram illustrating the operation of the negative charge pump of FIG. 19 which generates a voltage of −VDD in a φ 1 interval of FIG. 20 ;

FIG. 22 is a circuit diagram illustrating the operation of the negative charge pump of FIG. 19 which generates a voltage of −VDD in a φ 2 interval of FIG. 20 ; and

FIG. 23 is a block diagram of a display driving system according to an embodiment of the inventive concepts.

Example embodiments of inventive concepts will now be described more fully with reference to the accompanying drawings. However, example embodiments may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail to avoid the unclear interpretation of the example embodiments. Throughout the specification, like reference numerals in the drawings denote like elements.

It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it may be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there may be no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature′s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes”, and/or “including” if used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1A is a circuit diagram of a charge pump 100 which outputs a voltage that is 3 times higher than a power voltage VDD. FIG. 1B is a timing diagram illustrating the operation of the charge pump 100 of FIG. 1A in a steady state.

Referring to FIGS. 1A and 1B , the charge pump 100 includes three switches S 11 , S 21 , and S 31 , two pumping capacitors C 11 and C 21 , and an output capacitor Cout 1 between an output terminal and a ground. A clock signal CLK 11 alternating between a power voltage VDD and a ground voltage GND is applied to an N 31 terminal. A clock signal CLK 21 alternating between the power voltage VDD and the ground voltage GND is applied to an N 41 terminal. The clock signal CLK 11 and the clock signal CLK 21 have opposite phases. The charge pump 100 may generate a desired output voltage up to 3VDD as the switches S 11 through S 31 are turned on/off at desired or predetermined points of time.

During a steady state, such as in interval A, since the clock signal CLK 11 is at a lower level (GND) and the switch S 11 is turned on, a potential of the N 11 terminal is the power voltage VDD. Also during interval A, a potential of the N 31 terminal is the ground voltage GND so that the pumping capacitor C 11 is charged to the power voltage VDD. In interval B, if the clock signal CLK 11 is at a higher level (VDD), the switch S 11 is turned off, the switch S 21 is turned on, and the clock signal CLK 21 is at a lower level (GND), then the potential of the N 31 terminal changes from the ground voltage GND to the power voltage VDD. Also, the voltage of the N 11 terminal is boosted from the ground voltage VDD to 2VDD due to capacitor coupling effect. If the switch S 21 is turned on, a potential of the N 21 terminal becomes 2VDD, the N 41 terminal is grounded due to the clock signal CLK 21 that is at a low level (GND), and the pumping capacitor C 21 is charged to 2VDD. In interval C, the clock signal CLK 21 is at a high level (VDD), the potential of the N 41 terminal changes from the ground to the power voltage VDD. Also, the potential of the N 21 terminal is boosted from 2VDD to 3VDD due to capacitor coupling effect. Additionally, in interval C the switch S 31 is turned on, the potential 3VDD of the N 21 terminal is transmitted to the output terminal, an output voltage Vout 1 becomes 3VDD, and the output capacitor Cout 1 is charged to 3VDD. Accordingly, 3VDD is obtained using the power voltage VDD.

FIG. 2 is a block diagram of a charge pump 200 according to an embodiment of the inventive concepts.

Referring to FIG. 2 , the charge pump 200 includes a first converting unit 210 and a second converting unit 220 . The first converting unit 210 converts a power voltage VDD in response to a clock signal CLK 12 to generate a first pumping voltage. Also, the first converting unit 210 alternately outputs the first pumping voltage to an N 12 terminal and to an N 22 terminal. The second converting unit 220 converts the first pumping voltage provided through the N 12 terminal or the N 22 terminal in response to a clock signal CLK 22 or a clock signal CLK 32 to generate a second pumping voltage. Also, the second converting unit 220 provides the second pumping voltage to an output terminal. If the clock signals CLK 22 and CLK 32 have opposite phases, the second pumping voltage is provided to the output terminal Vout 2 in response to the clock signal CLK 22 for one half of a period of the clock signal CLK 22 . For the other half period, the second pumping voltage is provided to the output terminal in response to the clock signal CLK 32 . The second converting unit 220 responds to clock signals CLK 22 and CLK 32 so that the charge pump 200 can charge an output capacitor Cout 2 for one clock signal period, thereby improving current driving capability of the charge pump 200 .

FIG. 3 is a circuit diagram of a positive charge pump 300 according to an embodiment of the inventive concepts.

Referring to FIG. 3 , a positive charge pump 300 includes a first converting unit 310 and a second converting unit 320 .

The first converting unit 310 includes a switch Si providing a power voltage VDD to a terminal N 3 , and a pumping capacitor C 3 having a first terminal to which the N 3 terminal is connected. The first converting unit 310 also includes a second terminal N 6 to which a clock signal CLK 1 is applied. Furthermore, the first converting unit 310 includes a first transmitting unit 312 transmitting a potential of the N 3 terminal to an N 1 terminal or an N 2 terminal. The first transmitting unit 312 may include switches S 2 and S 3 respectively transmitting the potential of the N 3 terminal to the N 1 terminal and the N 2 terminal.

The second converting unit 320 includes a pumping capacitor C 1 having a first terminal to which the N 1 terminal is connected and a second terminal to which a clock signal CLK 2 is applied. The second converting unit 320 also includes a pumping capacitor C 2 having a first terminal to which the N 2 terminal is connected and a second terminal to which a clock signal CLK 3 is applied. More so the second converting 320 unit includes a second transmitting unit 322 providing a potential of the N 1 terminal or the N 2 terminal to an output terminal. The second transmitting unit 322 may include a switch S 4 providing the potential of the N 1 terminal to the output terminal and a switch S 5 transmitting the potential of the N 2 terminal to the output terminal Vout. If the clock signals CLK 2 and CLK 3 have opposite phases and the clock signals CLK 1 through CLK 3 alternate between a power voltage VDD and a ground voltage GND. Thus, the positive charge pump 300 can generate a voltage up to 3VDD using the power voltage VDD.

More specifically, the first converting unit 310 positively boosts the power voltage VDD to generate a voltage of 2VDD, and the first converting unit 310 transmits the voltage of 2VDD to the second converting unit 320 . The second converting unit 320 positively boosts the voltage of 2VDD provided from the first converting unit 310 to generate a voltage of 3VDD. The second converting unit 320 provides the voltage of 3VDD to the output terminal in response to the clock signal CLK 2 for one half of a period of the clock signal CLK 2 . The second converting unit 320 provides the voltage of 3VDD to the output terminal in response to the clock signal CLK 3 for the other half of the period of the clock signal CLK 2 . Accordingly, since the second converting unit 320 can charge an output capacitor Cout to the voltage of 3VDD for one period of the clock signal CLK 2 or CLK 3 , the positive charge pump 300 can generate the voltage of 3VDD that is three times higher than the power voltage VDD, thereby improving current supply capability.

FIG. 4 is a timing diagram illustrating the operation of the positive charge pump of FIG. 3 in a steady state.

Referring to FIG. 4 , the clock signal CLK 1 has a frequency that is two times higher than each of those of the clock signals CLK 2 and CLK 3 . Additionally, the clock signals CLK 2 and CLK 3 have opposite phases. Also, the clock signals CLK 1 through CLK 3 change between the power voltage VDD and the ground voltage GND. In this example embodiment, the positive charge pump 300 can generate a voltage of 3VDD that is three times higher than the power voltage VDD.

A process of generating a voltage of 3VDD will now be explained briefly with reference to FIGS. 3 and 4 . Explanation will be first made on how the first converting unit 310 boosts the power voltage VDD to obtain a voltage of 2VDD. The first converting unit then may transmit the voltage of 2VDD to the second converting unit 320 . In a φ 11 interval, a potential of the N 3 terminal is initialized to the power voltage VDD. In a φ 12 interval, the potential of the N 3 terminal may be positively boosted to a voltage of 2VDD. The potential VDD of the N 3 terminal may be transmitted to the N 1 terminal. As a result, the first converting unit 310 boosts the potential of the N 3 terminal from the power voltage VDD to the voltage of 2VDD. Then, the first converting unit 310 transmits the voltage of 2VDD to the N 1 terminal in a φ interval consisting of the φ 11 interval and the φ 12 interval. In a φ 21 interval, the potential of the N 3 terminal is initialized to the power voltage VDD. In a φ 22 interval, the N 3 terminal is positively boosted to a voltage of 2VDD and the potential 2VDD of the N 3 terminal is transmitted to the N 2 terminal. As a result, the first converting unit 310 positively boosts the potential of the N 3 terminal from the power voltage VDD to the voltage of 2VDD and transmits the voltage of 2VDD to the N 2 terminal in a φ 2 interval. The φ 2 consisting of the φ 21 interval and the φ 22 interval. Thus, the first converting unit 310 generates a voltage of 2VDD and transmits the voltage of 2VDD to the N 1 terminal in the φ 1 interval, and during the φ 2 interval the first converting unit 310 generates a voltage of 2VDD and transmits the voltage of 2VDD to the N 2 .

Next, explanation will be made on how the second converting unit 320 positively boosts the voltage provided from the first converting unit 310 . The second converting unit 320 uses the provided voltage to generate a voltage of 3VDD and provides a voltage of 3VDD to the output terminal. A potential of the N 1 terminal is initialized to the received 2VDD from the first converting unit 310 in the φ 12 interval. The 2VDD voltage is positively boosted to a voltage of 3VDD and transmitted to the output terminal in the φ 2 interval. The φ 2 interval consisting of the φ 21 interval and the φ 22 interval. Also, a potential of the N 2 terminal is initialized to the 2VDD voltage received from the first converting unit 310 in the φ 22 interval The 2VDD voltage is positively boosted to a voltage of 3VDD and transmitted to the output terminal in the φ 1 interval. The φ 1 interval consisting of the φ 11 interval and the φ 12 interval. Thus, the second converting unit 320 boosts the potential of the N 1 terminal from the voltage of 2VDD to the voltage of 3VDD and transmits the voltage of 3VDD to the output terminal in the φ 2 interval. Also, the second converting unit 320 boosts the potential voltage of the N 2 terminal from 2VDD to the 3VDD and outputs the voltage of 3VDD to the output terminal in the φ 1 interval. Accordingly, the positive charge pump 300 continuously generates the voltage of 3VDD for one period (φ 1 +φ 2 ) of the clock signal CLK 2 or the clock signal CLK 3 , and charges the output capacitor Cout.

The operation of the positive charge pump 300 will now be explained in detail with reference to FIGS. 5 through 8 .

FIG. 5 is a circuit diagram illustrating the operation of the positive charge pump 300 of FIG. 3 in the φ 1 interval of FIG. 4 .

Referring to FIG. 5 , a voltage stored in the pumping capacitor C 3 in the φ 11 interval is lower than the power voltage VDD due to a discharge in φ 22 interval. At this time, the clock signal CLK 1 is at a low level GND and applied to terminal N 6 .Thus, a potential of an N 6 terminal is changed from the power voltage VDD to the ground voltage GND. The switch S 1 is turned on to recover a potential voltage of the N 3 terminal which is higher than the power voltage VDD due to a discharge to the power voltage VDD. During the φ 11 interval, the first converting unit 310 does not transmit the potential of the N 3 terminal to the N 1 terminal and the N 2 terminal because the switches S 2 and S 3 are turned off. As a result, the pumping capacitor C 3 is charged to the power voltage VDD.

A voltage according to the amount of charge stored in the pumping capacitor C 1 in the cp 11 interval is lower than a voltage of 2VDD due to a discharge in the φ 2 interval. In the φ 11 interval, since the clock signal CLK 2 is at a low level, a potential of the N 4 terminal is changed from the power voltage VDD to the ground voltage GND. As a result, a potential of the N 1 terminal is lower than the voltage of 2VDD.

In the φ 11 interval, a charge of 2VDD is already stored in the pumping capacitor C 2 . In the φ 11 interval, since the clock signal CLK 3 is at a higher level (VDD), a voltage potential of the N 5 terminal is changed from the ground voltage GND to the power voltage VDD and a potential of the N 2 terminal is positively boosted from the voltage of 2VDD to a voltage of 3VDD due to coupling effect. In the φ 11 interval, the second transmitting unit 322 transmits the potential 3VDD of the N 2 terminal to the output terminal. That is, the switch S 4 is turned off, and the switch S 5 is turned on to transmit the potential 3VDD of the N 2 terminal to the output terminal, thereby charging the output capacitor Cout.

FIG. 6 is a circuit diagram illustrating the operation of the positive charge pump 300 of FIG. 3 in the φ 12 interval of FIG. 4 .

Referring to FIG. 6 , in the φ 12 interval, the pumping capacitor C 3 is charged to the power voltage VDD. In the φ 12 interval, since the switch S 1 is turned off and the clock signal CLK 1 is at a high level (VDD), a potential of the N 6 terminal is changed from the ground voltage GND to the power voltage VDD. Since the pumping capacitor C 3 is already charged to the voltage VDD, a potential of the N 3 terminal is positively boosted from the power voltage VDD to a voltage of 2VDD due to capacitor coupling effect. That is, the φ 12 interval is an interval in which the first converting unit 310 generates a pumping voltage of 2VDD.

Since the clock signal CLK 2 is still at a lower level (GND) in the φ 12 interval, a potential voltage of the N 4 terminal is maintained at the ground voltage GND. A voltage according to the amount of charge stored in the pumping capacitor C 1 is lower than a voltage of 2VDD due to a discharge in the φ 2 interval. Accordingly, a potential of the N 1 terminal is lower than the 2VDD voltage. In the φ 12 interval, the first transmitting unit 312 transmits the potential of the N 3 terminal to the N 1 terminal. That is, the switch S 2 is turned on and the switch S 3 is maintained in an off state. Accordingly, the voltage potential of the N 1 terminal is lowered due to a discharge in the φ 2 interval. However, the voltage potential of the N 1 terminal is recovered to the voltage of 2VDD in the φ 12 interval. As a result, the pumping capacitor C 1 is charged to the voltage of 2VDD.

Since the clock signal CLK 3 is still at a higher level (VDD) in the p 12 interval, a potential of the N 5 terminal is maintained at the power voltage VDD. In the φ 12 , the second transmitting unit 322 still transmits a potential of the N 2 terminal to the output terminal. That is, since the switch S 4 is turned off and the switch S 5 is turned on, the potential of the N 2 terminal can be transmitted to the output terminal, thereby charging the output capacitor Cout.

FIG. 7 is a circuit diagram illustrating the operation of the positive charge pump 300 of FIG. 3 in the φ 21 interval of FIG. 4 .

Referring to FIG. 7 , in the φ 21 interval a charge voltage stored in the pumping capacitor C 3 is lower than the power voltage VDD due to a discharge in the φ 12 interval. In the φ 21 interval, the clock signal CLK 1 is at a lower level (GND) and is applied to the terminal N 6 .A potential voltage of the N 6 terminal is changed from the power voltage VDD to the ground voltage GND. In the φ 21 interval, the switch 51 is turned on to recover a potential voltage of the N 3 terminal which is lower than the power voltage VDD due to a discharge to the power voltage VDD. Also in the φ 21 interval, the first transmitting unit 312 does not transmit the potential of the N 3 terminal to either the N 1 terminal or the N 2 terminal. That is, the switch S 2 is turned off and the switch S 3 is still in an off state. As a result, the pumping capacitor C 3 is charged to the power voltage VDD again.

In the φ 21 interval a charge voltage of 2VDD is already stored in the pumping capacitor C 1 Since the clock signal CLK 2 is at a higher level (VDD) in the φ 21 interval, a potential of the N 4 terminal is changed from the ground voltage GND to the power voltage VDD. Accordingly, a potential of the N 1 terminal is positively boosted from a voltage of 2VDD to a voltage of 3VDD due to capacitor coupling effect. At this time, the second transmitting unit 322 transmits the potential 3VDD of the N 1 terminal to the output terminal. That is, the switch S 4 is turned on, the switch S 5 is turned off, and the potential 3VDD of the N 1 terminal is transmitted to the output terminal, thereby charging the output capacitor Cout.

A voltage according to the amount of charge stored in the pumping capacitor C 2 in the φ 21 interval is lower than a voltage of 2VDD due to a discharge in the φ 1 interval. Since the clock signal CLK 3 is at a lower level (GND), a potential of the N 5 terminal is changed from the power voltage VDD to the ground voltage GND. As a result, the potential of the N 2 terminal is lower than the voltage of 2VDD.

FIG. 8 is a circuit diagram illustrating the operation of the positive charge pump 300 of FIG. 3 in the φ 22 interval of FIG. 4 .

Referring to FIG. 8 , the pumping capacitor C 3 is charged to the power voltage VDD in the φ 22 interval. At this time, since the switch Si is turned off and the clock signal CLK 1 is at a higher level (VDD), a potential of the N 6 terminal is changed from the ground voltage GND to the power voltage VDD. Since the pumping capacitor C 3 is already charged to the power voltage VDD, a voltage potential of the N 3 terminal is positively boosted from the power voltage VDD to a voltage of 2VDD due to capacitor coupling effect. That is, during the φ 22 interval the first converting unit 310 generates a pumping voltage of 2VDD, similar to the φ 12 interval.

Since the clock signal CLK 2 is still at a higher level (VDD) in the φ 22 interval, a potential of the N 4 terminal is maintained at the power voltage VDD. The second transmitting unit 322 transmits a potential of the N 1 terminal to the output terminal. Since the switch S 4 is turned on and the switch S 5 is turned off, the potential of the N 1 terminal is transmitted to the output terminal, thereby charging the output capacitor Cout.

Since the clock signal CLK 3 is still at a lower level (GND) in the φ 22 interval, a potential of the N 5 terminal is maintained at the ground voltage GND. A charge voltage stored in the pumping capacitor C 2 is lower than a voltage of 2VDD due to a discharge in the φ 1 interval. Accordingly, a potential of the N 2 terminal is lower than the voltage of 2VDD. In the φ 22 , the first transmitting unit 312 transmits the potential 2VDD of the N 3 terminal to the N 2 terminal. That is, the switch S 2 is still turned off and the switch S 3 is turned on. Accordingly, the voltage potential of the N 2 terminal which is lower than the voltage of 2VDD due to a discharge is recovered to the voltage of 2VDD in the φ 22 interval. As a result, the pumping capacitor C 2 is charged to the voltage of 2VDD.

FIG. 9 is a circuit diagram of a negative charge pump 900 according to an example embodiment of the inventive concepts.

Referring to FIG. 9 , the negative charge pump 900 includes a first converting unit 910 and a second converting unit 920 . The first converting unit 910 includes an initialization switch S 1 ′ providing a ground voltage GND to an N 3 ′ terminal. The first converting unit 910 also includes a pumping capacitor C 3 ′ having one end connected to terminal N 3 ′ and another end receiving a clock signal CLK 1 ′. Also, the first converting unit 910 includes a first transmitting unit 912 configured to transmit a potential voltage of the N 3 ′ terminal to an N 1 ′ terminal or an N 2 ′ terminal. The second converting unit 920 includes a pumping capacitor C 1 ′ having one end connected to a N 1 ′ terminal and an other end receiving clock signal CLK 2 ′. The second converting unit 920 also includes a pumping capacitor C 2 ′ connected having one end connected to a N 2 ′ terminal and an other end receiving clock signal CLK 3 ′. The second converting unit 920 also includes a second transmitting unit 922 configured to provide a potential voltage of the N 1 ′ terminal or the N 2 ′ terminal to an output terminal. If the clock signals CLK 2 ′ and CLK 3 ′ have opposite phases, and the clock signals CLK 1 ′ through CLK 3 ′ alternate between a power voltage VDD and the ground voltage GND, the negative charge pump 900 negatively boosts the power voltage VDD to generate a voltage of −2VDD. In detail, the first converting unit 910 is configured to negatively boost the power voltage VDD to generate a voltage of −VDD. Then, the first converting unit 910 transmits the voltage of −VDD to the second converting unit 920 . The second converting unit 920 negatively boosts the voltage of −VDD provided from the first converting unit 910 to generate a voltage of −2VDD. The second converting unit 920 is configured to provide the voltage of −2VDD to the output terminal in response to the clock signal CLK 2 ′ for one half of a period of the clock signal CLK 2 ′, and provides the voltage of −2VDD to the output terminal in response to the clock signal CLK 3 ′ for the other half of the period of the clock signal CLK 2 ′. Accordingly, since the second converting unit 920 can charge an output capacitor Cout′ to the voltage of −2VDD for one period of either clock signal CLK 2 ′ or CLK 3 ′, the negative charge pump 900 can continually generate the voltage of −2VDD, thereby improving current supply capability.

FIG. 10 is a timing diagram illustrating the operation of the negative charge pump 900 of FIG. 9 in a steady state.

Referring to FIG. 10 , the clock signal CLK 1 ′ has a frequency that is two times higher than each of those of the clock signals CLK 2 ′ and CLK 3 ′. Also, the clock signals CLK 2 ′ and CLK 3 ′ have opposite phases. The clock signals CLK 1 ′ through CLK 3 ′ alternate between the power voltage VDD and the ground voltage GND. In this example embodiment, the negative charge pump 900 can generate a voltage of −2VDD.

A process of generating a voltage of −2VDD will be briefly explained with reference to FIGS. 9 and 10 . Explanation will be first made on how the first converting unit 910 negatively boosts the power voltage VDD to generate a voltage of −VDD and transmits the voltage of −VDD to the second converting unit 920 . In a φ 11 ′ interval, a voltage potential of the N 3 ′ terminal is initialized to the ground voltage GND. Then, the voltage potential is negatively boosted to a voltage of −VDD in a φ 12 ′ interval. At this time, the voltage potential −VDD of the N 3 ′ terminal is transmitted to the N 1 ′ terminal. As a result, the first converting unit 910 negatively boosts the voltage potential of the N 3 ′ terminal from the ground voltage GND to the voltage of −VDD and transmits the voltage of −VDD to the N 1 ′ terminal in a φ 1 ′ interval consisting of the interval and the φ 12 ′ interval. In a φ 21 ′ interval, the potential of the N 3 ′ terminal is initialized to the ground voltage GND, and then the potential of the N 3 ′ terminal is negatively boosted to a voltage of −VDD in a φ 22 ′ interval. At this time, the potential −VDD of the N 3 ′ terminal is transmitted to the N 2 ′ terminal, unlike that in the φ 12 ′ interval. As a result, the first converting unit 910 negatively boosts the potential of the N 3 ′ terminal to the voltage of −VDD. Then, the first converting unit 910 transmits the voltage of −VDD to the N 2 ′ terminal in a φ 2 ′ interval consisting of the φ 21 ′ interval and the φ 22 ′ interval. As a result, the first converting unit 910 generates the voltage of −VDD and transmits the voltage of −VDD to the N 1 ′ terminal in the φ 1 ′ interval. Also, the first converting unit 910 generates the voltage of −VDD and transmits the voltage of −VDD to the N 2 ′ terminal in the φ 2 ′ interval.

Next, explanation will be made on how the second converting unit 920 negatively boosts the voltage of −VDD provided from the first converting unit 910 to generate a voltage of −2VDD. It will also be explained how the second converting unit 920 provides the voltage of −2VDD to the output terminal Vout′. A voltage potential of the N 1 ′ terminal is initialized to the voltage of −VDD received from the first converting unit 910 in the φ 12 ′ interval, and is negatively boosted to a voltage of −2VDD. The second converting unit 920 also transmits the negatively boosted voltage −2VDD to the output terminal Vout′ in the φ 2 ′ interval consisting of the φ 21 ′ interval and the φ 22 ′ interval. Meanwhile, a potential voltage of the N 2 ′ terminal is initialized to the voltage of −VDD received from the first converting unit 910 in the φ 22 ′ interval. Then, the second converting unit 920 is negatively boosted the voltage to a voltage of −2VDD and transmitted to the output terminal in the φ 1 ′ interval consisting of the φ 11 ′ interval and the φ 12 ′ interval. That is, the second converting unit 920 boosts the potential of the N 1 ′ terminal from the voltage of −VDD to the voltage of −2VDD and transmits the voltage of −2VDD to the output terminal in the φ 2 ′ interval. Also, the second converting unit 920 boosts the potential of the N 2 ′ terminal from the voltage of −VDD to the voltage of −2VDD and transmits the voltage of −2VDD to the output terminal in the φ 1 ′ interval. Accordingly, the negative charge pump 900 can continuously generate the voltage of −2VDD for one period (φ 1 ′+φ 2 ′) of the clock signal CLK 2 ′ or CLK 3 ′, thereby charging the output capacitor Cout′.

The operation of the negative charge pump 900 will now be explained in detail with reference to FIGS. 11 through 14 .

FIG. 11 is a circuit diagram illustrating the operation of the negative charge pump 900 of FIG. 9 in the φ 11 ′ interval of FIG. 10 .

Referring to FIG. 11 , a voltage stored in the pumping capacitor C 3 ′ in the φ 11 ′ interval is lower than the power voltage VDD due to a discharge in the φ 22 ′ interval. At this time, the clock signal CLK 1 ′ that is at a higher level (GND) is applied. Thus, a potential of an N 6 ′ terminal is changed from the ground voltage to the power voltage VDD. The switch S 1 ′ is turned on to recover a potential of the N 3 ′ terminal which is higher than the ground voltage GND due to a discharge to the ground voltage GND. In the φ 11 ′ interval, the first transmitting unit 912 does not transmit the potential of the N 3 ′ terminal to the N 1 ′ terminal and the N 2 ′ terminal. That is, the switches S 2 ′ and S 3 ′ are turned off. As a result, the pumping capacitor C 3 ′ is charged to the power voltage VDD again.

A charge voltage stored in the pumping capacitor C 1 ′ in the φ 11 ′ interval is lower than a voltage of 2VDD due to a discharge in the φ 2 ′ interval. In the interval, since the clock signal CLK 2 ′ is at a higher level (VDD), a potential of the N 4 ′ terminal is changed from the ground voltage GND to the power voltage VDD. As a result, a potential of the N 1 ′ terminal is higher than a voltage of −VDD,

In the interval, a voltage of 2VDD is already stored in the pumping capacitor C 2 ′. At the φ 11 ′ interval, since the clock signal CLK 3 ′ is at a lower level (GND), a potential of the N 5 ′ terminal is changed from the power voltage VDD to the ground voltage GND. Also, a potential of the N 2 ′ terminal is negatively boosted from a voltage of −VDD to a voltage of −2VDD due to coupling effect. In the interval, the second transmitting unit 922 is configured to transmit the potential −2VDD of the N 2 ′ terminal to the output terminal. That is, the switch S 4 ′ is maintained in an off state, the switch S 5 ′ is turned on, and the potential −2VDD of the N 2 ′ terminal is transmitted to the output terminal Vout′, thereby charging the output capacitor Cout′.

FIG. 12 is a circuit diagram illustrating the operation of the negative charge pump 900 of FIG. 9 in the φ 12 ′ interval of FIG. 10 .

Referring to FIG. 12 , the pumping capacitor C 3 ′ is charged to the power voltage VDD in the φ 12 ′ interval. At the φ 12 ′ interval, since the switch S 1 ′ is turned off and the clock signal CLK 1 ′ is at a lower level (GND), a potential of the N 6 ′ terminal is changed from the power voltage VDD to the ground voltage GND. Also the φ 12 ′ interval, the pumping capacitor C 3 ′ is already charged to the power voltage VDD, a potential of the N 3 ′ terminal is negatively boosted from the ground voltage GND to a voltage of −VDD due to capacitor coupling effect. That is, the φ 12 ′ interval is an interval in which the first converting unit 910 generates a pumping voltage of −VDD.

Since the clock signal CLK 2 ′ is still at a higher level (VDD) in the φ 12 ′ interval, a potential of the N 4 terminal is maintained at the power voltage VDD. A charge voltage stored in the pumping capacitor C 1 ′ is lower than a voltage of 2VDD due to a discharge in the φ 2 ′ interval. Accordingly, a potential of the N 1 ′ terminal is higher than a voltage of −VDD. At this time, the first transmitting unit 912 transmits the potential −VDD of the N 3 ′ terminal to the N 1 ′ terminal. That is, the switch S 2 ′ is turned on and the switch S 3 ′ is maintained in an off state. Accordingly, a potential of the N 1 ′ terminal which is higher than the voltage of −VDD due to a discharge in the φ 2 ′ interval is recovered to the voltage of −VDD in the φ 12 ′ interval. As a result, the pumping capacitor C 1 ′ is charged to a voltage of 2VDD again.

Since the clock signal CLK 3 ′ is still at a lower level (VDD) in the φ 12 ′ interval, a potential of the N 5 ′ terminal is maintained at the ground voltage GND. In the φ 12 ′ interval, the second transmitting unit 922 transmits a potential of the N 2 ′ terminal to the output terminal. That is, since the switch S 4 ′ is turned off and the switch S 5 ′ is turned on, the potential of the N 2 ′ terminal is transmitted to the output terminal Vout′, thereby charging the output capacitor Cout′.

FIG. 13 is a circuit diagram illustrating the operation of the negative charge pump 900 of FIG. 9 in the φ 21 ′ interval of FIG. 10 .

Referring to FIG. 13 , a charge voltage stored in the pumping capacitor C 3 ′ in the φ 21 ′ interval is lower than the power voltage VDD due to a discharge in the φ 12 ′ interval. In the φ 21 ′ interval, the clock signal CLK 1 ′ that is at a higher level (GND) is applied to the N 6 ′ terminal. Thus, a potential of the N 6 ′ terminal is changed from the ground voltage GND to the power voltage VDD. The switch S 1 ′ is turned on to recover a potential of the N 3 ′ terminal which is higher than the ground voltage GND due to a discharge to the ground voltage GND. In the φ 21 ′ interval, the first transmitting unit 912 does not transmit the potential of the N 3 ′ terminal to the N 1 ′ terminal and the N 2 ′ terminal. That is, the switch S 2 ′ is turned off and the switch S 3 ′ is maintained in an off state. As a result, the pumping capacitor C 3 ′ is charged to the power voltage VDD again.

A voltage charge of 2VDD is already stored in the pumping capacitor C 1 ′ in the φ 21 ′ interval. Since the clock signal CLK 2 ′ is at a lower level (GND), a potential of the N 4 ′ terminal is changed from the power voltage VDD to the ground voltage GND. Accordingly, a potential of the N 1 ′ terminal is negatively boosted from a voltage of −VDD to a voltage of −2VDD due to capacitor coupling effect. In the φ 21 ′ interval, the second transmitting unit 922 transmits the potential −2VDD of the N 1 ′ terminal to the output terminal. That is, the switch S 4 ′ is turned on, the switch S 5 ′ is turned off, and the potential −2VDD of the N 1 ′ terminal is transmitted to the output terminal Vout′, thereby charging the output capacitor Cout′.

A In the φ 21 interval, a charge voltage stored in the pumping capacitor C 2 ′ may be lower than a voltage of 2VDD due to a discharge in the φ 1 ′ interval. Since the clock signal CLK 3 ′ is at a higher level (VDD), a potential of the N 5 ′ terminal is changed from the ground voltage GND to the power voltage VDD. As a result, a potential of the N 2 ′ terminal is higher than a voltage of −VDD.

FIG. 14 is a circuit diagram illustrating the operation of the negative charge pump 900 of FIG. 9 in the φ 22 ′ interval of FIG. 10 .

Referring to FIG. 14 , the pumping capacitor C 3 ′ is charged to the power voltage VDD in the φ 22 ′ interval. In the φ 22 ′ interval, the switch S 1 ′ is turned off and the clock signal CLK 1 ′ is at a lower level (GND), a potential of the N 6 ′ terminal is changed from the power voltage VDD to the ground voltage GND. Since the pumping capacitor C 3 ′ is already charged to the power voltage VDD, a potential of the N 3 ′ terminal is negatively boosted from the ground voltage to a voltage of −VDD due to capacitor coupling effect. That is, during the φ 22 ′ interval the first converting unit 910 is configured to generate a pumping voltage of −VDD, like the φ 12 ′ interval.

Since the clock signal CLK 2 ′ is still at a lower level (GND) in the φ 22 ′ interval, a potential of the N 4 ′ terminal is maintained at the ground voltage GND. The second transmitting unit 922 is configured to transmit a potential of the N 1 ′ terminal to the output terminal Vout′. That is, since the switch S 4 ′ is turned on and the switch S 5 ′ is turned off, the potential of the N 1 ′ terminal is transmitted to the output terminal, thereby charging the output capacitor Cout′.

Since the clock signal CLK 3 ′ is still at a higher level (VDD) in the φ 22 ′ interval, a potential of the N 5 ′ terminal is maintained at the power voltage VDD. A charge voltage which is stored in the pumping capacitor C 2 ′ is lower than a voltage of 2VDD due to a discharge in the φ 1 ′ interval. Accordingly, a potential of the N 2 ′ terminal is higher than a voltage of −VDD. In the φ 22 ′ interval, the first transmitting unit 912 transmits the potential −VDD of the N 3 ′ terminal to the N 2 ′ terminal That is, the switch S 2 ′ is still turned off and the switch S 3 ′ is turned on. Accordingly, a potential of the N 2 ′ terminal which is higher than a voltage of −VDD due to a discharge is recovered to the voltage of −VDD in the φ 22 ′ interval. As a result, the pumping capacitor C 2 ′ is charged to a voltage of 2VDD again.

FIG. 15 is a circuit diagram of a positive charge pump 1500 according to another embodiment of the inventive concepts.

Referring to FIG. 15 , the positive charge pump 1500 includes a first converting unit 1510 and a second converting unit 1520 . The first converting unit 1510 includes an initialization switch S 15 configured to supply a power voltage VDD to an N 35 terminal. The charge pump 1500 also includes a pumping capacitor C 35 having one end connected to a N 35 terminal and another end receiving clock signal CLK 15 . The charge pump 1500 may also include a first transmitting unit 1512 configured to transmit a potential of the N 35 terminal to an N 15 terminal or an N 25 terminal. The first transmitting unit 1512 may include a switch S 25 and a switch S 35 respectively transmitting the potential of the N 35 terminal to the N 15 terminal and the N 25 terminal. The second converting unit 1520 includes a pumping capacitor C 15 having one end connected to terminal N 15 and an other end receiving a clock signal CLK 25 . The second converting unit 1520 may also include a pumping capacitor C 25 having a first end connected to the N 25 terminal and another end receiving the clock signal CLK 35 . The second converting unit 1520 may have a second transmitting unit 1522 providing a potential of the N 15 terminal or the N 25 terminal to an output terminal. The second transmitting unit 1522 may have initialization switches S 65 and S 75 respectively providing the power voltage VDD to the N 15 terminal and the N 25 terminal. The second transmitting unit 1522 may include a switch S 45 providing the potential of the N 15 terminal to the output terminal and a witch S 55 transmitting the potential of the N 25 terminal to the output terminal. If the clock signals CLK 25 and CLK 35 have opposite phases and the clock signals CLK 15 through CLK 35 alternate between the power voltage VDD and a ground voltage GND. Also, the positive charge pump 1500 may be configured to selectively generate a voltage of 2VDD or 3VDD using the power voltage VDD. For example, if the positive charge pump 1500 generates a voltage of 2VDD, the first converting unit 1510 is inactivated. Therefore, the initialization switches S 65 and S 75 of converting unit 1510 are alternately turned on and off Accordingly, the second converting unit 1520 generates a voltage of 2VDD. If the positive charge pump 1500 generates a voltage of 3VDD, the first converting unit 1510 is activated, and the initialization switches S 65 and S 75 are inactivated to be maintained in an off state. Accordingly, the first converting unit 1510 generates a voltage of 2VDD and the second converting unit 1520 generates a voltage of 3VDD. In an example embodiment, the positive charge pump 1500 generates the voltage of 2VDD or 3VDD to charge the output capacitor for one period of the clock signal CLK 25 or CLK 35 .

FIG. 16 is a timing diagram illustrating the operation of the positive charge pump 1500 of FIG. 15 which generates a voltage of 2VDD in a steady state.

Referring to FIG. 16 , the clock signals CLK 25 and CLK 35 have opposite phases, and alternate between the power voltage VDD and the ground voltage GND. In this example embodiment, the positive charge pump 1500 may generate a voltage of 2VDD that is two times higher than the power voltage VDD.

Since the operation of the positive charge pump 1500 in a 3VDD generation mode is somewhat similar to the operation of the positive charge pump 300 of FIG. 3 , a detailed explanation thereof will not be given.

The operation of the positive charge pump 1500 in a 2VDD generation mode will be explained in detail with reference to FIGS. 17 and 18 .

FIG. 17 is a circuit diagram illustrating the operation of the positive charge pump 1500 of FIG. 15 which generates a voltage of 2VDD in the φ 1 ″ interval of FIG. 16 .

Referring to FIG. 17 , a charge voltage stored in the pumping capacitor C 15 may be lower than the power voltage VDD due to a discharge in the φ 2 ″ interval. Since the clock signal CLK 25 is at a lower level (GND) in the φ 1 ″ interval, a potential of the N 45 terminal is changed from the power voltage VDD to the ground voltage GND. Accordingly, a potential of the N 15 terminal is lower than the power voltage VDD. The initialization switch S 65 is turned on to recover the potential of the N 15 terminal to the power voltage VDD. As a result, the power voltage VDD is applied to both ends of the pumping capacitor C 15 , thereby storing a charge corresponding to the power voltage VDD. Also in the φ 1 ″ interval, the pumping capacitor C 25 is already charged to the power voltage VDD, and a potential of the N 25 terminal is at the power voltage VDD. The initialization switch S 75 is turned off Since the clock signal CLK 35 is at a higher level (VDD), a potential of the N 55 terminal is changed from the ground voltage GND to the power voltage VDD. Accordingly, a potential of the N 25 terminal is positively boosted from the power voltage to a voltage of 2VDD due to capacitor coupling effect. Additionally in the φ 1 ″ interval, the second transmitting unit 1522 transmits the potential 2VDD of the N 25 terminal to the output terminal, thereby charging the output capacitor Cout 5 .

FIG. 18 is a circuit diagram illustrating the operation of the positive charge pump 1500 of FIG. 15 which generates a voltage of 2VDD in the φ 2 ″ interval of FIG. 16 .

Referring to FIG. 18 , the pumping capacitor C 15 is charged to the power voltage VDD and a potential of the N 15 terminal is at the power voltage VDD in the φ 2 ″ interval. The initialization switch S 65 is turned off Since the clock signal CLK 25 is at a higher level (VDD), a potential of the N 45 terminal is changed from the ground voltage GND to the power voltage VDD. Accordingly, a potential of the N 15 terminal is positively boosted from the power voltage VDD to a voltage of 2VDD due to capacitor coupling effect. Also in the φ 2 ″ interval, the second transmitting unit 1522 transmits the potential 2VDD of the N 15 terminal to the output terminal, thereby charging the output capacitor. Additionally, in the φ 2 ″ interval, charge voltage stored in the pumping capacitor C 25 may be lower than the power voltage VDD due to a discharge in the φ 1 ″ interval. Since the clock signal CLK 35 is at a lower level (GND), a potential of the N 55 terminal is changed from the power voltage VDD to the ground voltage GND. Accordingly, a potential of the N 25 terminal is lower than the power voltage VDD. The initialization switch S 75 is turned on to recover the potential of the N 25 terminal to the power voltage VDD. As a result, the power voltage VDD is applied to both ends of the pumping capacitor C 25 , thereby storing charge corresponding to the power voltage VDD in the pumping capacitor C 25 .

As a result, since the positive charge pump 1500 continuously charges the output capacitor Cout 5 to a voltage of 2VDD for one period of the clock signal CLK 25 or CLK 35 , output voltage ripple according to a load current can be minimized.

FIG. 19 is a circuit diagram of a negative charge pump 1900 according to another embodiment of the inventive concepts.

Referring to FIG. 19 , the negative charge pump 1900 includes a first converting unit 1910 and a second converting unit 1920 . The first converting unit 1910 includes an initialization switch S 19 providing a ground voltage GND to an N 39 terminal, a pumping capacitor C 39 having one end connected to N 39 terminal and another end receiving a clock signal CLK 19 . The first converting unit 1910 may also have a first transmitting unit 1912 transmitting a potential of the N 39 terminal to an N 19 terminal or an N 29 terminal. The first transmitting unit 1912 may include switches S 29 and S 39 respectively transmitting a potential of the N 39 terminal to the N 19 terminal and the N 29 terminal. The second converting unit 1920 includes a pumping capacitor C 19 having one end connected to the N 19 terminal and an other end receiving a clock signal CLK 29 The second converting unit 1920 may also have a pumping capacitor C 29 having one end connected to the N 29 terminal and another end connected to a clock signal CLK 39 . The second converting unit may include a second transmitting unit 1922 providing a potential of the N 19 terminal or the N 29 terminal to an output terminal. The converting transmitting unit 1920 may include initialization switches S 69 and S 79 respectively providing a ground voltage GND to the N 19 terminal and the N 29 terminal. The second transmitting unit 1922 may include a switch S 49 providing the potential of the N 19 terminal to the output terminal, and a switch S 59 providing the potential of the N 29 terminal to the output terminal. If the clock signals CLK 29 and CLK 39 have opposite phases, and the clock signals CLK 19 through CLK 39 alternate between the power voltage VDD and the ground voltage GND, the negative charge pump 1900 may selectively generate a voltage of −VDD or −2VDD using the power voltage VDD. For example, if the negative charge pump 1900 generates a voltage of −VDD, the first converting unit 1910 is inactivated, and the initialization switches S 69 and S 79 are activated to be alternately turned on and off. Accordingly, the second converting unit 1920 generates a voltage of −VDD. Meanwhile, if the negative charge pump 1900 generates a voltage of −2VDD, the first converting unit 1910 is activated, and the initialization switches S 69 and S 79 are inactivated to be maintained in an off state. Accordingly, the first converting unit 1910 generates a voltage of −VDD, and the second converting unit 1920 generates a voltage of −2VDD. In an example embodiment, the negative charge pump 1900 generates the voltage of −VDD or −2VDD to charge the output capacitor Cout 9 for one period of the clock signal CLK 29 or CLK 39 .

FIG. 20 is a timing diagram illustrating the operation of the negative charge pump 1900 of FIG. 19 which generates a voltage of −VDD in a steady state.

Referring to FIG. 20 , the clock signals CLK 29 and CLK 39 have opposite phases, and alternate between the power voltage VDD and the ground voltage GND. In an example embodiment, the negative charge pump 1900 is configured to generate a voltage of −VDD.

Since the operation of the negative charge pump 1900 in a 2VDD generation mode is somewhat similar to the operation of the negative charge pump 900 of FIG. 9 a detailed explanation thereof will not be given.

The operation of the negative charge pump 1900 in a −VDD generation mode will be explained with reference to FIGS. 21 and 22 .

FIG. 21 is a circuit diagram illustrating the operation of the negative charge pump 1900 of FIG. 19 which generates a voltage of −VDD in the φ 11 interval of FIG. 20 .

Referring to FIG. 21 , a voltage according to the amount of charge stored in the pumping capacitor C 19 may be lower than the power voltage VDD due to a discharge in the φ 21 interval. Since the clock signal CLK 29 is at a higher level in the φ 11 interval, a potential of the N 49 terminal is changed from the ground voltage GND to the power voltage VDD. Accordingly, a potential of the N 19 terminal is higher than the ground voltage GND. In the φ 11 interval, the initialization switch S 69 is turned on to recover the potential of the N 19 terminal to the ground voltage GND. As a result, the power voltage VDD is applied to both ends of the pumping capacitor C 19 , thereby storing charge the amount of which corresponds to the power voltage VDD. Meanwhile, the pumping capacitor C 29 is already charged to the power voltage VDD, and a potential of the N 29 terminal is at the ground voltage GND. The initialization switch S 79 is turned off. Since the clock signal CLK 39 is at a lower level (GND), a potential of the N 59 is changed from the power voltage VDD to the ground voltage GND. Accordingly, a potential of the N 29 terminal is negatively boosted from the ground voltage GND to a voltage of −VDD due to capacitor coupling effect. At this time in the φ 11 interval, the second transmitting unit 1922 transmits the potential −VDD of the N 221 terminal to the output terminal, thereby charging the output capacitor Cout 9 .

FIG. 22 is a circuit diagram illustrating the operation of the negative charge pump 1900 of FIG. 19 which generates a voltage of −VDD in the φ 21 interval of FIG. 2 .

Referring to FIG. 22 , the pumping capacitor C 19 is already charged to the power voltage VDD in the φ 12 interval, and a potential of the N 19 terminal is at the ground voltage GND. In the φ 21 interval the initialization switch S 69 is turned off Since the clock signal CLK 29 is at a lower level (GND), a potential of the N 49 terminal is changed from the power voltage VDD to the ground voltage GND. Accordingly, a potential of the N 19 terminal is negatively boosted from the ground voltage GND to a voltage of −VDD due to capacitor coupling effect. At this time in the φ 21 interval, the second transmitting unit 1922 transmits the potential −VDD of the N 19 terminal to the output terminal, thereby charging the output capacitor Cout 9 . Meanwhile in the φ 21 interval, a voltage according to the amount of charge stored in the pumping capacitor C 29 is lower than the power voltage VDD due to a discharge in the φ 11 interval. Since the clock signal CLK 39 is at a higher level (VDD), a potential of the N 59 terminal is changed from the ground voltage GND to the power voltage VDD. Accordingly, a potential of the N 29 terminal is higher than the ground voltage GND. The initialization switch S 79 is turned on to recover the potential of the N 29 terminal to the ground voltage GND. As a result, the power voltage VDD is applied to both ends of the pumping capacitor C 29 , thereby storing charge the amount of which corresponds to the power voltage VDD again.

As a result, since the negative charge pump 1900 charges the output capacitor Cout 9 to the power voltage VDD during one period of the clock signal CLK 29 or CLK 39 in a −VDD generation mode, output voltage ripple can be minimized.

FIG. 23 is a block diagram of a display driving system 2300 according to an embodiment of the inventive concepts.

Referring to FIG. 23 , the display driving system, 2300 includes a timing controller 2330 , a scan driving unit 2340 , a data driving unit 2310 , a liquid crystal panel 2320 , and a charge pump 2350 . The timing controller 2330 is configured to generate a control signal for controlling the scan driving unit 2340 and the data driving unit 2310 . The timing controller 2330 is also configured to transmit an external image signal to the data driving unit 2310 .

In detail, the scan driving unit 2340 and the data driving unit 2310 drive the liquid crystal panel 2320 according to the control signal provided by the timing controller 2330 . The scan driving unit 2340 sequentially applies scan signals to row electrodes of the liquid crystal panel 2320 , and thin film transistors (TFTs) connected to the row electrodes are sequentially increased as the scan signals are applied to the row electrodes. A gradation voltage supplied by the data driving unit 2310 is applied to a liquid crystal through the TFTs connected to the row electrodes to which the scan signals are applied. The gradation voltage is used to control the angle of rotation of the liquid crystal and adjust the amount of transmitted light. In order to drive a liquid crystal display (LCD), a source line driving voltage AVDD that is a positive voltage higher than a power voltage VCI input from an external battery is desired or required. Also to drive the liquid crystal display a boosting voltages, such as a gate line high voltage VGH and a gate line low voltage VGL that is a negative voltage lower than a ground voltage GND is desired or required. The source line driving voltage AVDD is used as a driving voltage of source lines for the TFT-LCD pixels. The gate line high voltage VGH and the gate line low voltage VGL are used as a driving voltage of gate lines for the TFT-LCD pixels.

The charge pump 2350 receives a power voltage VCI of about 2.5 to 3.3 V and is configured to generate the voltages AVDD and VGH obtained by positively boosting the power voltage VCI. The charge pump 2350 may also generate a voltage VGL obtained by negatively boosting the power voltage VCI. Also the charge pump 2350 , may provide the voltages AVDD, VGH, and VGL to the scan driving unit 2340 and the data driving unit 2310 . The data driving unit 2310 receives the source line driving voltage AVDD from the charge pump 2350 and supplies a gradation voltage corresponding to a received image signal. The scan driving unit 2340 receives the gate line higher voltage VGH and the gate line lower voltage VGL from the charge pump 2350 and may use them as on-off voltages of the TFTs connected to the row electrodes.

While embodiments of inventive concepts have been particularly shown and described with reference to exemplary embodiments thereof using specific terms, the embodiments and terms have been used to explain the inventive concept and should not be construed as limiting the scope of the inventive concept defined by the claims. Therefore, the scope of the inventive concepts is defined not by the detailed description of the inventive concepts but by the appended claims, and all differences within the scope will be construed as being included in the inventive concepts.