Circuit for aligning input signals

Embodiments of the disclosure relate to a circuit for aligning input signals.

Often, during manufacturing and testing of integrated chips manual efforts are required to encounter challenges of meeting certain constraints, for example timing requirements. Existing techniques employ low cost testers to test the timing requirements of the integrated chips. However, while sending input signals to a device under test (DUT) the input signals can be misaligned with respect to each other. The misalignment of the input signals can be due to interface uncertainties. Further, board parasitics and package parasitics can also cause additional interface uncertainties. Such interface uncertainties need to be considered while designing which in turn makes designing a time consuming, complex, and cumbersome process.

In an existing technique, the interface uncertainties can be minimized by adding a finite delay to each input signal of the input signals. However, calculation of the finite delay can be inaccurate due to manual intervention. Further, manual efforts involved in calculation of the finite delay increases with increase in number of the input signals leading to time inefficiency and increased inaccuracy.

An example of a circuit for aligning input signals includes a clock generating circuit that is responsive to a first signal and a second signal to generate a clock signal. The first signal is associated with a first input signal of the input signals and the second signal is associated with a second input signal of the input signals. The circuit also includes a first flip flop coupled to the clock generating circuit. The first flip flop is responsive to a first type of edge of the clock signal to output the first signal. The circuit further includes a second flip flop coupled to the clock generating circuit. The second flip flop is responsive to the first type of edge of the clock signal to output the second signal. Further, the circuit includes a finite state machine (FSM) that is coupled to the clock generating circuit, the first flip flop and the second flip flop. The FSM is responsive to a second type of edge of the clock signal to detect early arrival of one of the first signal and the second signal with respect to each other. The FSM also generates a first control signal that is indicative of delay to be added to the first input signal if early arrival of the first signal is detected, and a second control signal that is indicative of delay to be added to the second input signal if early arrival of the second signal is detected. Moreover, the circuit includes a first programmable delay element and a second programmable delay element. The first programmable delay element is coupled to the FSM to delay the first input signal based on the first control signal if early arrival of the first signal is detected. The second programmable delay element is coupled to the FSM to delay the second input signal based on the second control signal if early arrival of the second signal is detected.

An example of a circuit includes a clock generating circuit to generate a clock signal based on a plurality of signals. The circuit also includes a plurality of flip flops coupled to the clock generating circuit to output the plurality of signals at a first type of edge of the clock signal. One flip flop of the plurality of flip flops corresponds to one signal of the plurality of signals. The circuit further includes a finite state machine (FSM) coupled to the clock generating circuit and the plurality of flip flops. The FSM is responsive to a second type of edge of the clock signal to detect at least one early arriving signal from the plurality of signals and to generate a control signal based on detection. Further, the circuit includes a plurality of programmable delay elements coupled to the FSM. At least one programmable delay element of the plurality of programmable delay elements is responsive to the control signal to delay at least one input signal associated with the at least one early arriving signal. One programmable delay element corresponds to one signal of the plurality of signals and the at least one programmable delay element corresponds to the at least one early arriving signal.

An example of a method includes detecting early arrival of at least one signal from a plurality of signals in response to a desired type of edge of a clock signal. The method also includes generating a control signal in response to detection of early arrival of the at least one signal. The method further includes delaying at least one input signal associated with the at least one signal based on the control signal. Moreover, the method includes outputting the plurality of signals if at least one of alignment of the plurality of signals and delaying of each input signal associated with each signal of the plurality of signals is detected.

In the accompanying figures, similar reference numerals may refer to identical or functionally similar elements. These reference numerals are used in the detailed description to illustrate various embodiments and to explain various aspects and advantages of the present disclosure.

FIG. 1 illustrates a circuit for aligning input signals, in accordance with one embodiment;

FIG. 2 is a timing diagram illustrating alignment of input signals, in accordance with one embodiment;

FIG. 3 illustrates a finite state machine, in accordance with one embodiment;

FIG. 4 illustrates a programmable delay element, in accordance with one embodiment; and

FIG. 5 is a flow diagram illustrating a method for aligning input signals, in accordance with one embodiment.

FIG. 1 illustrates a circuit 100 for aligning input signals. The circuit 100 can be included in a device under test (DUT) and can be coupled between input ports of the DUT and logic of the DUT.

It is noted that the circuit 100 can be used in various other application areas where it is desired to align the input signals and generate aligned signals. The circuit 100 can be external to a device that requires the aligned signals or can be embedded in the device that requires the aligned signals. The aligned signals can be defined as signals with minimal or no misalignment.

In one example, the DUT can be placed on an automated testing equipment (ATE) board. The circuit 100 can be present in the DUT or can be embedded in the ATE board to provide aligned signals to the logic of the DUT.

The circuit 100 includes a clock generating circuit 105 , hereinafter referred to as the clock circuit 105 . The clock circuit 105 can include an OR gate 106 and a NOT gate 108 with output terminal of the OR gate 106 being coupled to an input terminal of the NOT gate 108 .

It is noted that the clock circuit 105 can be implemented using combination of various other gates.

The circuit 100 also includes a first flip flop 110 A, hereinafter referred to as the flip flop 110 A, and a second flip flop 110 B, hereinafter referred to as the flip flop 110 B. Clock input terminals (CLK) of the flip flop 110 A and the flip flop 110 B are coupled to the output terminal of the OR gate 106 . The flip flop 110 A and the flip flop 110 B can be delay flip flops.

In some embodiments, the circuit 100 includes N such flip flops, for example the flip flop 110 A to a flip flop 110 N.

The circuit 100 also includes a finite state machine (FSM) 115 . The FSM 115 is coupled to the clock circuit 105 , the flip flop 110 A and the flip flop 110 B.

The circuit 100 further includes a first programmable delay element 120 A, hereinafter referred to as the delay element 120 A, and a second programmable delay element 120 B, hereinafter referred to as the delay element 120 B. The delay element 120 A and the delay element 120 B are coupled to the FSM 115 .

In some embodiments, the circuit 100 includes N such delay elements, for example the delay element 120 A to a delay element 120 N.

The circuit 100 can also include other delay elements, for example a delay element 125 A to a delay element 125 N. The other delay elements can be configured manually or can be used to add a finite delay. The other delay elements are hereinafter referred to as finite delay elements. Each such finite delay element is coupled to corresponding delay element. For example, the delay element 125 A is coupled to the delay element 120 A and the delay element 125 N is coupled to the delay element 120 N.

The circuit 100 can also include a plurality of gates, for example a first gate 130 A, hereinafter referred to as the gate 130 A, and a second gate 130 B, hereinafter referred to as the gate 130 B. The gate 130 A has input terminals coupled to the delay element 125 A and to the FSM 115 . The gate 130 B has input terminals coupled to the delay element 125 B and to the FSM 115 . The circuit 100 also includes a first multiplexer 135 A, hereinafter referred to as the multiplexer 135 A, and a second multiplexer 135 B, hereinafter referred to as the multiplexer 135 B. The multiplexer 135 A is coupled to the gate 130 A and the multiplexer 135 B is coupled to the gate 130 B.

In some embodiments, the circuit 100 includes N such gates, for example the gate 130 A to a gate 130 N.

In some embodiments, when the finite delay elements are not present the gates can be coupled to corresponding delay elements. For example, the gate 130 A can be coupled to the delay element 120 A and the gate 130 N can be coupled to the delay element 120 N.

Input signals, for example a signal 140 A and a signal 140 B can be received at respective input ports of the DUT. The signal 140 A and the signal 140 B can be misaligned with respect to each other. The working of the circuit 100 to align the input signals is explained as follows.

It is noted that the following description has been explained with respect to two input signals and can be applied for N number of input signals, where N is a natural number greater than 1.

A reset signal (RZ) can be used to reset or clear the flip flop 110 A and the flip flop 110 B. The OR gate 106 is responsive to a first signal 160 A and a second signal 160 B to generate a clock signal 145 . The first signal 160 A is obtained at output of the delay element 120 A and is also referred to as a first signal associated with the signal 140 A. Similarly, the second signal 160 B is obtained at output of the delay element 120 B and is also referred to as a second signal associated with the signal 140 B. Initially, when the input signals are received for first time then the first signal 160 A is similar to the signal 140 A and the second signal 160 B is similar to the signal 140 B. The flip flop 110 A is responsive to a first type of edge, for example a positive edge, of the clock signal 145 to output the first signal 160 A to the FSM 115 . Similarly, the flip flop 110 B is responsive to the first type of edge of the clock signal 145 to output the second signal 160 B to the FSM 115 .

The FSM 115 receives inverted version of the clock signal 145 . The inverted version of the clock provided to the FSM is hereinafter referred to as an FSM clock. The FSM 115 is responsive to a second type of edge, for example a negative edge, of the clock signal 145 to process and detect early arrival of one of the first signal 160 A and the second signal 160 B with respect to each other. The FSM 115 then generates control signals based on detection. For example, if early arrival of the first signal 160 A is detected as compared to the second signal 160 B, then the FSM 115 generates a first control signal 150 A, hereinafter referred to as the control signal 150 A, with at least one non zero bit. The control signal 150 A is indicative of delay to be added to the signal 140 A if early arrival of the first signal 160 A is detected. The control signal 150 A can be a combination of one or more bits. All zero bits in a control signal indicate no delay. Non-zero bits in the control signal are indicative of the delay.

Similarly, the FSM 115 generates a second control signal 150 B, hereinafter referred to as the control signal 150 B, based on the detection. If early arrival of the second signal 160 B is detected as compared to the first signal 160 A, then the control signal 150 B has at least one non zero bit. The control signal 150 B is indicative of delay to be added to the signal 140 B if early arrival of the second signal 160 B is detected.

The delay element 120 A delays the signal 140 A based on the control signal 150 A, if early arrival of the first signal 160 A is detected. If early arrival of the second signal 160 B is detected, the delay element 120 B delays the signal 140 B based on the control signal 150 B.

In some embodiments, a fixed delay (D 1 ) can also be added to the first signal 160 A by using the delay element 125 A. A delayed signal thus obtained can be referred to as the signal 160 A. The fixed delay (D 1 ) can be added to the first signal 160 A when the delay added to the signal 140 A is not sufficient to align the first signal 160 A with the second signal 160 B. The first signal 160 A can then be outputted as an output signal 155 A, hereinafter referred to as the signal 155 A. Similarly, another fixed delay (D 2 ) can be added to the second signal 160 B, using the delay element 125 B, when the delay added to the signal 140 B is not sufficient to align the second signal 160 B with the first signal 160 A. A delayed signal thus obtained can be referred to as the signal 160 B. The second signal 160 B can then be outputted as an output signal 155 B, hereinafter referred to as the signal 155 A.

The gate 130 A can output the signal 155 A in response to an enable signal (EN). The enable signal is generated by the FSM 115 when the input signals are aligned or when each signal of the input signals has been delayed at least once. Similarly, the gate 130 B outputs the signal 155 B in response to the enable signal.

A delay flag, present in the FSM 115 , can be associated with each input signal and is indicative of whether each signal of the input signals has been delayed at least once. For example, one delay flag can be associated with the signal 140 A and another delay flag can be associated with the signal 140 B. If the delay flag associated with the signal 140 A is LOW then the signal 140 A is considered as not delayed. Similarly, if the delay flag associated with the signal 140 B is LOW then the signal 140 B is considered as not delayed. If all the delay flags are asserted HIGH then the input signals are considered to be aligned. The delay flags can be maintained using counters as explained in conjunction with FIG. 3 .

The input signals can be aligned in one or more clock cycles. A clock cycle, generated from the clock circuit 105 , can be defined as a period required to determine if the input signals are aligned or misaligned. The alignment can happen in any clock cycle.

The FSM 115 also generates a run signal (RN) when the FSM 115 starts operating. The run signal indicates that alignment of the input signals has started. The run signal is asserted HIGH when any of the input signals arrive early.

The multiplexer 135 A can be used to select one of the first signal 160 A or the signal 140 A as the output signal 155 A. Similarly, the multiplexer 135 B can be used to select one of the second signal 160 B or the signal 140 B as the output signal 155 B. A bypass signal (BP) can be used to selectively output the input signals as output signals using multiplexers. The multiplexer 135 A can be used to selectively output the signal 140 A as the output signal 155 A, if there is no delay added to the signal 140 A. Similarly, the multiplexer 135 B can be used to selectively output the signal 140 B as the output signal 155 B, if there is no delay added to the signal 140 B.

FIG. 2 is a timing diagram illustrating alignment of the input signals, for example the signal 140 A, the signal 140 B, a third signal 140 C, hereinafter referred to as the signal 140 C, and a fourth signal 140 D, hereinafter referred to as the signal 140 D. The reset signal (RZ) is asserted HIGH in order to reset the flip flops associated with the input signals. For example, the reset signal resets the flip flop 110 A associated with the signal 140 A.

In illustrated example, initially, the signal 140 A is at logic level HIGH and hence the first signal 160 A is sampled HIGH. Also, the signal 140 B, the signal 140 C, and the signal 140 D are at logic level LOW and hence the second signal 160 B, a third signal 160 C, and a fourth signal 160 D, are sampled LOW. Since the first signal 160 A is sampled HIGH, the clock signal 145 is also at logic level HIGH indicating sampling of at least one signal, for example the first signal 160 A as HIGH. A flip flop, for example the flip flop 110 A, that samples the first signal 160 A as HIGH then outputs logic 1 of the first signal 160 A to an FSM, for example the FSM 115 . Similarly, the second signal 160 B, the third signal 160 C, and the fourth signal 160 D, outputs logic 0 to the FSM 115 .

The FSM 115 detects early arrival of the signal 140 A with respect to the signal 140 B, the signal 140 C, and the signal 140 D. The run signal (RN) is asserted HIGH as the FSM 115 starts operation. A first delay flag can be associated with the signal 140 A, a second delay flag can be associated with the signal 140 B, a third delay flag can be associated with the signal 140 C, and a fourth delay flag can be associated with the signal 140 D. Initially, the first delay flag, the second delay flag, the third delay flag, and the fourth delay flag are LOW. Since the signal 140 A arrives early and needs to be delayed after the first clock cycle, the first delay flag is asserted HIGH and other delay flags remain LOW. The FSM 115 then generates a plurality of control signals corresponding to the input signals. For example, the control signal 150 A is generated for the signal 140 A and the control signal 150 B is generated for the signal 140 B. As the first signal 160 A is sampled HIGH, the control signal 150 A has at least one non-zero bit indicating the delay to be added to the signal 140 A. Other control signals, for example the control signal 150 B, a third control signal 150 C, hereinafter referred to as the control signal 150 C, and a fourth control signal 150 D, hereinafter referred to as the control signal 150 D, are generated without any change in the bits. The delay element 120 A then delays the signal 140 A, which initially is similar to the first signal 160 A before addition of the delay. The first signal 160 A is hence aligned with the second signal 160 B at an instant 205 . The first signal 160 A and the second signal 160 B can be aligned in one or more clock cycles that are generated from the circuit 105 . The alignment can happen in any clock cycle. As illustrated in FIG. 2 , the first signal 160 A and the second signal 160 B are aligned in a second clock cycle.

After the second clock cycle, the FSM 115 now detects that the first signal 160 A and the second signal 160 B are sampled HIGH due to early arrival as compared to the third signal 160 C and the fourth signal 160 D. Since the signal 140 A and the signal 140 B needs to be delayed, the first delay flag and the second delay flag are asserted HIGH. The FSM 115 then generates the control signals for the input signals. The bits in the control signal 150 A and the control signal 150 B are incremented in order to delay the signal 140 A and the signal 140 B. At instant 210 , the first signal 160 A and the second signal 160 B are then aligned with respect to the third signal 160 C. The alignment can be performed in one or more cycles. As illustrated, the first signal 160 A, the second signal 160 B, and the third signal 160 C are aligned in a third clock cycle. The FSM 115 now detects early arrival of the first signal 160 A, the second signal 160 B, and the third signal 160 C as compared to the fourth signal 160 D. Since the signal 140 A, the signal 140 B, and the signal 140 C needs to be delayed, the first delay flag, the second delay flag, and the third delay flag are asserted HIGH. The FSM 115 then generates the control signals to delay the signal 140 A, the signal 140 B, and the signal 140 C, by incrementing the bits in respective control signals. The first signal 160 A, the second signal 160 B, and the third signal 160 C are then aligned with respect to the fourth signal 160 D at instant 215 . As illustrated, the first signal 160 A, the second signal 160 B, the third signal 160 C, and the fourth signal 160 D are aligned in a fourth clock cycle. The fourth delay flag is also asserted HIGH at end of the fourth clock cycle as the input signals are now aligned with each other. When the input signals are aligned with respect to each other, the enable signal (EN) is asserted HIGH.

Referring now to FIG. 3 , the FSM 115 includes a set of registers, a decision unit, and a generating unit 305 .

The set of registers include a first register 310 A, hereinafter referred to as the register 310 A, and a second register 310 B, hereinafter referred to as the register 310 B. The register 310 A and the register 310 B are delay flip flops. A third multiplexer 315 A, hereinafter referred to as the multiplexer 315 A, is coupled to the register 310 A and has one input terminal that receives the first signal 160 A. A fourth multiplexer 315 B, hereinafter referred to as the multiplexer 315 B, is coupled to the register 310 B and has one input terminal that receives the second signal 160 B.

The decision unit includes a first AND gate 320 A, hereinafter referred to as the AND gate 320 A, a second AND gate 320 B, hereinafter referred to as the AND gate 320 B, and an OR gate 325 . The AND gate 320 A has input terminals that receive the first signal 160 A and the second signal 160 B. The AND gate 320 B has one input terminal coupled to the register 310 A and to another input terminal of the multiplexer 315 A. Another input terminal of the AND gate 320 B is coupled to the register 310 B and to another input terminal of the multiplexer 315 B. The OR gate 325 has input terminals coupled to the AND gate 320 A and the AND gate 320 B. A third AND gate 330 A, hereinafter referred to as the AND gate 330 A, is coupled to the multiplexer 315 A and has input terminals that receive the first signal 160 A and an inverted version of the enable signal (EN). A fourth AND gate 330 B, hereinafter referred to as the AND gate 330 B, is coupled to the multiplexer 315 B and has input terminals that receive the second signal 160 B and an inverted version of the enable signal (EN).

The generating unit 305 includes a fifth AND gate 335 A, hereinafter referred to as the AND gate 335 A, a counter 340 A, a fifth multiplexer 345 A, hereinafter referred to as the multiplexer 345 A, and an incrementer 350 A. The AND gate 335 A has input terminals that receive the first signal 160 A and an inverted version of the enable signal (EN). The counter 340 A can include the delay flag associated with the signal 140 A. The incrementer 350 A is coupled between one input terminal of the multiplexer 345 A and the control signal 150 A from the counter 340 A. The multiplexer 345 A is coupled to the AND gate 335 A and the counter 340 A, and has another input terminal that receives the control signal 150 A. The generating unit 305 also includes a sixth AND gate 335 B, hereinafter referred to as the AND gate 335 B, a counter 340 B, a sixth multiplexer 345 B, hereinafter referred to as the multiplexer 345 B, and an incrementer 350 B. The AND gate 335 B has input terminals that receive the second signal 160 B and an inverted version of the enable signal (EN). The counter 340 B can include the delay flag associated with the signal 140 B. The incrementer 350 B is coupled between one input terminal of the multiplexer 345 B and the control signal 150 B from the counter 340 B. The multiplexer 345 B is coupled to the AND gate 335 B and the counter 340 B, and has another input terminal that receives the control signal 150 B.

In some embodiments, the decision unit includes another gate, for example an OR gate 355 , having input terminals coupled to the register 310 A and the register 310 B.

The register 310 A and the register 310 B are reset using the reset signal (RZ). If the first signal 160 A arrives earlier than the second signal 160 B, the first signal 160 A is at logic 1 as compared to logic 0 of the second signal 160 B. As the enable signal (EN) is at logic 0, the AND gate 330 A outputs a logic 1. The multiplexer 315 A hence selects the first signal 160 A and logic 1 of the first signal 160 A is reflected at input of the register 310 A. At a positive edge of the FSM clock, the register 310 A outputs logic 1. Similarly, the AND gate 330 B outputs a logic 0. The multiplexer 315 B hence selects an output of the register 310 B that is stored previously. Logic 0 is received at input of the register 310 B which is output at a positive edge of the FSM clock. The AND gate 320 B performs a logical AND operation of the first signal 160 A at logic 1 and the enable signal at logic 0 to provide a logic 0 to the OR gate 325 . The AND gate 320 A performs a logical AND operation of the first signal 160 A and the second signal 160 B to provide a logic 0 to the OR gate 325 . The OR gate 325 hence generates EN=0 which indicates that the first signal 160 A and the second signal 160 B are not aligned with respect to each other. Hence the early arriving signal, the first signal 160 A, needs to be delayed using the control signal 150 A generated by the generation unit 305 . The AND gate 335 A generates a logic 1 based on values of the enable signal and the first signal 160 A. The multiplexer 345 A then outputs value of the incrementer 350 A to the counter 340 A. The incrementer 350 A generates the value by adding a binary 1 to an input stream. The input stream can be a combination of one or more bits. The counter 340 A can assert the delay flag associated with the signal 140 A as HIGH and further outputs the control signal 150 A at a positive edge of the FSM clock in order to delay the signal 140 A. The control signal 150 B does not add any delay to the delay element 120 B as the AND gate 335 B outputs a logic 0.

The delay element 120 A adds the delay to the signal 140 A and the FSM 115 again detects if the first signal 160 A is aligned with respect to the second signal 160 B. If the signals are aligned or if delay has been added, the enable signal is asserted HIGH and EN=1.

In some embodiments, the OR gate 355 generates a run signal (RN) to indicate that the FSM 115 is in operation. The run signal is asserted HIGH and RN=1 when either the first signal 160 A or the second signal 160 B is sampled HIGH.

FIG. 4 illustrates a programmable delay element, for example the delay element 120 A. The delay element 120 A includes one or more delay units, for example a delay unit 425 A to a delay unit 425 N. The delay unit 425 A includes a first transistor 405 A 1 , hereinafter referred to as the transistor 405 A 1 , a second transistor 405 B 1 , hereinafter referred to as the transistor 405 B 1 , a first switch 410 A 1 , hereinafter referred to as the switch 410 A 1 , a second switch 410 B 1 , hereinafter referred to as the switch 410 B 1 , a third switch 410 C 1 , hereinafter referred to as the switch 410 C 1 , and a load 415 A 1 . The transistor 405 A 1 has a drain coupled to a drain of the transistor 405 B 1 . The transistor 405 B 1 has a gate coupled to a gate of the transistor 405 A 1 . The switch 410 A 1 has a source coupled to a power supply (VDD) and a drain coupled to a source of the transistor 405 A 1 . The switch 410 B 1 has a source coupled to a ground supply (GND) and a drain coupled to a source of the transistor 405 B 1 . The switch 410 A 1 and the switch 410 B 1 have gates that receive the control signal 150 A. The load 415 A 1 has a gate coupled to the drain of the transistor 405 A 1 and to the drain of the transistor 405 B 1 , and a source coupled to a drain of the load 415 A 1 . The load 415 A 1 includes a transistor. The switch 410 C 1 has a drain coupled to the source and the drain of the load 415 A 1 , a source coupled to the ground supply (GND), and a gate that receives the control signal 150 A. The delay element 120 A further includes an inverter 420 having one terminal coupled to the gate of the load 415 A 1 .

The transistor 405 A 1 and the transistor 405 B 1 together invert the signal 140 A. The switch 410 A 1 , the switch 410 B 1 , and the switch 410 C 1 are responsive to the control signal 150 A that corresponds to the delay element 120 A. The switch 410 A 1 controls the transistor 405 A 1 , the switch 410 B 1 controls the transistor 405 B 1 , and the switch 410 C 1 controls the load 415 A 1 , to delay the signal 140 A corresponding to the delay element 120 A. The load 415 A 1 acts as a capacitor and stores the signal 140 A which is inverted. The load 415 A 1 also increases delay range of the delay element 120 A to align the signal 140 A with other input signals. The inverter 420 inverts the signal 140 A before outputting.

In some embodiments, the delay element 120 A includes N such transistors, N such switches, and N such loads. For example, from the transistor 405 A 1 to a transistor 405 AN, from the transistor 405 B 1 to a transistor 405 BN, from the switch 410 A 1 to a switch 410 AN, from the switch 410 B 1 to a switch 410 BN, from the switch 410 C 1 to a switch 410 CN, from the load 415 A 1 to a load 415 AN.

Structure and functioning of other delay units are similar to that of the delay unit 425 A.

In some embodiments, the transistor 405 A 1 and the transistor 405 B 1 together constitute a complementary metal oxide semiconductor (CMOS) inverter. The transistor 405 A 1 and the switch 410 A 1 can be positive metal oxide semiconductor (PMOS) type transistors. The transistor 405 B 1 , the switch 410 B 1 , the load 415 A 1 , and the switch 410 C 1 can be negative metal oxide semiconductor (NMOS) type transistors.

It is noted that various other implementations of the delay element 120 A can be used for generating delay.

FIG. 5 is a flow diagram illustrating a method for aligning input signals. The aligning can be performed using an aligning circuit, for example the circuit 100 . The circuit 100 can be coupled between input ports of a device under test (DUT) and a logic of the DUT.

At step 505 , early arrival of at least one signal from a plurality of signals or the input signals is detected in response to a desired type of edge, for example a negative edge, of a clock signal, for example the clock signal 145 . The early arrival of the at least one signal is detected by sampling the signals using flip flops, for example the flip flop 110 A to the flip flop 110 N. One or more signals that are sampled HIGH are then detected as early arriving signals and can be referred to as the at least one signal. The detection can be performed by a finite state machine (FSM), for example the FSM 115 . The early arrival of the at least one signal indicates that the signals are misaligned with respect to each other.

The clock signal can be generated by performing a logical OR operation of the signals using a clock generating circuit, for example a clock circuit 105 .

At step 510 , a control signal is generated in response to detection of early arrival of the at least one signal. In one example, if the first signal 160 A arrives early, the control signal 150 A is generated by the FSM 115 to delay the signal 140 A. The control signal can be a combination of one or more control signals. One control signal can be generated corresponding to one input signal and can be used to delay respective input signal. Each control signal indicates the delay that needs to be added to respective input signal. In case no delay is to be added to an input signal, then the control signal corresponding to that input signal has all zero bits.

At step 515 , at least one input signal associated with the at least one signal is delayed based on the control signal. Several input signals can be delayed based on their respective control signals. The at least one input signal can be delayed using a programmable delay element, for example the delay element 120 A.

In some embodiments, a delay flag associated with the at least one input signal is asserted HIGH after delaying the at least one input signal. One or more input signals are considered to be aligned if delay flags associated with the input signals are asserted HIGH.

In some embodiments, a fixed delay can be added to further delay the at least one signal.

At step 520 , the signals are outputted if alignment of the signals is detected or if each input signal, associated with each signal of the signals, being delayed is detected. Once the signals are delayed, there can still be minimal misalignment with respect to other signals. In such a case, condition of alignment of the signals is not satisfied and the signals can only be outputted if condition of addition of the delay has been detected in each signal. In one embodiment, a logical AND operation of the signals can be performed to detect alignment of the signals. In another embodiment, a logical AND operation of outputs of a set of registers can be performed to detect delaying of each input signal associated with each signal of the signals. One register of the set of registers corresponds to one signal of the signals and enables detection of early arrival of one of the first signal and the second signal.

By using the aligning circuit, misaligned input signals received at the input ports of the DUT can be aligned before transmission to the logic of the DUT. Since the delay is added automatically by the aligning circuit, manual correction can be eliminated. Also, since the aligning circuit can be placed just before the logic of the DUT it can be ensured that minimal misalignment is present in signals received by the logic.

In the foregoing discussion, the term “coupled” refers to either a direct electrical connection between the devices connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, that are connected together to provide a desired function. The term “signal” means at least one current, voltage, charge, data, or other signal.

The foregoing description sets forth numerous specific details to convey a thorough understanding of embodiments of the disclosure. However, it will be apparent to one skilled in the art that embodiments of the disclosure may be practiced without these specific details. Some well-known features are not described in detail in order to avoid obscuring the disclosure. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of disclosure not be limited by this Detailed Description, but only by the Claims.