Auto leveling receiver

The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of contract No. FA8650-05-C-7214 awarded by the U.S. Air Force.

The invention relates to RF communications and more specifically to an apparatus for controlling the amplification of an analog signal in the front end of a digital receiver and a method of use in RF equipment.

RF communication equipment generally employ amplifiers to increase analog signal levels before being digitally processed. This helps to distinguish weak signals from noise. Too much amplification, however, can adversely affect the receiver. For example, unnecessarily amplifying a strong signal may induce distortion, and possibly overload or damage certain components (e.g. saturating analog-to-digital converters (ADCs)) of a digital receiver.

According to the present invention, there is provided an auto leveling circuit suitable for use in an RF receiver. The auto leveling circuit comprises a plurality of automatic gain control (AGC) circuits each being an amplifier stage to amplify an RF signal according to at least two incrementally discrete levels. In order to control the amplification level, the AGC circuit further comprises peak detectors to detect the amplitude of the amplified RF signal and comparators to compare the amplitude of the RF signal with a threshold value indicative of a saturation point of the amplifiers.

In an embodiment, a plurality of AGC circuits are ganged together in series. Each AGC circuit provides two or more discrete levels with which to incrementally increase or decrease the level of the RF signal in discrete gain steps. When AGC acts as an attenuator, the gain levels are suppressed when they approach a saturation region of operation and the gain decreases by a discrete step. Alternatively, when AGC acts as an amplifier, a subsequent gain level is engaged when the previous gain level enters a margin before its saturation region, thereby increasing the output signal by a discrete step. This process continues in successive AGC stages, until the desired signal strength is achieved.

In another embodiment, a method of detecting an RF signal is disclosed. An RF signal is received from an antenna (or other source) at an input of an AGC having two or more incrementally discrete gain levels. The AGC determines the peak amplitude of the RF signal and compares it with a reference. If the peak amplitude of the RF signal is greater than the reference, the gain of the respective discrete gain level is suppressed and the subsequent gain level is decreased by a discrete step. The method disclosed provides an amplified RF output signal with constant phase relationship to the RF input signal across all gain settings.

These and other aspects, features, and advantages of the invention will become apparent upon review of the following description taken in connection with the accompanying drawings. The invention, though, is pointed out with particularity by the appended claims.

FIG. 1 is a system block diagram of a portion of a signal processing system in accordance with the present invention;

FIG. 2 is a schematic diagram of an automatic leveling circuit in accordance with the present invention;

FIG. 3 is circuit diagram of a portion of an automatic leveling circuit detailing an automatic gain control feature of the present invention;

FIG. 4 is a circuit diagram of an exemplary variable gain amplifier in accordance with the present invention;

FIG. 5 illustrates phase linearity of an amplified output signal across several amplitude levels of the auto leveling circuit of the present invention; and

FIG. 6 shows the output signal of the auto leveling circuit being increased in discrete gain steps.

In FIG. 1 , an automatic leveling circuit (ALC) 3 operable in an analog portion or front end of a digital receiver quickly senses signal strength at an antenna 7 input over a large dynamic frequency range and adjusts signal strength to an optimal level for digital processing. Automatic scaling or leveling employed by the present invention also speeds up digital processing of the received RF analog signal in an analog-to-digital converter (ADC) 2 by reducing the number of bits the ADC 2 requires to process the signal, while maintaining the accuracy in the conversion process. Any communication device such as an RF transmitter-receiver of a mobile phone, a personal communications service (PCS) phone, a wireless local area network (LAN) transmitter-receiver, etc may incorporate the ALC 3 .

Still referring to FIG. 1 , receiver 1 , in accordance with an embodiment of the invention, includes a low noise amplifier (LNA) and filter 6 to receive an incoming RF signal from an antenna 7 and to provide an initial amplified RF signal. Mixer 5 converts the amplified RF signal to an intermediate frequency (IF) signal before filter 4 removes unwanted components of the intermediate signal. Automatic leveling circuit 3 amplifies the intermediate signal to an optimum level for signal processing by ADC 2 . One skilled in the art will recognize that the above is only a small part of a device and that there are a multitude of signal processing functions possible depending upon the specific use of the receiver 1 .

FIG. 2 illustrates details of an exemplary ALC 3 where an automatic gain control (AGC) circuit 100 , in order to desirably scale the analog RF signal, amplifies signal in accordance with one or more predetermined discrete gain settings. AGC 100 includes a variable gain amplifier (VGA) 200 to amplify the analog RF signal by one or more predetermined discrete gain steps. Peak detector 300 (abbreviated PK Detector in FIG. 2 ) detects the amplitude of the analog signal and provides its output to a comparator 400 (abbreviated CMP in FIG. 2 ). Comparator 400 compares peak voltage of the analog signal with a threshold value indicative of a pre-saturation point for VGA 200 . Since, comparator 400 generates a digital output indicative of a “0” or “1” digit, VGA 200 knows whether its output is saturated by receipt of a digital representation of a discrete yes/no or on/off signal representation. In the illustFative embodiment, receiver 1 is implemented as an integrated circuit in a fully differential cascaded architecture that provides immunity to noise from digital circuitry of the receiver 1 .

Exemplary ALC 3 comprises three AGCs 100 a , 100 b , and 100 c wherein each AGC provides a respective amplifier stage, 31 , 32 , and 33 . First amplifier stage 31 provides three discrete gain levels and two adjustable on/off steps. Second amplifier stage 32 provides three discrete gain levels and two adjustable on/off steps. Since the output of second amplifier stage 32 is large, only two discrete gain levels and one adjustable on/off step are provided in third amplifier stage 33 . Final stage 34 buffers the output power of the output signal for receipt by A/D 2 .

FIG. 3 exemplifies a circuit diagram having two AGCs 100 a , 100 b ganged together and representing first two amplifier stages 31 and 32 . VGA 200 has a differential RF input 102 a , 102 b and a differential RF output 104 a , 104 b and a differential control node 106 a , 106 b . VGA's 200 differential output node 104 a , 104 b is coupled to differential input 301 a , 301 b of peak detector 300 a , 300 b . At this point, the differential signals on differential output 104 a , 104 b are separated into two discrete levels 31 a and 31 b.

Differential output signals of VGA 200 are received by peak detector 300 a , 300 b , each of which outputs a signal representative of the peak voltage amplitude of the output signal of VGA 200 . The peak voltage amplitude at each discrete level 31 a , 31 b is compared to respective first and second reference voltages applied at nodes 305 and 306 , respectively, which values indicate the maximum linear output for VGA 200 at that respective discrete level 31 a , 31 b . As the RF output signal of VGA 200 approaches its saturation point, comparators 400 a , 400 b send a signal to nodes 106 a , 106 b of VGA 200 to suppress the gain. One skilled in the art will recognize that the above is only one way to attenuate gain in response to VGA saturation and that there are a multitude of circuit arrangements that may be used depending upon the design requirements.

In one embodiment of the invention, a plurality of AGCs 100 are ganged together in series to create a plurality of amplifier stages 31 , 32 , and 33 , respectively. A circuit designer, however, may combine any number of AGCs to amplify the output signal to any desired level. Such an arrangement advantageously allows automatic leveling circuit 3 to sense the strength of the output signal and increases it by predetermined discrete amounts until obtaining a desired output signal strength.

FIG. 6 shows the output of the automatic leveling circuit having five discrete gain levels, representative of gain stages 31 and 32 each having two discrete levels, 31 a , 31 b , 32 a , and 32 b , respectively, and amplifier stage 33 having one discrete level 33 a . Discrete gain levels 31 a , 31 b , 32 a , 32 b , and 33 a increase the output by incremental amounts until obtaining the desired output signal strength.

FIG. 6 also illustrates attenuation of the output in response to VGA approaching saturation. The brief voltage spike 30 illustrates the ALR adjusting the gain when multiple gain stages of VGAs 200 saturate. After reducing or terminating the gain of VGAs 200 in response to the signal spike 30 , the output signal level is increased by the predetermined discrete levels 31 a , 31 b , 32 a , 32 b , and 33 a until attaining the desired signal strength.

VGA 200 in AGC 100 makes possible the amplification of the output signal in discrete, fast, predetermined gain steps.

FIG. 4 shows an embodiment of VGA 200 with three discrete gain levels controlled by bias sources 206 , 208 , and 210 , with bias sources 206 and 208 having adjustable on/off steps. As illustrated, VGA circuit 200 receives a digital input at control nodes 106 a , 106 b . The digital input controls two of three discrete bias sources 206 and 208 of VGA, 200 which results in discrete gain states. The output signal of VGA 200 may suffer amplitude attenuatation and phase distortion as the VGA 200 approaches saturation; however, suppressing one or both control nodes 106 a , 106 b mitigates this effect by reducing the output by one or more predetermined discrete gain steps.

Alternatively, VGA 200 may work as an amplifier by incrementally increasing the output signal by predetermined discrete gain steps. When there is sufficient headroom available for the output signal to be amplified, differential transistor pair 212 is turned on to increase the output signal by a predetermined discrete gain step. If there is still sufficient headroom available for the output signal to be amplified again, differential transistor pair 213 can be switched on to increase the output signal by another predetermined discrete gain step. At this point, the output is at the desired level. Alternatively, if more gain is required, the circuit designer may gang together additional VGAs 200 .

VGA 200 has three discrete gain levels controlled by bias sources 206 , 208 , and 210 , with bias sources 206 and 208 having adjustable on/off steps. The three discrete gain levels each comprises a differential transistor pair, where differential transistor pair 211 is always on and differential transistor pairs 212 and 213 can be turned off. Differential transistor pairs 212 and 213 are turned on and off by their respective bias source 206 and 208 . The gain settings for differential transistor pairs 211 , 212 , and 213 are primarily determined by the ratio of the emitter resistors to the collector resistors R 1 La/R 0 , R 1 La/R 1 , and R 1 La/R 2 , respectively, when the differential transistor pairs 212 , and 213 are biased on. The gain steps occur when the transconductance of the adjustable gain stages, comprising differential transistor pairs 212 , and 213 , is suppressed by turning off their respective bias source 206 , 208 . Because the circuit designer may control the value of the ratio of the emitter resistors to the collector resistors the output signal of AGC 100 is adjustable by predetermined discrete gain steps. One skilled in the art will recognize that the above description of VGA 200 is only one embodiment and any number of gain stages could be provided to meet the designers needs.

In an alternative embodiment, the VGA may comprise any other type of transistor arrangement, such as FET, MOS, CMOS, Bi-CMOS, HBY, MES-FET, or HEMT type transistors, so long as the desired effect is obtained.

The present invention is further operable as a method for operating an RF radio. In FIG. 3 , AGC 100 receives an input RF signal and provides an amplified output RF signal. The peak voltage amplitude of the output signal is determined by peak detectors 300 a , 300 b and compared to a reference value 305 and 306 , which reference value is indicative of the saturation point of VGA 200 . If the peak amplitude of the output signal is less than the saturation point, VGA 200 will amplify the output signal by another predetermined discrete value and continue to do so, until obtaining the desired signal strength for the output signal. Alternatively, if the output signal is greater than the reference, VGA 200 will shut off the gain.

The arrangement provided within in the illustrated RF circuitry creates an auto-leveling receiver 1 that increases the analog signal in the analog portion of the receiver 1 by discrete predetermined gain steps until achieving the desired signal strength. Because the gain in each stage 31 , 32 , and 33 is known, it is possible for ADC 2 to receive information about the input RF signal before ADC 2 processes the output from the automatic leveling circuit 3 . Accordingly, ADC 2 digitally processes the RF signal by sampling fewer bits and without losing information contained in the signal.

The time required for auto-leveling receiver 1 to optimize the signal level is a function of VGAs 200 ability to rapidly adjust its gain. The faster VGA 200 can adjust its gain the faster auto-leveling receiver 1 can converge on the desired signal level. The transition between gain steps in VGAs 200 occurs rapidly. In the illustrative embodiment, the transition occurs in approximately one nanosecond. Operating VGAs 200 gain stages out of saturation maintains a constant phase relationships across all gain settings. This is crucial for signal processing systems where the phase of the signal carries the information. FIG. 5 illustrates linearity in phase of the output signal across all gain settings as the input signal level is swept across a 55 dB dynamic range, advantageously showing a constant phase relationship across all amplitude levels 51 , 52 , and 53 .

While the present invention has been particularly shown and described with reference to exemplary embodiments, it should be understood by those of skill in the art that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by appended claims and their equivalents.