Operational amplifier

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-138218, filed on Jun. 9, 2009, the entire contents of which are incorporated herein by reference.

The embodiment discussed herein relates to an operational amplifier.

FIG. 4 is a circuit diagram illustrating an operational amplifier according to the related art (for example, see Japanese Patent Application Laid-Open Publication No. 11-154832).

As illustrated in FIG. 4 , transistors Tr 1 and Tr 2 make up a current mirror circuit. The transistor Tr 2 provided on the output side of the current mirror circuit operates as a constant current source. That is, the transistor Tr 2 passes a drain current that has substantially the same value as the value of a current that flows through a first current source 1 .

The drain of the transistor Tr 2 is coupled to the sources of transistors Tr 3 and Tr 4 . The drain of the transistor Tr 3 is coupled to the drain of a transistor Tr 5 , the gate of the transistor Tr 5 , and the gate of a transistor Tr 6 . The source of the transistor Tr 5 is coupled to a ground GND. The drain of the transistor Tr 4 is coupled to the drain of the transistor Tr 6 . The source of the transistor Tr 6 is coupled to the ground GND. An input signal VM is applied to the gate of the transistor Tr 3 . An input signal VP is applied to the gate of the transistor Tr 4 . The transistors Tr 2 to Tr 6 are included in a differential input circuit activated based on the constant current supplied from the transistor Tr 2 .

A coupling point of the drains of the transistors Tr 3 and Tr 5 , that is, a node N 1 , is coupled to the gate of a transistor Tr 11 . A coupling point of the drains of the transistors Tr 4 and Tr 6 , that is, a node N 2 , is coupled to the gate of a transistor Tr 12 . The sources of the transistors Tr 11 and Tr 12 are coupled to the ground GND through a second current source 2 .

The drain of the transistor Tr 11 is coupled to the drain of a transistor Tr 13 . The source of the transistor Tr 13 is coupled to a power source Vcc. The drain of the transistor Trig is coupled to the drain of a transistor Tr 14 , and the gates of the transistors Tr 13 and Tr 14 . The source of the transistor Tr 14 is coupled to the power source Vcc. The transistors Tr 11 to Tr 14 and the second current source 2 are included in a differential amplifier circuit that amplifies a differential voltage between the node N 1 and the node N 2 .

A coupling point of the drains of the transistors Tr 11 and Tr 13 , that is, a node N 3 , is coupled to the gate of an output transistor Tr 21 . The source of the transistor Tr 21 is coupled to the power source Vcc. The drain of the transistor Tr 21 is coupled to an output terminal To.

The node N 2 is coupled to the gate of an output transistor Tr 22 . The drain of the transistor Tr 22 is coupled to the output terminal To, and the source of the transistor Tr 22 is coupled to the ground GND. An output signal Vout is applied to the gate of the transistor Tr 3 as the input signal VM.

For example, when the voltage value of the input signal VP becomes higher than the voltage value of the input signal VM (the output signal Vout), the value of the drain current of the transistor Tr 4 decreases and becomes lower than the value of the drain current of the transistor Tr 3 . As a result, the voltage level of the node N 2 falls and the transistor Tr 22 is turned off.

When the potential of the node N 2 becomes lower than the potential of the node N 1 , the potential of the node N 3 decreases based on an operation of the differential amplifier circuit. When the potential of the node N 3 decreases, the output transistor Tr 21 is turned on and the voltage level of the output signal Vout rises. As a result, the voltage values of the input signal VP and the output signal Vout (the input signal VM) become substantially the same.

As the potential of the node N 3 decreases, the drain current supplied from the transistor Tr 21 to the transistor Tr 22 increases. When the drain current of the transistor Tr 22 increases, the value of a voltage between the gate and the source (hereinafter referred to as a “gate-source voltage”) of the transistor Tr 22 increases. As a result, the potential of the node N 2 increases. The potentials of the nodes N 1 and N 2 become substantially the same by controlling the drain current of the transistor Tr 21 based on the differential voltage between the nodes N 1 and N 2 . When the potentials of the nodes N 1 and N 2 are substantially the same, the drain voltages of the transistors Tr 3 and Tr 4 are substantially the same. Accordingly, a voltage between the source and the drain (hereinafter referred to as the “source-drain voltage”) of the transistor Tr 3 and the source-drain voltage of the transistor Tr 4 become substantially the same, and the drain currents of the transistor Tr 3 and Tr 4 become substantially the same. As a result, the gate-source voltages of the transistors Tr 3 and Tr 4 may be substantially the same, and generation of an offset voltage of the input signal VP and the output signal Vout may be reduced if not prevented.

According to an aspect of an embodiment, an operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

FIG. 1 is a circuit diagram illustrating an example of an operational amplifier according to an embodiment;

FIG. 2 is a circuit diagram illustrating another example of the operational amplifier according to the embodiment;

FIG. 3 is a circuit diagram illustrating another example of the operational amplifier according to the embodiment; and

FIG. 4 is a circuit diagram illustrating an operational amplifier according to the related art.

FIG. 1 is a circuit diagram illustrating an example of an operational amplifier according to an embodiment.

As illustrated in FIG. 1 , the operational amplifier includes a current source 1 , a first differential amplifier circuit 10 , a second differential amplifier circuit 20 , and an output stage circuit 30 . The current source 1 supplies a constant current I 1 to a transistor Tr 1 . The transistor Tr 1 is coupled to a transistor Tr 2 , and the transistors Tr 1 and Tr 2 make up a current mirror circuit. The transistors Tr 1 and Tr 2 are P-channel metal oxide semiconductor (PMOS) transistors for example. The drain of the transistor Tr 1 is coupled to the gates of the transistors Tr 1 and Tr 2 . The sources of the transistors Tr 1 and Tr 2 are coupled to a power source Vcc. The electrical characteristics of the transistor Tr 2 provided on the output side are substantially the same as the electrical characteristics of the transistor Tr 1 provided on the input side. Accordingly, the transistor Tr 2 on the output side operates as a constant current source and passes a current I 2 that has substantially the same value as the value of the constant current I 1 that flows through the transistor Tr 1 on the input side.

The first differential amplifier circuit 10 includes the transistor Tr 2 that operates as the constant current source, a differential pair 11 , and a current mirror circuit 12 . The differential pair 11 includes a transistor Tr 3 and a transistor Tr 4 . The transistors Tr 3 and Tr 4 are PMOS transistors for example. The gate of the transistor Tr 3 is coupled to an inverting input terminal T 1 to which an input signal VM is applied. The gate of the transistor Tr 4 is coupled to a non-inverting input terminal T 2 to which an input signal VP is applied. The sources of the transistors Tr 3 and Tr 4 are coupled to the drain of the transistor Tr 2 . The drain of the transistor Tr 3 is coupled to the drain of a transistor Tr 5 in the current mirror circuit 12 . The drain of the transistor Tr 4 is coupled to the drain of a transistor Tr 6 in the current mirror circuit 12 . The transistors Tr 5 and Tr 6 are N-channel metal oxide semiconductor (NMOS) transistors for example.

The current mirror circuit 12 includes the transistors Tr 5 and Tr 6 , and transistors Tr 7 and Tr 8 . The transistors Tr 7 and Tr 8 are NMOS transistors for example. The transistors Tr 5 and Tr 7 are provided on the input side of the current mirror circuit 12 , and the transistors Tr 6 and Tr 8 are provided on the output side of the current mirror circuit 12 . The drain of the transistor Tr 5 is coupled to the gates of the transistors Tr 5 to Tr 8 . The source of the transistor Tr 5 is coupled to the drain of the transistor Tr 7 . The source of the transistor Tr 7 is coupled to a ground GND (a low potential power source). Thus, the transistors Tr 5 and Tr 7 are coupled in series.

The source of the transistor Tr 6 is coupled to the drain of the transistor Tr 8 , and the source of the transistor Tr 8 is coupled to the ground GND. Similar to the transistors Tr 5 and Tr 7 , the transistors Tr 6 and Tr 8 are coupled in series. The electrical characteristics of the transistor Tr 6 on the output side are substantially the same as the electrical characteristics of the transistor Tr 5 on the input side, and the electrical characteristics of the transistor Tr 8 on the output side are substantially the same as the electrical characteristics of the transistor Tr 7 on the input side. Accordingly, the transistors Tr 6 and Tr 8 on the output side pass a current I 4 that has substantially the same value of the value of a current I 3 that flows through the transistors Tr 5 and Tr 7 on the input side.

A node N 1 at a coupling point of the drains of the transistors Tr 3 and Tr 5 , and a node N 2 at a coupling point of the drains of the transistors Tr 4 and Tr 6 is coupled to the second differential amplifier circuit 20 . The node N 2 is coupled also to the gate of an output transistor Tr 22 on the pull-down side of the output stage circuit 30 .

The first differential amplifier circuit 10 is activated based on the current I 2 supplied from the transistor Tr 2 , amplifies a potential difference between the potential of the input signal VP and the potential of the input signal VM, and outputs the amplified potential difference to the second differential amplifier circuit 20 and the output transistor Tr 22 .

The second differential amplifier circuit 20 includes a differential pair 21 , a current source 22 , and a current mirror circuit 23 . The differential pair 21 includes transistors Tr 11 and Tr 12 . The transistors Tr 11 and Tr 12 are NMOS transistors for example. The gate of the transistor Tr 11 is coupled to the node N 1 . The gate of the transistor Tr 12 is coupled to the node N 2 . The source of the transistor Tr 11 is coupled to the drain of a transistor Tr 15 . The source of the transistor Tr 12 is coupled to the drain of a transistor Tr 16 . The transistors Tr 15 and Tr 16 are NMOS transistors for example. The transistors Tr 11 and Tr 12 may have substantially the same electrical characteristics. The transistors Tr 5 , Tr 6 , Tr 11 , and Tr 12 may have substantially the same ratio of a channel width (W) to a channel length (L) (hereinafter referred to as the “W/L ratio”). According to the embodiment, all of the transistors Tr 5 , Tr 6 , Tr 11 , and Tr 12 may have substantially the same electrical characteristics or substantially the same size.

The gates of the transistors Tr 15 and Tr 16 are coupled to the node N 1 . The sources of the transistors Tr 15 and Tr 16 are coupled to the ground GND. The transistors Tr 15 and Tr 16 , and the transistor Tr 7 are coupled to each other and make up a current mirror circuit. The transistors Tr 15 and Tr 16 may have substantially the same electrical characteristics. The transistors Tr 7 , Tr 8 , Tr 15 , and Tr 16 may have substantially the same W/L ratio. All of the transistors Tr 7 , Tr 8 , Tr 15 , and Tr 16 may have substantially the same electrical characteristics or substantially the same size. Thus, the transistors Tr 15 and Tr 16 operate as the current source 22 . The transistor Tr 15 passes a current I 5 , and the transistor Tr 16 passes a current I 6 . The currents I 5 and I 6 have substantially the same value as the value of the current I 3 that flows through the transistor Tr 7 (Tr 5 ). A current that flows through the transistors Tr 15 and Tr 16 that make up the current source 22 is controlled based on the gate voltage of the transistor Tr 7 (the drain voltage of the transistor Tr 5 ). The current mirror circuit 12 operates also as a current control circuit that controls a current of the current source 22 .

The drain of the transistor Tr 11 is coupled to the drain of a transistor Tr 13 . The drain of the transistor Tr 12 is coupled to the drain of a transistor Tr 14 . The transistors Tr 13 and Tr 14 are PMOS transistors for example. The transistors Tr 13 and Tr 14 are coupled to each other and operate as the current mirror circuit 23 .

A node N 3 at a coupling point of the drains of the transistors Tr 11 and Tr 13 is coupled to the gate of an output transistor Tr 21 on the pull-up side of the output stage circuit 30 .

The second differential amplifier circuit 20 is activated based on the current supplied from the current source 22 , and operates as a differential voltage detection circuit that detects a differential voltage between the nodes N 1 and N 2 .

The output stage circuit 30 includes the output transistor Tr 21 , and the output transistor Tr 22 . For example, the output transistor Tr 21 is a PMOS transistor, and the output transistor Tr 22 is an NMOS transistor. The gate of the output transistor Tr 21 is coupled to the node N 3 . The source of the output transistor Tr 21 is coupled to the power source Vcc. The drain of the output transistor Tr 21 is coupled to an output terminal To. The transistor Tr 21 passes a drain current I 7 dependent on the potential of the node N 3 as an idling current.

The gate of the output transistor Tr 22 is coupled to the node N 2 . The drain of the output transistor Tr 22 is coupled to the output terminal To. The source of the output transistor Tr 22 is coupled to the ground GND. The transistor Tr 22 passes a drain current I 8 dependent on the potential of the node N 2 as an idling current.

The operational amplifier according to the embodiment operates so that an output signal Vout is input as the input signal VM. That is, the inverting input terminal T 1 and the output terminal To are coupled to each other and the operational amplifier operates as a voltage follower circuit. In the operational amplifier that operates as a voltage follower circuit, the transistors Tr 3 and Tr 4 pass currents that have substantially the same value and cause the drain voltages of the transistors Tr 3 and Tr 4 (the potentials of the nodes N 1 and N 2 ) to be substantially the same.

The current I 2 supplied from the transistor Tr 2 to the differential pair 11 is divided into the currents I 3 and I 4 using the transistors Tr 3 and Tr 4 . The current I 3 that flows through the transistor Tr 3 further flows through the transistors Tr 5 and Tr 7 coupled in series. The current I 4 that flows through the transistor Tr 4 further flows through the transistors Tr 6 and Tr 8 coupled in series. The transistors Tr 7 and Tr 8 have substantially the same electrical characteristics. The source voltages of the transistors Tr 7 and Tr 8 have substantially the same value, and the gate voltages of the transistors Tr 7 and Tr 8 also have substantially the same value. The drain of the transistor Tr 7 is coupled to the source of the transistor Tr 5 , and the drain of the transistor Tr 8 is coupled to the source of the transistor Tr 6 . Thus, the output impedances of the sources of the transistors Tr 5 and Tr 6 may be substantially the same. The drain voltage of the transistor Tr 5 is supplied in common to the gates of the transistors Tr 5 and Tr 6 . That is, the transistors Tr 5 and Tr 6 operate as a current mirror circuit. The transistor Tr 6 is coupled to the transistor Tr 5 , and has substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 5 . The transistor Tr 8 is coupled to the transistor Tr 7 , and has substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 7 . Thus, the transistor Tr 6 operates with substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 5 , and the transistor Tr 8 operates with substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 7 . Accordingly, the transistors Tr 6 and Tr 8 may pass a current that has substantially the same value as the value of the current I 3 that flows through the transistors Tr 5 and Tr 7 .

Each node voltage of the transistors Tr 5 and Tr 7 coupled in series is determined based on the current I 3 and the electrical characteristics of the transistors Tr 5 and Tr 7 . The drain voltage of the transistor Tr 5 is, that is, the gate voltages of the transistors Tr 5 and Tr 7 are determined so that the transistors Tr 5 and Tr 7 may operate. Even when variation in the characteristics of the transistors Tr 5 and Tr 7 is caused by a manufacturing process for example, the drain voltage of the transistor Tr 5 is determined so that the transistor Tr 5 may operate.

The transistor Tr 11 in the second differential amplifier circuit 20 , the gate of which the drain voltage of the transistor Tr 5 is supplied to as an input voltage, is coupled to the transistor Tr 6 . The transistor Tr 15 in the second differential amplifier circuit 20 is coupled to the transistor Tr 8 . The transistor Tr 11 has substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 6 (Tr 5 ), and the transistor Tr 15 has substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 8 (Tr 7 ). Thus, the transistor Tr 11 may operate with substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 6 (Tr 5 ), and the transistor Tr 15 may operate with substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 8 (Tr 7 ). The current I 5 , which has substantially the same value as the value of the current I 3 that flows through the transistor Tr 7 , flows through the transistor Tr 15 , and the source potential of the transistor Tr 11 becomes substantially the same as the source potential of the transistor Tr 5 . The drain voltage of the transistor Tr 5 is supplied in common to the gates of the transistors Tr 11 and Tr 5 . Since the transistor Tr 11 is applied with the gate-source voltage based on the drain voltage of the transistor Tr 5 , the transistor Tr 11 may operate as desired.

When variation in the characteristics of the transistors Tr 5 and Tr 7 is caused by a manufacturing process for example, the characteristics of the transistors Tr 11 and Tr 15 vary as well. Accordingly, the transistors Tr 11 and Tr 15 may operate with substantially the same electrical characteristics as the electrical characteristics of the transistors Tr 5 and Tr 7 . As a result, the transistor Tr 11 may operate as desired regardless of the variation in the characteristics.

The transistors Tr 12 and Tr 16 differ from the transistors Tr 11 and Tr 15 in that the gate of the transistor Tr 12 is coupled to the node N 2 . The operational amplifier according to the embodiment, which operates as a voltage follower circuit, causes the voltages of the nodes N 1 and N 2 to be substantially the same. Thus, the voltage relationship between the transistors Tr 12 and Tr 16 and the voltage relationship between the transistors Tr 11 and Tr 15 are substantially the same. Accordingly, the transistors Tr 12 and Tr 16 may operate similarly to the transistors Tr 11 and Tr 15 . Since, similar to the transistor Tr 11 , the transistor Tr 12 is applied with the gate-source voltage from the current mirror circuit 12 regardless of the variation in the characteristics, the transistor Tr 11 may operate as desired.

Described below is a case where the voltage level of the input signal VP rises after the output signal Vout is maintained at the voltage level of the input signal VP.

When the voltage level of the input signal VP rises, the value of the drain current I 3 of the transistor Tr 3 increases, and the value of the drain current I 4 of the transistor Tr 4 decreases. Accordingly, the voltage value of the node N 2 decreases and the transistor Tr 22 is turned off.

When the potential of the node N 2 becomes lower than the potential of the node N 1 , the potential of the node N 3 in the second differential amplifier circuit 20 decreases, and the output transistor Tr 21 is turned on. As a result, the voltage level of the output signal Vout rises and the output signal Vout is maintained at the voltage level of the input signal VP. When the potential of the node N 3 decreases based on the difference between the potentials of the nodes N 1 and N 2 , the value of the gate-source voltage of the transistor Tr 21 increases, and the value of the current supplied from the transistor Tr 21 to the transistor Tr 22 increases. When the value of the drain current of the transistor Tr 22 increases, the value of the gate-source voltage of the transistor Tr 22 increases. As a result, the potential of the node N 2 increases. Thus, the potentials of the nodes N 1 and N 2 become substantially the same.

As the value of the drain current I 3 of the transistor Tr 3 increases, the value of the drain current I 5 of the transistor Tr 15 increases, and the value of the drain current I 6 of the transistor Tr 16 increases. When the value of the drain current I 6 increases, an operating current of the second differential amplifier circuit 20 (the differential pair 21 ) increases. As a result, the value of the current supplied from the transistor Tr 21 to the transistor Tr 22 may be higher compared with the operational amplifier in FIG. 4 . Thus, the potentials of the nodes N 1 and N 2 may be caused to be substantially the same, and the output signal Vout may be caused to be at the voltage level of the input signal VP.

Described below is a case where the voltage level of the input signal VP falls after the output signal Vout is maintained at the voltage level of the input signal VP.

When the voltage level of the input signal VP falls, the value of the drain current I 3 of the transistor Tr 3 decreases, and the value of the drain current I 4 of the transistor Tr 4 increases. As a result, the voltage level of the node N 2 rises and the transistor Tr 22 is turned on.

When the potential of the node N 2 becomes higher than the potential of the node N 1 , the potential of the node N 3 in the second differential amplifier circuit 20 increases, and the output transistor Tr 21 is turned off. Accordingly, the voltage level of the output signal Vout falls and the output signal Vout is maintained at the voltage value of the input signal VP. When the potential of the node N 3 increases based on the difference between the nodes N 1 and N 2 , the value of the current supplied from the transistor Tr 21 to the transistor Tr 22 decreases. When the value of the drain current of the transistor Tr 22 decreases, the value of the gate-source voltage of the transistor Tr 22 decreases. As a result, the potential of the node N 2 decreases. Thus, the potentials of the nodes N 1 and N 2 become substantially the same.

As the value of the drain current I 3 of the transistor Tr 3 decreases, the value of the drain current I 5 of the transistor Tr 15 decreases, and the value of the drain current I 6 of the transistor Tr 16 decreases. When the value of the drain current I 6 decreases, the operating current of the second differential amplifier circuit 20 (the differential pair 21 ) decreases. Accordingly, the value of the current supplied from the transistor Tr 21 to the transistor Tr 22 may be lower compared with the operational amplifier in FIG. 4 . Thus, the potentials of the nodes N 1 and N 2 may be caused to be substantially the same, and the output signal Vout may be caused to be at the voltage level of the input signal VP.

The above embodiment may provide advantages described below.

(1) A common voltage (the voltage of the node N 1 ) is supplied to the gate of the transistor Tr 11 of the differential pair 21 and to the gate of the transistor Tr 15 of the current source 22 . Accordingly, the value of the gate voltage of the transistor Tr 15 decreases depending on the gate voltage of the transistor Tr 11 even when the drain voltage of the transistor Tr 5 becomes lower than a set value due to the variation in the characteristics, which is caused by a manufacturing process for example, and the value of the gate voltage of the transistor Tr 11 decreases. When the value of the gate voltage of the transistor Tr 15 decreases, the value of the current I 5 that flows through the transistor Tr 15 decreases, and the value of the drain voltage of the transistor Tr 15 , that is, the source potential of the transistor Tr 11 decreases. Thus, possible consequences due to the variation caused by the manufacturing process may be reduced more desirably, if not prevented, compared with the operational amplifier in FIG. 4 , and the gate-source voltage that enables the transistor Tr 15 to operate may be obtained as desired. As a result, occurrence of an undesired operation that may slow down the operating speed of the second differential amplifier circuit 20 may be reduced if not prevented.

The possible consequences due to the variation caused by the manufacturing process may be reduced, if not prevented, by supplying voltages (the voltages of the node N 1 and N 2 ) with substantially the same potentials to the gate of the transistor Tr 12 of the differential pair 21 and to the gate of the transistor Tr 16 of the current source 22 .

Since the current of the current source 22 is controlled based on the voltage of the node N 1 that varies depending on the difference between the potentials of the input signals VM and VP, the output signal Vout may be caused to be at the voltage level of the input signal VP due to the operation of the second differential amplifier circuit 20 activated with the current of the current source 22 .

(2) The transistors Tr 5 and Tr 7 that determine the gate voltage of the transistor Tr 11 of the differential pair 21 are coupled in series similar to the transistors Tr 11 and Tr 15 . A common voltage (the voltage of the node N 1 ) is supplied to the gates of the transistors Tr 5 , Tr 7 , Tr 11 , and Tr 15 . The transistors Tr 5 and Tr 11 have substantially the same electrical characteristics, and the transistors Tr 7 and Tr 15 have substantially the same electrical characteristics. Thus, the transistor Tr 11 may operate with substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 5 , and the transistor Tr 15 may operate with substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 7 . When variation in the characteristics of the transistors Tr 5 and Tr 7 is caused by a manufacturing process for example, the characteristics of the transistors Tr 11 and Tr 15 vary as well. Thus, the transistors Tr 11 and Tr 15 may operate with substantially the same electrical characteristics as the electrical characteristics of the transistors Tr 5 and Tr 7 regardless of the variation in the characteristics. Accordingly, regardless of the variation in the characteristics, the transistor Tr 11 of the differential pair 21 may operate as desired as long as the transistor Tr 5 may operate. Similarly, the transistor Tr 12 of the differential pair 21 may operate as desired as long as the transistor Tr 5 may operate. When the transistor Tr 5 may operate, the drain voltage of the transistor Tr 5 is within a range of values of an input voltage with which the second differential amplifier circuit 20 (the differential pair 21 ) may operate. Thus, the range of the values of the input voltage with which the second differential amplifier circuit 20 may operate may be secured as long as the first differential amplifier circuit 10 may operate.

(3) The gate voltage of the output transistor Tr 22 is controlled using the first differential amplifier circuit 10 . The drain current I 8 (the idling current) of the output transistor Tr 22 is determined using the transistors Tr 1 to Tr 8 that operate based on the constant current I 1 of the current source 1 . The gate voltage of the output transistor Tr 21 is controlled using the second differential amplifier circuit 20 . For example, the operating currents of the transistors Tr 11 to Tr 16 in the second differential amplifier circuit 20 are determined using the transistors Tr 2 to Tr 8 in the first differential amplifier circuit 10 , which operate based on the constant current I 1 . The drain current I 7 (the idling current) of the output transistor Tr 21 is determined based on the operation of the second differential amplifier circuit 20 . Since both of the idling currents of the output transistors Tr 21 and Tr 22 are determined based on the constant current I 1 of the current source 1 , the idling currents of the output transistors Tr 21 and Tr 22 may be controlled as desired. Besides, the occurrence of variation in the current of the current source for determining both of the idling currents may be reduced if not prevented. As a result, the occurrence of the undesired operation, such as generation of an offset voltage, resulting from the variation in the current may be reduced if not prevented.

The above embodiment may be changed as described below.

As illustrated in FIG. 2 , the transistor Tr 11 in FIG. 1 may be replaced with transistors Tr 11 a and Tr 11 b coupled in parallel, and the transistor Tr 12 in FIG. 1 may be replaced with transistors Tr 12 a and Tr 12 b . The drains of the transistors Tr 11 a and Tr 11 b are coupled to the drain of the transistor Tr 13 . The sources of the transistors Tr 11 a and Tr 11 b are coupled to the drains of the transistors Tr 15 and Tr 16 . The gates of the transistors Tr 11 a and Tr 11 b are coupled to the node N 1 . The drains of the transistors Tr 12 a and Tr 12 b are coupled to the drain of the transistor Tr 14 . The sources of the transistors Tr 12 a and Tr 12 b are coupled to the drains of the transistors Tr 15 and Tr 16 . The gates of the transistors Tr 12 a and Tr 12 b are coupled to the node N 2 . The transistors Tr 11 a , Tr 11 b , Tr 12 a , and Tr 12 b may have substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 11 (Tr 12 ).

According to the configuration described above, the gate-source voltages of the transistors Tr 11 a , Tr 11 b , Tr 12 a , and Tr 12 b may be caused to be lower compared with the configuration in FIG. 1 . Accordingly, the values of the drain voltages of the transistors Tr 15 and Tr 16 that make up the current source 22 may be caused to increase, and the value of the current of the current source 22 may be caused to increase. Thus, the value of the operating current of the second differential amplifier circuit 20 may be caused to increase.

As illustrated in FIG. 3 , the transistor Tr 15 in FIG. 2 may be replaced with transistors Tr 15 a and Tr 15 b coupled in parallel. The transistor Tr 16 in FIG. 2 may be replaced with transistors Tr 16 a and Tr 16 b coupled in parallel. The transistors Tr 15 a , Tr 15 b , Tr 16 a , and Tr 16 b may have substantially the same electrical characteristics as the electrical characteristics of the transistor Tr 15 (Tr 16 ).

The configuration illustrated in FIG. 3 may double the value of the current that flows through the current source 22 compared with the configuration of the operational amplifier in FIG. 1 . Accordingly, the value of the operating current of the second differential amplifier circuit 20 may be doubled, and the operating speed of the second differential amplifier circuit 20 may be increased.

In the embodiment, the current mirror circuit 12 in the first differential amplifier circuit 10 is made up of the transistors Tr 5 and Tr 7 coupled in series, and the transistors Tr 6 and Tr 8 coupled in series. However, the transistors Tr 7 and Tr 8 may be omitted and the current mirror circuit 12 may be made up of the transistors Tr 5 and Tr 6 . In this case, each of the channel lengths of the transistors Tr 5 and Tr 6 is preferably caused to be substantially the same as a length obtained by adding the channel length of the transistor Tr 11 to the channel length of the transistor Tr 15 , and the transistors Tr 5 , Tr 6 , Tr 11 , and Tr 15 are preferably caused to have substantially the same channel width.

The transistor Tr 16 used in the embodiment may be omitted, and the current source 22 may be made up of the transistor Tr 15 .

In the embodiment, the PMOS transistors may be replaced with the NMOS transistors, and similarly, the NMOS transistors may be replaced with the PMOS transistors. In this case, the ground GND (the low potential power source) and the power source Vcc (the high potential power source) are desirably replaced with each other.

The operational amplifier according to the embodiment is configured as a voltage follower circuit. However, the configuration is not limited as long as an output from the output terminal To may be fed back to an input terminal. The drain voltages of the input transistors Tr 3 and Tr 4 may be caused to be substantially the same by controlling the drain current of the output transistor Tr 22 and the gate-source voltage of the output transistor Tr 21 with the second differential amplifier circuit 20 .

The output transistors Tr 21 and Tr 22 according to the embodiment may be NMOS transistors. In this case, the drain voltages of the input transistors Tr 3 and Tr 4 may be caused to be substantially the same by controlling the drain current of one of the output transistors Tr 21 and Tr 22 using the second differential amplifier circuit 20 and controlling the gate-source voltage of the other one of the output transistors Tr 21 and Tr 22 .

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding aspects of the invention and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the aspects of the invention. Although the embodiment in accordance with the aspects of the invention has been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

Moreover, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from the context, the phrase “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, the phrase “X employs A or B” is satisfied by any of the following instances: X employs A; X employs B; or X employs both A and B. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form.