On/off detection circuit having function for timely detecting current flowing in electronic device

1. Technical Field

The present disclosure relates to detection circuits and, particularly, to an ON/OFF detection circuit capable of timely detecting current flowing in electronic devices.

2. Description of Related Art

Many electronic products need to be tested before delivering. One of the more important tests is the ON/OFF test for ensuring the reliability of the electronic products. Traditionally, the ON/OFF test is to turn on and off the electronic products automatically about 5000 times using a test machine. The quality of the tested electronic device is checked after finishing the ON/OFF tests. However, the operation status of the electronic device must be tested again to assure whether the electronic device has broken down during the ON/OFF testing process. It is time consuming and wasteful of resources.

Therefore, it is desirable to provide an ON/OFF detection circuit which can overcome the limitations described above.

FIG. 1 is a functional block diagram of an ON/OFF detection circuit, according to an exemplary embodiment.

FIG. 2 is a circuit diagram of a switch circuit and a current sampling circuit of the ON/OFF detection circuit of FIG. 1 .

FIG. 3 is a circuit diagram of an amplifying circuit of the ON/OFF detection circuit of FIG. 1 .

FIG. 4 is a circuit diagram of an alarm circuit of the ON/OFF detection circuit of FIG. 1 .

Embodiments of the disclosure will now be described in detail, with reference to the accompanying drawings.

Referring to FIG. 1 , an ON/OFF detection circuit 100 , according to an exemplary embodiment, is configured for timely detecting current flowing in electronic devices 110 . The ON/OFF detection circuit 100 includes a switch circuit 10 , a current sampling circuit 20 , a current amplifying circuit 30 , an alarm circuit 40 , and a control circuit 50 . The switch circuit 10 is connected with the current sampling circuit 20 and the control circuit 50 . The amplifying circuit 30 is connected between the current sampling circuit 20 and the control circuit 50 . The alarm circuit 40 is coupled with the control circuit 50 .

Referring to FIG. 2 , the switch circuit 10 includes an inductor PL 1 , a first capacitor CE 1 , a second capacitor CE 2 , a third capacitor CE 3 , a relay K 1 , a first diode D 1 , and a first transistor Q 1 . The inductor PL 1 includes a first terminal coupled to a power source Vcc of about 12 volts (V), and a second terminal connected to a cathode of the first diode D 1 . All of positive terminals of the first capacitor CE 1 , the second capacitor CE 2 , and the third capacitor CE 3 are connected to the cathode of the first diode D 1 , while all of negative terminals of the first capacitor CE 1 , the second capacitor CE 2 , and the third capacitor CE 3 are grounded. The first transistor Q 1 is an NPN type, and includes a collector “c” connected to an anode of the first diode D 1 , an emitter “e” being grounded, and a base “b” as a control terminal 11 of the switch circuit 10 . The relay K 1 includes an L1 terminal, an L2 terminal, a COM1 terminal, a COM2 terminal, an NO1 terminal, and an NO2 terminal. The L1 terminal and the L2 terminal are connected to the anode and the cathode of the first diode D 1 respectively. The COM1 terminal and the COM2 terminal are electrically interconnected to cooperatively serve as an input terminal 12 of the switch circuit 10 . The NO1 terminal and the NO2 terminal are electrically interconnected to cooperatively serve as an output terminal 13 of the switch circuit 10 . When the control terminal 11 is at a low level (e.g., logical “0”), the collector “c” and the emitter “e” of the first transistor Q 1 are disconnected. As a consequence, the relay K 1 is disconnected, while the input terminal 12 and the output terminal 13 are disconnected. When the control terminal 11 is at a high level (e.g., logical “1”), the collector “c” and the emitter “e” of the first transistor Q 1 are coupled. As a consequence, the relay K 1 is connected, and the input terminal 12 and the output terminal 13 are connected.

The current sampling circuit 20 includes a current transformer T 1 and a sampling resistor Rc. The current transformer T 1 includes a primary coil and a secondary coil. The primary coil is connected between the input terminal 12 of the switch circuit 10 and a constant voltage source 60 . The secondary coil and the sampling resistor Rc are connected in parallel. The current transformer T 1 is configured for sampling a current flowing to the electronic device 110 . The sampling resistor Rc converts the sampled current flowing in the secondary coil into a sampled voltage. A first terminal of the sampling resistor Rc serves as an AD1 terminal, and a second terminal of the sampling resistor Rc serves as an AD2 terminal.

Referring to FIG. 3 , the amplifying circuit 30 is configured for filtering and amplifying the sampled voltage between the AD1 terminal and the AD2 terminal. The amplifying circuit 30 includes a first filter circuit 31 , a first buffer amplifying circuit 32 , a second filter circuit 33 , a second buffer amplifying circuit 34 , a difference amplifying circuit 35 , and a rheostat Rf. The first filter circuit 31 is coupled to the AD1 terminal. The first buffer amplifying circuit 32 is coupled to the first filter circuit 31 . The second filter circuit 33 is coupled to the AD2 terminal. The second buffer amplifying circuit 34 is coupled to the second filter circuit 33 . The rheostat Rf is connected between the first buffer amplifying circuit 32 and the second buffer amplifying circuit 34 . The first buffer amplifying circuit 32 and the second buffer amplifying circuit 34 are coupled to the difference amplifying circuit 35 . The difference amplifying circuit 35 is connected to the control circuit 50 . The first filter circuit 31 and the second filter circuit 33 are configured for filtering the high frequency part of the sampled voltage. The first buffer amplifying circuit 32 and the second buffer amplifying circuit 34 are configured for transforming the electrical impedance of the sampled voltage output from the first filter circuit 31 and the second filter circuit 33 correspondingly. The difference amplifying circuit 35 is configured for amplifying the sampled voltage output from the first buffer amplifying circuit 32 and the second buffer amplifying circuit 34 .

The first filter circuit 31 and the second filter circuit 33 respectively include a first resistor R 1 , and a first capacitor C 1 connected in series to the first resistor R 1 . A first terminal of the first resistor R 1 of the first filter circuit 31 is coupled to the AD1 terminal, while a first terminal of the first resistor R 1 of the second filter circuit 33 is coupled to the AD2 terminal. The first capacitor C 1 includes a first terminal coupled to the first resistor R 1 , and a second terminal grounded.

The first buffer amplifying circuit 32 and the second buffer amplifying circuit 34 each include a first amplifier P 1 , a second resistor R 2 , a second capacitor C 2 , and a third resistor R 3 . The first amplifier P 1 includes a positive terminal connected to a second terminal of the first resistor R 1 , a negative terminal connected to a first terminal of the second resistor R 2 , and an output terminal connected to a second terminal of the second resistor R 2 . The second capacitor C 2 is connected between the positive terminal and the negative terminal of the first amplifier P 1 . The third resistor R 3 includes a first terminal connected to the output terminal of the first amplifier P 1 and a second terminal. The rheostat Rf is connected between two negative terminals of the first amplifiers P 1 . In this embodiment, the second buffer amplifying circuit 34 further includes a fifth resistor R 5 . The fifth resistor R 5 includes a first terminal coupled to the second terminal of the third resistor R 3 of the second buffer amplifying circuit 34 and a second terminal grounded.

The difference amplifying circuit 35 includes a second amplifier P 2 , a fourth resistor R 4 , and a fifth resistor R 5 . The second amplifier P 2 includes a negative terminal connected to the second terminal of the third resistor R 3 of the first buffer amplifying circuit 32 , a positive terminal connected to the second terminal of the third resistor R 3 of the second buffer amplifying circuit 34 , and an output terminal coupled to the control circuit 50 . The fourth resistor R 4 is connected between the negative terminal and the output terminal of the second amplifier P 2 . The fifth resistor R 5 includes a first terminal connected to the positive terminal of the second amplifier P 2 and a second terminal grounded.

Referring to FIG. 4 , the alarm circuit 40 includes a sixth resistor R 6 , a second transistor Q 2 , a second diode D 2 , and a buzzer BZ 1 . The sixth resistor R 6 includes a first terminal coupled to the control circuit 50 . The second transistor Q 2 is an NPN type, and includes a collector “c” coupled to an anode of the second diode D 2 , an emitter “e” grounded, and a base “b” coupled to a second terminal of the sixth resistor R 6 . A cathode of the second diode D 2 is connected to the power source. The buzzer BZ 1 includes a positive terminal connected to the cathode of the second diode D 2 , and a negative terminal coupled to the anode of the second diode D 2 .

The control circuit 50 includes a single chip processor with a test times and a comparison voltage preset therein. The comparison voltage defines a tolerance of acceptable range, such as ±5%, and the comparison voltage is varied according to the parameters of the electronic device 110 and the ON/OFF detection circuit 100 . The control circuit 50 is used to control the connection and disconnection between the input terminal 12 and the output terminal 13 of the switch circuit 10 via the control terminal 11 .

Before the ON/OFF detection, a power terminal of the electronic device 110 is coupled to the output terminal 13 . When the control terminal 11 is input a high level signal output from the control circuit 50 , and the input terminal 12 connects to the output terminal 13 , the electronic device 110 is turned on. The current sampling circuit 20 inducts the current flowing to the electronic device 110 and converts the sampled current to a sampled voltage. The sampled voltage is filtered and amplified by the amplifying circuit 30 , and then is output to the control circuit 50 . The control circuit 50 converts the sampled voltage from an analog signal to a digital signal, and compares the sampled voltage with the comparison voltage. The control circuit 50 controls the alarm circuit 40 according to the comparing result. When the control terminal 11 is input a low level signal output from the control circuit 50 , and the input terminal 12 disconnects from the output terminal 13 , the electronic device 110 is turned off.

If the sampled voltage exceeds the acceptable range of the comparison voltage during the test, the electronic device is unqualified. If the sampled voltage locates in the acceptable range of the comparison voltage, the test times subtracts one. The electronic device 110 is repeatedly turned off and turned on via the ON/OFF detection circuit 100 , meanwhile, the voltage is timely sampled and compared with the acceptable range of the comparison voltage. If the test times are exhausted but all of the sampled voltages are located in the acceptable range of the comparison voltage, the electronic device is qualified.

It will be understood that particular embodiments and methods are shown and described by way of illustration only. The principles and the features of the present disclosure may be employed in various and numerous embodiments thereof without departing from the scope of the disclosure as claimed. The above-described embodiments illustrate the scope of the disclosure but do not restrict the scope of the disclosure.