Low dropout regulator circuit without external capacitors rapidly responding to load change

1. Field of Invention

The present invention relates to an analog integrated circuit technology, and more particularly to a low dropout regulator circuit without external capacitors rapidly responding to load change.

2. Description of Related Arts

The low dropout regulator (LDO) is widely used in various analog integrated circuits and mixed-signal integrated circuits owing to its advantages of low output voltage ripple, low noise and low quiescent current.

A conventional LDO circuit is shown in FIG. 1 , wherein VREF_GEN is a reference voltage generating circuit, OP is an operational amplifier, MP 1 is an output regulating transistor, RF 1 and RF 2 are feedback resistors, RL is a load resistor, CL is a load capacitor. The working principle of the LDO is described as follows. The reference voltage generating circuit transmits a reference voltage to a negative input node of the operational amplifier, then the feedback resistors feedback a voltage in proportion to the output voltage to a positive input node of the operational amplifier, and then the operational amplifier detects the difference between the feedback voltage and the reference voltage. According to the difference, the gate voltage of the output regulating transistor MP 1 is regulated. When the feedback voltage VFB is higher than the reference voltage VREF, the operational amplifier will pull up the gate voltage Vc of the output regulating transistor, then the output voltage VOUT will be decreased so as to lower the feedback voltage VFB to the reference voltage VREF. When the feedback voltage VFB is lower than the reference voltage VREF, the operational amplifier will pull down the gate voltage Vc of the output regulating transistor, then the output voltage VOUT will be increased so as to increase the feedback voltage VFB to the reference voltage VREF. Therefore, the LDO circuit stabilizes the output voltage VOUT by the negative feedback of the operational amplifier and the regulating transistor. When the LDO circuit is stable, the output voltage thereof can be expressed as follows:

VOUT=VREF*( RF 1 +RF 2)/ RF 2

For the LDO circuit shown in FIG. 1 , when the rapid load transition (ns level) occurs, the transient current what are needed herein is mainly provided by the load capacitor CL for obtaining the stable output voltage. Therefore, it is necessary for the LDO circuit to be provided with a more than μF-level large capacitor by the exterior so as to provide a good load transient response thus increasing the system cost. Furthermore, the resistance of the external capacitor's parasitic resistor will affect the loop stability of the LDO circuit, thus greatly increasing the complexity of the system design. If there is no external capacitor CL, when the rapid load transition (ns level) occurs, it has to be the negative feedback loop to respond to the load transition, so it is required that the bandwidth of the whole loop is larger than GHz. The output regulating transistor MP 1 has a very large width-length ratio and a large gate parasitic capacitance, so the current of the operational amplifier must be very large for obtaining the GHz-level loop bandwidth, otherwise the deficiency of the loop bandwidth will cause the big ripple of the output voltage VOUT. When the ripple of the output voltage VOUT exceeds ±10%, the LDO power supply system will not work properly.

An object of the present invention is to provide a low dropout regulator (LDO) circuit without external capacitors rapidly responding to load change, which is capable of controlling the output voltage by two loops of the slow operational amplifier loop and fast comparator loop, so that the load response speed of the LDO is greatly improved without the increase of the power consumption and external large capacitor.

Accordingly, in order to accomplish the above object, the present invention provides a low dropout regulator circuit without external capacitors rapidly responding to load change, comprising:

a slow path for controlling voltage comprising an operational amplifier I 0 ;

a fast path for controlling voltage comprising a comparator I 1 , a comparator I 2 , a field effect transistor MN 1 and a field effect transistor MN 2 ;

a shared branch comprising a driving transistor MPR, a resistor RF 1 and a resistor RF 2 , wherein said operational amplifier I 0 , driving transistor MPR, resistor RF 1 and resistor RF 2 form an operational amplifier loop for providing an accurate output voltage, said comparator I 1 , comparator I 2 , field effect transistor MN 1 , field effect transistor MN 2 , driving transistor MPR, resistor RF 1 and resistor RF 2 form a comparator loop for responding to rapid load change; and

a reference voltage generating circuit 13 for providing said operational amplifier I 0 , said comparator I 1 and said comparator I 2 with three reference voltages VR, VRL and VRH respectively, wherein a relationship among said three reference voltages is VRH>VR>VRL.

The specific circuit connection of the low dropout regulator (LDO) circuit is described as follows:

a negative input of the operational amplifier I 0 is connected with the output reference voltage VR of the reference voltage generating circuit 13 , a positive input of the operational amplifier I 0 is connected with one end of the resistor RF 1 and one end of the resistor RF 2 , an output of the operational amplifier I 0 is connected with a gate of the driving transistor MPR;

a positive input of the comparator I 1 is connected with the output reference voltage VRL of the reference voltage generating circuit I 3 , a negative input of the comparator I 1 is connected with the end of the resistor RF 2 , an output of the comparator I 1 is connected with a gate of the field effect transistor MN 1 ;

a negative input of the comparator I 2 is connected with the output reference voltage VRH of the reference voltage generating circuit I 3 , a positive input of the comparator I 2 is connected with the end of the resistor RF 2 , an output of the comparator I 2 is connected with a gate of the field effect transistor MN 2 ;

a source of the driving transistor MPR is connected with the power supply, a drain of the driving transistor MPR is connected with the other end of the resistor RF 1 ;

a drain of the FET MN 1 is connected with the gate of driving transistor MPR, a source of the field effect transistor MN 1 is connected with the ground;

a drain of the field effect transistor MN 2 is connected with the drain of the driving transistor MPR, a source of the field effect transistor MN 2 is connected with the ground;

the end of the resistor RF 1 connecting with the operational amplifier I 0 is connected with one end of the resistor RF 2 , the other end of the resistor RF 1 is connected with the drain of the driving transistor MPR, the other end of the resistor RF 2 is connected with the ground;

the gate of the driving transistor MPR is connected with one end of a resistor Rc, the other end of the resistor Rc is connected with one end of a capacitor Cc, the other end of the capacitor Cc is connected with the drain of the driving transistor MPR.

The working principle of the low dropout regulator (LDO) circuit is explained as follows.

When the current load at the output is constant, the output voltage will be controlled by the operational amplifier loop, the feedback voltage VFB of the operational amplifier loop is equal to the reference voltage VR. Now, the outputs of the comparator I 1 and the comparator I 2 are low voltage, the field effect transistor MN 1 and the field effect transistor MN 2 are shut off without affecting the normal work of the operational amplifier loop;

when the current load at the output changes from heavy load to light load, owing to inadequate response speed of the operational amplifier loop, the output voltage will have an overshoot of upward transition. When the overshoot voltage exceeds VRH(RF 1 +RF 2 )/RF 2 , the output of the comparator I 2 will be high level, the field effect transistor MN 2 will be conducted, so that the output voltage VOUT will be pulled down and the upward transition overshoot voltage of the output voltage will be reduced;

when the current load at the output changes from light load to heavy load, the output voltage will have an overshoot of downward transition. When the overshoot voltage is lower than VRL(RF 1 +RF 2 )/RF 2 , the output of the comparator I 1 will be high level, the field effect transistor MN 1 will be conducted thus pulling down the gate voltage of the driving transistor MPR, so that the output voltage will be pulled up and the downward transition overshoot voltage of the output voltage will be reduced.

The current load of the whole LDO circuit changes from 1 mA to 100 mA, and then to 1 mA, the rise and fall time is 100 ns. The transition peak of the output voltage is 113 mV, which fully satisfies the general requirement of the linear power supply of ±10%.

The resistor Rc is a Miller compensation zero resistor. The capacitor Cc is a Miller compensation capacitor. The resistor Rc is connected with the capacitor Cc producing a left half plane zero to improve the phase margin of the LDO circuit. A value of the left half plane zero is 1/(Rc*Cc). By pole splitting of the capacitor Cc, the main pole moves to low frequency, and the secondary pole moves to high frequency so that the operational amplifier is stabilized.

The benefits of the present invention are shown as follows.

The circuit can control the output by two loops of a slow operational amplifier loop and a fast comparator loop so that the load response speed of the LDO is greatly improved without the increase of power consumption and external big capacitor.

These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.

FIG. 1 is a conventional LDO circuit.

FIG. 2 is a circuit diagram of a low dropout regulator (LDO) circuit without external capacitors rapidly responding to load change according to a preferred embodiment of the present invention.

FIG. 3 is an implementation diagram of an operational amplifier of the present invention.

FIG. 4 is an implementation diagram of a comparator of the present invention.

FIG. 5 is a simulation waveform of the LDO circuit of the present invention.

Referring to the FIG. 2 , a low dropout regulator (LDO) circuit without external capacitors rapidly responding to load change according to a preferred embodiment of the present invention is illustrated, which comprises a slow pathway and a fast pathway for controlling voltage, wherein the slow pathway for providing precise output voltage comprises an operational amplifier I 0 , a driving transistor MPR, a resistor RF 1 and a resistor RF 2 forming an operational amplifier loop, and the fast pathway for responding to rapid load change comprises a comparator I 1 , a comparator I 2 , a field effect transistor (FET) MN 1 , a field effect transistor (FET) MN 2 , a driving transistor MPR, a resistor RF 1 and a resistor RF 2 forming a comparator loop.

The low dropout regulator (LDO) circuit without external capacitors rapidly responding to load change further comprises a reference voltage generating circuit 13 for providing the operational amplifier I 0 , the comparator I 1 and the comparator I 2 with three reference voltages VR, VRL and VRH respectively, wherein the relationship among the three reference voltages is VRH>VR>VRL.

The specific circuit connection of the low dropout regulator (LDO) circuit is described as follows.

A negative input of the operational amplifier I 0 is connected with the output reference voltage VR of the reference voltage generating circuit 13 , a positive input of the operational amplifier I 0 is connected with one end of the resistor RF 1 and one end of the resistor RF 2 , an output of the operational amplifier I 0 is connected with a gate of the driving transistor MPR.

A positive input of the comparator I 1 is connected with the output reference voltage VRL of the reference voltage generating circuit I 3 , a negative input of the comparator I 1 is connected with the end of the resistor RF 2 , an output of the comparator I 1 is connected with a gate of the FET MN 1 .

A negative input of the comparator I 2 is connected with the output reference voltage VRH of the reference voltage generating circuit I 3 , a positive input of the comparator I 2 is connected with the end of the resistor RF 2 , an output of the comparator I 2 is connected with a gate of the FET MN 2 .

A source of the driving transistor MPR is connected with the power supply, a drain of the driving transistor MPR is connected with the other end of the resistor RF 1 .

A drain of the FET MN 1 is connected with the gate of driving transistor MPR, a source of the FET MN 1 is connected with the ground.

A drain of the FET MN 2 is connected with the drain of the driving transistor MPR, a source of the FET MN 2 is connected with the ground.

The end of the resistor RF 1 connecting with the operational amplifier I 0 is connected with one end of the resistor RF 2 , the other end of the resistor RF 1 is connected with the drain of the driving transistor MPR, the other end of the resistor RF 2 is connected with the ground.

The gate of the driving transistor MPR is connected with one end of a resistor Rc, the other end of the resistor Rc is connected with one end of a capacitor Cc, the other end of the capacitor Cc is connected with the drain of the driving transistor MPR.

The working principle of the low dropout regulator (LDO) circuit is explained as follows.

When the current load at the output is constant, the output voltage will be controlled by the operational amplifier loop, the feedback voltage VFB of the operational amplifier loop is equal to the reference voltage VR. Now, the outputs of the comparator I 1 and the comparator I 2 are low voltage, the FET MN 1 and the FET MN 2 are shut off without affecting the normal work of the operational amplifier loop.

When the current load at the output changes from heavy load to light load, owing to inadequate response speed of the operational amplifier loop, the output voltage will have an overshoot of upward transition. When the overshoot voltage exceeds VRH(RF 1 +RF 2 )/RF 2 , the output of the comparator I 2 will be high level, the FET MN 2 will be conducted, so that the output voltage VOUT will be pulled down and the upward transition overshoot voltage of the output voltage will be reduced.

When the current load at the output changes from light load to heavy load, the output voltage will have an overshoot of downward transition. When the overshoot voltage is lower than VRL(RF 1 +RF 2 )/RF 2 , the output of the comparator I 1 will be high level, the FET MN 1 will be conducted thus pulling down the gate voltage of the driving transistor MPR, so that the output voltage will be pulled up and the downward transition overshoot voltage of the output voltage will be reduced.

The resistor Rc is a Miller compensation zero resistor which is adapted for producing a left half plane zero to improve the phase margin. The capacitor Cc is a Miller compensation capacitor which is adapted for the Miller compensation to stabilize the operational amplifier loop.

As shown in FIG. 3 , the operational amplifier I 0 is achieved by the FETs MP 11 , MP 12 , MP 13 , MP 14 , MP 15 , MP 16 , MN 11 , MN 12 , MN 13 and MN 14 . Sources of the FETs MP 11 , MP 12 , MP 13 and MP 14 are connected with the power supply. A gate of the FET MP 11 , a drain of the FET MP 11 and a gate of the FET MP 12 are connected with a drain of the FET MN 12 . A drain of the FET MP 12 and a source of the FET MP 15 are connected with a source of the FET MP 16 . A gate of the FET MP 13 , a drain of the FET MP 13 and a gate of the FET MP 14 are connected with a drain of the FET MN 13 . A drain of the FET MP 14 is connected with a drain of the FET MN 16 . A gate of the FET MN 16 , a gate of the FET MN 15 and a drain of the FET MN 15 are connected with a drain of the FET MP 16 . A gate of the FET MN 13 , a gate of the FET MN 14 and a drain of the FET MN 14 are connected with a drain of the FET MP 15 . Sources of the FETs MN 11 , MN 12 , MN 13 , MN 14 , MN 15 and MN 16 are connected with the ground. A gate of the FET MN 12 and a gate of the FET MN 11 are connected with a drain of the FET MN 11 as a bias current input of the operational amplifier I 0 . A gate of the FET MP 15 is a negative input of the operational amplifier I 0 . A gate of the FET MP 16 is a positive input of the operational amplifier I 0 .

As shown in FIG. 4 , the circuit diagram of the comparator I 1 is the same as that of the comparator I 2 which is achieved by the FETs MP 21 , MP 22 , MN 21 , MN 22 , MN 23 and MN 24 . A source of the FET MP 21 and a source of the FET MP 22 are connected with the power supply. A drain of the FET MP 21 , a gate of the FET MP 21 and a gate of the FET MP 22 are connected with a drain of the FET MN 21 . A drain of the FET MP 22 is connected with that of the FET MN 22 . A drain of the FET MN 23 and a gate of the FET MN 23 are connected with a gate of the FET MN 24 . A source of the FET MN 23 and a source of the FET MN 24 are connected with the ground. A drain of the FET MN 24 and a source of the FET MN 21 are connected with a source of the FET MN 22 . A gate of the FET MN 21 is a positive input of the comparator. A gate of the FET MN 22 is a negative input of the comparator.

Referring to FIG. 5 , the current load change from 1 mA to 100 mA, and then to 1 mA, the rise and fall time is 100 ns. As can be seen from the simulation graph, the transition peak of the output voltage is 113 mV, which fully satisfies the general requirement of the linear power supply of ±10%.

One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.

It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.