Infrared control system

1. Technical Field

The disclosure generally relates to control systems, and more particularly relates, to an infrared control system for remotely controlling a computer.

2. Description of the Related Art

Generally, computers are controlled through keyboards or touchpads. In either case physical contact is required between the user and the computer. However, it can be inconvenient to have to physically contact the computer each time to use it.

Therefore, there is room for improvement within the art.

Many aspects of an infrared control system can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the exemplary infrared control system. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment.

FIG. 1 is a block view of an infrared control system including an infrared control unit and a computer, according to an exemplary embodiment.

FIG. 2 is a circuit view of the infrared control unit of the infrared control system shown in FIG. 1 .

FIG. 3 is a circuit view of an infrared response unit of the computer shown in FIG. 1 .

FIG. 1 shows an exemplary embodiment of an infrared control system 100 , which includes an infrared control unit 10 and a computer 20 communicating with the infrared control unit 10 using infrared signals. The computer 20 includes an infrared response unit 21 , a power on/off port 23 , and a reset signal port 25 ; among them, the infrared response unit 21 is electrically connected to the power on/off port 23 and the reset signal port 25 .

The infrared response unit 21 includes an infrared receiving circuit 211 , a control circuit 213 , a power on/off circuit 215 , and a reset circuit 217 . The control circuit 213 is electrically connected to the infrared receiving circuit 211 , the power on/off circuit 215 , and the reset circuit 217 . The power on/off circuit 215 is electrically connected to the power on/off port 23 , and the reset circuit 217 is electrically connected to the reset signal port 25 .

The infrared control unit 10 can be integrated with an existing infrared remote controller and is capable of transmitting infrared signals. The infrared receiving circuit 211 receives the infrared signals from the infrared control unit 10 and then decodes the infrared signals. The control circuit 213 receives and processes the infrared signals from the infrared receiving circuit 211 to generate corresponding command signals. The command signals are transmitted to the power on/off circuit 215 or the reset circuit 217 to power the computer 20 on/off or reset the computer 20 .

Also referring to FIG. 2 , the infrared control unit 10 includes an encoder U 1 , a switch module with switches S 0 -S 2 , a first transistor T 1 , three diodes D 1 -D 3 , twelve resistors R 1 -R 12 , and a light emitting diode (LED) D 0 . The encoder U 1 may be a PT2262-M3L3 encoder and includes nine first address ports A 0 -A 8 , three encoding input ports DA 0 -DA 2 , and an output port Dout. Among the address ports A 0 -A 8 , the resistors are series connected in pairs R 1 :R 5 , R 2 :R 6 , R 3 :R 7 , R 4 :R 8 and all the pairs are connected together in parallel. The node between resistors R 5 -R 8 is electrically connected to a first power source VBB, and the node between resistors R 1 -R 4 is connected to ground. The resistors R 1 -R 4 have the same resistance value, the resistors R 5 -R 8 have the same resistance value, and the resistors R 9 -R 11 have the same resistance value.

The first address ports A 0 and A 1 are electrically connected to the first power source VBB. The first address port A 2 is electrically connected to the node between the resistors R 2 and R 6 , the first address port A 3 is electrically connected to the node between the resistors R 3 and R 7 , the first address port A 4 is electrically connected to the node between the resistors R 4 and R 8 , and the first address port A 5 is electrically connected to the node between the resistors R 1 and R 5 . The first address ports A 6 -A 8 are electrically connected to ground.

The anode of the diode D 1 is electrically connected to the resistor R 9 in series, the anode of the diode D 2 and the resistor R 10 are connected in series and together connected in parallel to the diode D 1 and the resistor R 9 , and the anode of the diode D 3 and the resistor R 11 are connected in series and together connected in parallel to the diode D 2 and the resistor R 10 . The cathodes of the diodes D 1 -D 3 are electrically connected to the first power source VBB. The resistors R 9 -R 12 are electrically connected to ground.

The encoding input port DA 0 of the encoder U 1 is electrically connected to the node between the anode of the diode D 1 and the resistor R 9 and electrically connected to one end of the switch S 2 , and another end of the switch S 2 is electrically connected to the first power source VBB. The encoding input port DA 1 of the encoder U 1 is electrically connected to the node between the anode of the diode D 2 and the resistor R 10 and electrically connected to one end of the switch S 1 . Another end of the switch S 1 is electrically connected to the first power source VBB. The encoding input port DA 2 of the encoder U 1 is electrically connected to the node between the anode of the diode D 3 and the resistor R 11 and electrically connected to one end of the switch S 0 , and another end of the switch S 0 is electrically connected to the first power source VBB.

The LED D 0 may be an infrared LED in this embodiment. The first transistor T 1 may be an npn transistor in this embodiment. The base of the first transistor T 1 is electrically connected to the resistor R 12 and the output port Dout of the encoder U 1 in series. The emitter of the transistor T 1 is connected to ground, and the collector of the transistor T 1 is electrically connected to the cathode of the LED D 0 . The anode of the LED D 0 is electrically connected to the first power source VBB. The first power source VBB can be supplied by an existing 5V battery.

In this exemplary embodiment, when pressed, the switches S 0 -S 2 are associated with the operation states of the computer 20 . When the switches S 0 , S 1 , and S 2 are not pressed, the computer 20 maintains a predetermined operating state. When the switch S 0 is pressed, the computer 20 is powered on. When the switch S 1 is pressed, the computer 20 is powered off; when the switch S 2 is pressed, the computer 20 is reset. Thereby, when any one switch among the switches S 0 -S 2 is pressed, the associated encoding input port DA 0 , DA 1 , or DA 2 receives corresponding input voltage provided by the first power source VBB, so the associated encoding input port DA 0 , DA 1 , or DA 2 goes high level.

Providing that 1 represents high level and 0 represents low level, then the encoding input ports DA 0 -DA 2 of the encoder U 1 have logical combinations based on the pressed switch module S 0 -S 2 as follows: when no switches S 0 -S 2 are pressed, the logical combination of the encoding input ports DA 0 -DA 2 is 000; when the switch S 0 is pressed, the logical combination of the encoding input ports DA 0 -DA 2 is 001; when the switch S 1 is pressed, the logical combination of the encoding input ports DA 0 -DA 2 is 010; when the switch S 2 is pressed, the logical combination of the encoding input ports DA 0 -DA 2 is 100. The encoder U 1 encodes the logical combinations to generate corresponding address codes and data codes, and the LED D 0 transmits the address codes and the data codes to the infrared receiving circuit 211 using infrared signals.

Also referring to FIG. 3 , the infrared receiving circuit 211 includes an infrared probe U 2 , a second transistor T 2 , a decoder U 3 , a capacitor CR, and three resistors R 13 , R 14 , and R 15 . The second transistor T 2 can be an npn transistor in this embodiment. The infrared probe U 2 is electrically connected between the base and the emitter of the second transistor T 2 and is capable of receiving infrared signals including logical combinations. The emitter of the second transistor T 2 is electrically connected to ground, and the base of the second transistor T 2 is electrically connected to a second power source VCC through the resistor R 13 . The collector of the second transistor T 2 is electrically connected to one end of the resistor R 14 and one end of the resistor R 15 , another end of the resistor R 14 is electrically connected to the second power source VCC, another end of the resistor R 15 is electrically connected to one end of the capacitor CR, and another end of the capacitor CR is electrically connected to the decoder U 3 .

The decoder U 3 may be a PT2272-M3L3 decoder and includes nine second address ports B 0 -B 8 , a decoding input port Din, and three decoding output ports DB 0 -DB 2 . The decoding input port Din is electrically connected to the collector of the second transistor T 2 through the capacitor CR and the resistor R 15 in turn. The second address ports B 0 -B 8 and the decoding output ports DB 0 -DB 2 are electrically connected to the control circuit 213 . Thereby, when the infrared probe U 2 of the infrared receiving circuit 211 receives the encoded infrared signals from the infrared control circuit 10 , the infrared signals are transmitted to the decoding input port Din and are decoded to generate corresponding address codes and data codes.

The control circuit 213 includes a control chip U 4 , which can be a PIC16F73 control chip and includes nine third address ports C 0 -C 8 , three data ports RA 0 -RA 2 , a power control port V, and a reset control port Reset. In this exemplary embodiment, the third address ports C 0 -C 8 are electrically connected to the second address ports B 0 -B 8 , respectively, for receiving the address codes from the decoder U 3 . For example, the address port B 0 is electrically connected to the address port C 0 , and the address port B 2 is electrically connected to the address port C 2 . The data ports RA 0 -RA 2 are electrically connected to the decoding output ports DB 0 -DB 2 , respectively, for receiving the data codes from the decoder U 3 . The power control port V is electrically connected to the power on/off circuit 215 and is capable of outputting a corresponding command signal according to the address code and the data code to power the computer 20 on/off. The reset control port Reset is electrically connected to the reset circuit 217 and is capable of outputting a corresponding command signal according to the address code and the data code to reset the computer 20 .

The power on/off circuit 215 includes a first field effect transistor (FET) Q 1 and two resistors R 16 and R 17 . The gate of the first FET Q 1 is electrically connected to the power control port V through the resistor R 16 to receive the corresponding command signals. The source of the first FET Q 1 is electrically connected to ground and the drain of the first FET Q 1 is electrically connected to the second power source VCC through the resistor R 17 . The drain of the first FET Q 1 is further electrically connected to the power on/off port 23 of the computer 20 to transmit the command signals to the computer 20 , for powering the computer 20 on/off.

The reset circuit 217 includes a second FET Q 2 and two resistors R 18 and R 19 . The gate of the second FET Q 2 is electrically connected to the reset control port Reset through the resistor R 18 for receiving the corresponding command signals. The source of the second FET Q 2 is electrically connected to ground and the drain of the second FET Q 2 is electrically connected to the second power source VCC through the resistor R 19 . The drain of the second FET Q 2 is further electrically connected to the reset signal port 25 of the computer 20 to transmit the command signals to the computer 20 , for resetting the computer 20 .

In use, when any one switch among the switch module S 0 -S 2 is pressed, the corresponding encoding input port among DA 0 -DA 2 receives a logical combination, such as 001 or 010. Then the encoder U 1 encodes the logical combinations to generate corresponding address codes and data codes, and the LED D 0 transmits the address codes and the data codes to the infrared receiving circuit 211 in the form of infrared signals. The infrared probe U 2 of the infrared receiving circuit 211 receives and decodes the encoded infrared signals, and the decoded infrared signals are transmitted to the control circuit 213 through the second address ports B 0 -B 8 and the decoding output ports DB 0 -DB 2 . The control circuit 213 receives the decoded infrared signals and outputs corresponding command signals based on the corresponding logical combination to control the computer 20 . For example, when the infrared receiving circuit 211 receives the logical code 001, namely, the switch S 0 is pressed, then the control circuit 213 outputs a corresponding command signal according to the logical code 001 to the power on/off circuit 215 . Thus, the computer 20 is powered on according to the command signal.

In summary, in this exemplary embodiment, the resistors R 9 -R 19 , the capacitor CR, and the diodes D 1 -D 3 can be omitted.

In the infrared control system 100 of the exemplary embodiment, the infrared control unit 10 encodes different infrared signals and outputs the encoded infrared signals to the computer 20 , the infrared receiving circuit 211 of the computer 20 receives and decodes the infrared signals. Thus, the control circuit 213 of the computer 20 receives the decoded infrared signals from the infrared receiving circuit 211 to generate corresponding command signals, resulting in powering computer 20 on/off or resetting the computer 20 .

It is to be understood, however, that even though numerous characteristics and advantages of the exemplary disclosure have been set forth in the foregoing description, together with details of the structure and function of the exemplary disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of exemplary disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.