Programming method for flash memory device

This application claims the benefit of Korean Patent Application No. 10-2009-0041763, filed May 13, 2009, the contents of which are hereby incorporated herein by reference.

The inventive concept relates to a flash memory device such as a solid state disk (SSD) or a flash memory card, and more particularly, to a programming method for a flash memory device.

Generally, a flash memory device has a function of electrically erasing all data of a cell at once, and thus is widely used in computers and memory cards. Recently, as use of mobile information devices, such as cell phones, personal digital assistants (PDAs), and digital cameras, is rapidly increasing, the flash memory device, instead of a hard disk, is widely used as a storage device. The mobile information devices require high capacity storage devices in order to provide various functions. Accordingly, a flash memory device that can store multi-bit data of 2 bits or more in one memory cell has being suggested.

According to an aspect of the inventive concept, there is provided a programming method for a flash memory device that includes a plurality of banks including a plurality of memory cells for storing multi-bit data, the programming method including: programming a most significant bit (MSB) page with respect to banks of a first bank group; programming a least significant bit (LSB) page with respect to banks of a second bank group; programming the MSB page with respect to the banks of the second bank group; and programming the LSB page with respect to the banks of the first bank group.

The programming method may further include repeatedly performing the programming of the MSB page with respect to the first bank group, the programming of the LSB page with respect to the second bank group, the programming of the MSB page with respect to the second bank group, and the programming of the LSB page with respect to the first bank group, until a program of the flash memory device is completed.

According to another aspect of the inventive concept, there is provided a programming method for a flash memory device that includes a plurality of banks including a plurality of memory cells for storing multi-bit data, the programming method including: programming a least significant bit (LSB) page with respect to a first bank group; programming a most significant bit (MSB) page with respect to the first bank group; programming the LSB page with respect to a second bank group; and programming the MSB page with respect to the second bank group.

The programming method may further include repeatedly performing the programming of the LSB page with respect to the first bank group, the programming of the MSB page with respect to the first bank group, the programming of the LSB page with respect to the second bank group, and the programming of the MSB page with respect to the second bank group, until a program of the flash memory device is completed.

FIG. 1 is a block diagram of a flash memory device, according to an embodiment of the inventive concept;

FIG. 2 is a circuit diagram of a first bank of FIG. 1 ;

FIG. 3A is a diagram for describing an operation of programming a least significant bit (LSB) page;

FIG. 3B is a diagram for describing an operation of programming a most significant bit (MSB) page;

FIG. 4 is a flowchart illustrating a programming method for a flash memory device, according to an embodiment of the inventive concept;

FIG. 5 is a table for describing the programming method of FIG. 4 ;

FIG. 6 is a flowchart illustrating a programming method for a flash memory device, according to another embodiment of the inventive concept; and

FIG. 7 is a table for describing the programming method of FIG. 6 .

The attached drawings for illustrating exemplary embodiments of the inventive concept are referred to in order to gain a sufficient understanding of the exemplary embodiments, the merits thereof, and the objectives accomplished by the implementation of the exemplary embodiments. Hereinafter, the exemplary embodiments will be described in detail with reference to the attached drawings. Like reference numerals in the drawings denote like elements.

FIG. 1 is a block diagram of a flash memory device 100 , according to an embodiment of the inventive concept. Referring to FIG. 1 , the flash memory device 100 may include first through n-th banks B 1 through Bn, wherein n is an integer greater than one. The first through n-th banks B 1 through Bn each include a plurality of memory cells for storing multi-bit data, and are connected via a channel CH. For example, when data DATA is to be stored in a corresponding bank from among the first through n-th banks B 1 through Bn, data DATA corresponding to the first bank B 1 is transmitted so as to program memory cells of the first bank B 1 , and then data DATA corresponding to the second bank B 2 is transmitted so as to program memory cells of the second bank B 2 . The corresponding data DATA is transmitted to the third banks through n-th banks B 3 through Bn in the same manner.

FIG. 2 is a circuit diagram of the first bank B 1 of FIG. 1 . For convenience, FIG. 2 illustrates the first bank B 1 of FIG. 1 , but the second through n-th banks B 2 through Bn may have the same structure as the first bank B 1 of FIG. 2 . Referring to FIGS. 1 and 2 , the first bank B 1 includes a plurality of strings, and each string may include a string selection transistor SST, a ground selection transistor GST, and memory cells MC 0 through MC 31 . The string selection transistor SST may have a gate connected to a string selection line SSL, and a first terminal connected to a corresponding bit line. The ground selection transistor GST may have a gate connected to a ground selection line GSL, and a first terminal connected to a common source line CSL. The memory cells MC 0 through MC 31 may be interposed between a second terminal of the string selection transistor SST and a second terminal of the ground selection transistor GST, and have gates respectively connected to corresponding word lines WL 0 through WL 31 . A plurality of bit line pairs (BLe 0 , BLo 0 ) through (BLe(n-1), BLo(n-1)) may be arranged to cross the word lines WL 0 through WL 31 . During a reading/programming operation, one bit line may be selected from among each of the bit line pairs (BLe 0 , BLo 0 ) through (BLe(n-1), BLo(n-1)), and thus two pages may be formed with respect to one word line. However, one page may be formed with respect to one word line.

A programming operation for storing 2 bits of data may be divided into an operation of programming a least significant bit (LSB) page, and an operation of programming a most significant bit (MSB) page. The operations of programming the LSB page and the MSB page will now be described with respect to FIGS. 3A and 3B .

FIG. 3A is a diagram for describing an operation of programming a LSB page, and FIG. 3B is a diagram for describing an operation of programming a MSB page.

One memory cell may be programmed to have one state selected from the group of “11”, “10”, “00”, and “01” states. Hereinafter, it is assumed that a memory cell having the “11” state is an erased memory cell, the threshold voltage of a memory cell having the “10” state is higher than the threshold voltage of a memory cell having the “11” state, the threshold voltage of a memory cell having the “00” state is higher than the threshold voltage of the memory cell having the “10” state, and the threshold voltage of the memory cell having the “01” state is higher than the threshold voltage of the memory cell having the “00” state.

Here, when the LSB page is programmed with respect to the memory cell having the “11” state, the memory cell is changed to having the erased state or the “10” state, as shown in FIG. 3A . When the MSB page is programmed with respect to the memory cell having the “10” state, the memory cell is changed to having the “10” or the “00” state as shown in FIG. 3B , and when the MSB page is programmed with respect to the memory cell having the “11” state, the memory cell is changed to having the erased state or the “01” state as shown in FIG. 3B .

FIG. 4 is a flowchart illustrating a programming method for a flash memory device, according to an embodiment of the inventive concept. Referring to FIG. 4 , an MSB page is programmed with respect to banks of a first bank group in operation S 410 , and an LSB page is programmed with respect to banks of a second bank group in operation S 420 . The first bank group includes at least one bank including a plurality of memory cells for storing multi-bit data. The second bank group includes at least one bank that includes a plurality of memory cells for storing multi-bit data and is not included in the first bank group. For example, when the flash memory device includes 2 n banks, wherein n is a natural number, the first bank group may include n banks, and the second bank group may include the remaining n banks that are not included in the first bank group. After operation S 420 , the MSB page is programmed with respect to the banks of the second bank group in operation S 430 . After operation S 430 , the LSB page is programmed with respect to the banks of the first bank group in operation S 440 . Next, it is determined whether a program of the flash memory device is completed in operation S 450 . If the program is not completed, operations S 410 through S 440 are performed.

FIG. 5 is a table for describing the programming method of FIG. 4 . The programming method for a flash memory device including a first through fourth banks B 1 through B 4 will now be described with reference to FIGS. 4 and 5 . Here, the number of banks is not limited to 4, and the programming method of FIG. 4 may be applied to a flash memory device including a different number of banks. According to an embodiment of the inventive concept, it is assumed that the first bank group includes the first and second banks B 1 and B 2 , and the second bank group includes the third and fourth banks B 3 and B 4 .

First in operation S 410 , the MSB page is programmed with respect to the first and second banks B 1 and B 2 included in the first bank group. In FIG. 5 , the MSB page is programmed with respect to the first bank B 1 , and then the MSB page is programmed with respect to the second bank B 2 . Then, in operation S 420 , the LSB page is programmed with respect to the third and fourth banks B 3 and B 4 included in the second bank group. In FIG. 5 , the LSB page is programmed with respect to the third bank B 3 , and then the LSB page is programmed with respect to the fourth bank B 4 .

In operation S 430 , the MSB page is programmed with respect to the third and fourth banks B 3 and B 4 included in the second bank group. Here, the MSB page may be programmed with respect to the third and fourth banks B 3 and B 4 included in the second bank group in the order of programming the LSB page in operation S 420 . In other words, since the LSB page is programmed with respect to the third bank B 3 and then with respect to the fourth bank B 4 in operation S 420 , the MSB page may be programmed with respect to the third bank B 3 and then with respect to the fourth bank B 4 in operation S 430 according to the order of operation S 420 .

In operation S 440 , the LSB page is programmed with respect to the first and second banks B 1 and B 2 included in the first bank group. Here, the LSB page may be programmed with respect to the first and second banks B 1 and B 2 included in the first bank group in the order of programming the MSB page in operation S 410 . In other words, since the MSB page is programmed with respect to the first bank B 1 and then with respect to the second bank B 2 in operation S 410 , the LSB page may be programmed with respect to the first bank B 1 and then with respect to the second bank B 2 in operation S 440 according to the order of operation S 410 .

If it is determined that the program is not completed in operation S 450 , operation S 410 is performed, and thus the MSB page is programmed with respect to the first and second banks B 1 and B 2 included in the first bank group. Here, the MSB page may be programmed with respect to the first and second banks B 1 and B 2 included in the first bank group in the order of programming the LSB page in operation S 440 . In other words, since the LSB page is programmed with respect to the first bank B 1 and then with respect to the second bank B 2 in operation S 440 , the MSB page may be programmed with respect to the first bank B 1 , and then with respect to the second bank B 2 in operation S 410 according to the order of operation S 440 .

In operation S 420 , the LBS page is programmed with respect to the third and fourth banks B 3 and B 4 included in the second bank group. Here, the LSB page may be programmed with respect to the third and fourth banks B 3 and B 4 included in the second bank group in the order of programming the MSB page in operation S 430 . In other words, since the MSB page is programmed with respect to the third bank B 3 and then with respect to the fourth bank B 4 in operation S 430 , the LSB page may be programmed with respect to the third bank B 3 , and then with respect to the fourth bank B 4 in operation S 420 according to the order of operation S 430 .

Operations thereafter are performed in the same manner as the operations described above, and thus details thereof are not repeated herein.

FIG. 6 is a flowchart illustrating a programming method for a flash memory device, according to another embodiment of the inventive concept.

Referring to FIG. 6 , the programming method programs an LSB page with respect to banks of a first bank group in operation S 610 , and then programs an MSB page with respect to the banks of the first bank group in operation S 620 . The first bank group includes at least one bank including a plurality of memory cells for storing multi-bit data. The second bank group includes at least one bank that includes a plurality of memory cells for storing multi-bit data and is not included in the first bank group. For example, when the flash memory device includes 2 n banks, wherein n is a natural number, the first bank group may include n banks, and the second bank group may include the remaining n banks that are not included in the first bank group. After operation S 620 , the LSB page is programmed with respect to the banks of the second bank group in operation S 630 , and the MSB page is programmed with respect to the banks of the second bank group in operation S 640 . Then, it is determined whether a program of the flash memory device is completed in operation S 650 . If the program is not completed, operations S 610 through S 640 are performed.

FIG. 7 is a table for describing the programming method of FIG. 6 .

The programming method for a flash memory device including first through fourth banks B 1 through B 4 will now be described with reference to FIGS. 6 and 7 . However, as described above with reference to FIGS. 4 and 5 , the number of banks is not limited to 4, and the programming method of FIG. 6 may be applied to a flash memory device including a different number of banks. In FIG. 7 , the first bank group includes the first and third banks B 1 and B 3 , and the second bank group includes the second and fourth banks B 2 and B 4 .

First, the LSB page is programmed with respect to the first and third banks B 1 and B 3 included in the first bank group in operation S 610 . In FIG. 7 , the LSB page is programmed with respect to the first bank B 1 , and then with respect to the third bank B 3 .

In operation S 620 , the MSB page is programmed with respect to the first and third banks B 1 and B 3 included in the first bank group. Here, the MSB page may be programmed with respect to the first and third banks B 1 and B 3 included in the first bank group in the order of programming the LSB page in operation S 610 . In other words, since the LSB page is programmed with respect to the first bank B 1 and then with respect to the third bank B 3 in operation S 610 , the MSB page may be programmed with respect to the first bank B 1 and then with respect to the third bank B 3 in operation S 620 according to the order of operation S 610 .

In operation S 630 , the LSB page is programmed with respect to the second and fourth banks B 2 and B 4 included in the second bank group. In FIG. 7 , the LSB page is programmed with respect to the second bank B 2 , and then programmed with respect to the fourth bank B 4 .

In operation S 640 , the MSB page is programmed with respect to the second and fourth banks B 2 and B 4 included in the second bank group. Here, the MSB page may be programmed with respect to the second and fourth banks B 2 and B 4 included in the second bank group in the order of programming the LSB page in operation S 630 . In other words, since the LSB page is programmed with respect to the second bank B 2 and then with respect to the fourth bank B 4 in operation S 630 , the MSB page may be programmed with respect to the second bank B 2 and then with respect to the fourth bank B 4 in operation S 640 according to the order of operation S 630 .

If it is determined that the program is not completed in operation S 650 , operation S 610 is performed, and thus the LSB page is programmed with respect to the first and third banks B 1 and B 3 included in the first bank group. Here, the LSB page may be programmed with respect to the first and third banks B 1 and B 3 included in the first bank group in the order of programming the MSB page in operation S 620 . In other words, since the MSB page is programmed with respect to the first bank B 1 and then with respect to the third bank B 3 in operation S 620 , the LSB page may be programmed with respect to the first bank B 1 and then with respect to the third bank B 3 in operation S 610 according to the order of operation S 620 .

In operation S 620 , the MSB page is programmed with respect to the first and third banks B 1 and B 3 included in the first bank group. Here, as described above, since the LSB page is programmed with respect to the first bank B 1 and then with respect to the third bank B 3 in operation S 610 , the MSB page may be programmed with respect to the first bank B 1 and then with respect to the third bank B 3 in operation S 620 according to the order of operation S 610 .

In operation S 630 , the LSB page may be programmed with respect to the second and fourth banks B 2 and B 4 included in the second bank group. Here, the LSB page may be programmed with respect to the second and fourth banks B 2 and B 4 included in the second bank group in the order of programming the MSB page in operation S 640 . In other words, since the MSB page is programmed with respect to the second bank B 2 and then with respect to the fourth bank B 4 in operation S 640 , the LSB page may be programmed with respect to the second bank B 2 and then with respect to the fourth bank B 4 in operation S 630 according to the order of operation S 640 .

In operation S 640 , the MSB page is programmed with respect to the second and fourth banks B 2 and B 4 included in the second bank group. Here, as described above, since the LSB page is programmed with respect to the second bank B 2 and then with respect to the fourth bank B 4 in operation S 630 , the MSB page may be programmed with respect to the second bank B 2 and then with respect to the fourth bank B 4 in operation S 640 according to the order of operation S 630 .

Operations thereafter are performed in the same manner as the operations described above, and thus details thereof are not repeated herein.

As described above, when a flash memory device is programmed according to an embodiment of the inventive concept, a time after programming an LSB page until programming an MSB page is shorter than a time after programming the MSB page until programming the LSB page, and thus channel waste may be reduced. This is because in the flash memory device, the time consumed to program the MSB page is longer than a time consumed to program the LSB page.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.