Electronic device with optical module

1. Technical Field

The present disclosure relates to electronic devices, and more particularly to an electronic device with an optical module.

2. Description of Related Art

Electronic devices such as media players, often use an optical module to write/read information to/from optical media. However, upon powering up, the optical module may receive transient high-voltage from the power supply/source. As such, damage may result, and service life of the optical module be decreased.

Therefore, there is room for improvement in the art.

Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the two views.

FIG. 1 is a schematic, functional block diagram of an electronic device, in accordance with an exemplary embodiment.

FIG. 2 is a partial circuit diagram of the electronic device of FIG. 1 .

Referring to FIG. 1 , an electronic device 100 according to an exemplary embodiment is illustrated. The electronic device 100 , such as an optical media player, includes an optical module 10 , a processor 20 , a power source module 30 , a controller 40 , and a switch module 50 .

The optical module 10 is configured for writing information to an optical medium (not shown), and reading information from the optical medium. In this embodiment, the optical module 10 is an optical pickup head (OPU). The OPU emits light to the medium and receives the light reflected from the medium, so as to write/read information to/from the medium. When the medium is a compact disc (CD), the OPU emits infrared laser light with a wave length of 780 nanometer (nm). When the medium is a digital video disc (DVD), the OPU emits red laser light with a wave length of 650 nm.

The power source module 30 is configured for powering the optical module 10 .

The processor 20 is configured for receiving operational commands, and generating a driving signal accordingly. In response to the operational commands, the processor 20 is further configured for recognizing the medium to be read or written to. When the medium is a CD, the processor 20 generates a first driving signal. When the medium is a DVD, the processor 20 generates a second driving signal. In this embodiment, the driving signal (the first driving signal and the second driving signal) is a low level signal. The processor 20 is further configured for receiving feedback from the optical module 10 , and adjusting the operation of the optical module 10 accordingly.

The processor 20 includes a delay module 24 . The delay module 24 is configured for generating and maintaining output of a delay signal for a first predetermined time in response to the determination that the power source module 30 is powered on. The processor 20 generates the driving signal upon determination that the first predetermined time has elapsed. After the first predetermined time, the delay signal terminates and the processor 20 outputs the driving signal. The first predetermined time can be modified by the delay module 24 . In this embodiment, the delay module 24 is a procedure embedded in the processor 20 , and the first predetermined time is stored in the processor 20 as a factory set value. In other embodiments, the delay module 24 can be a circuit with delay function.

Further referring to FIG. 2 , the controller 40 is configured for generating and maintaining output of a control signal for a second predetermined time in response to determination that the power source module 30 is powered on. The controller 40 includes a maintaining unit 41 . The maintaining unit 41 is configured for maintaining the output of the control signal for the second predetermined time. The control signal terminates upon determination that the second predetermined time has elapsed. The second predetermined time can be modified by the maintaining unit 41 . In this embodiment, the second predetermined time is a factory set value.

The switch module 50 is configured for enabling an electrical connection between the power source module 30 and the optical module 10 when the switch module 50 is turned on, and further for disabling the electrical connection between the power source module 30 and the optical module 10 when the switch module 50 is turned off. The switch module 50 is turned on according to the driving signal and turned off according to the control signal.

As discussed, the switch module 50 is turned off according to the control signal generated by the controller 40 in response to determination that the power source module 30 is powered on. The processor 20 delays output of the driving signal according to the delay signal generated by the delay module 24 . After the two predetermined times, the control signal and the delay signal terminate, and the processor 20 outputs the driving signal to the switch module 50 . The switch module 50 is turned on to enable the electrical connection between the power source module 30 and the optical module 10 , and the optical module 10 is powered by the power source module 30 .

In this embodiment, the processor 20 is a digital signal processing (DSP) chip. The processor 20 includes a first pin 21 , a second pin 22 , and a third pin 23 . The first pin 21 outputs the first driving signal. The second pin 22 outputs the second driving signal. The third pin 23 receives the feedback from the optical module 10 . The power source module 30 includes a power source Vcc.

The controller 40 includes a first transistor Q 1 , a second transistor Q 2 , a first delay circuit 42 , and a second delay circuit 44 . The maintaining unit 41 consists of the first delay circuit 42 and the second delay circuit 44 . The first delay circuit 42 delays the first control signal as an input of the first transistor Q 1 for the second predetermined time. The first delay circuit 42 includes a first resistor R 1 and a first capacitor C 1 . The second delay circuit 42 delays the second control signal as an input of the second transistor Q 2 for the second predetermined time. The second delay circuit 44 includes a second resistor R 2 and a second capacitor C 2 .

One terminal of the first resistor R 1 is electrically connected to the power source Vcc. The other terminal of the first resistor R 1 is electrically grounded via the first capacitor C 1 . One terminal of the second resistor R 2 is electrically connected to the power source Vcc. The other terminal of the second resistor R 2 is electrically grounded via the second capacitor C 2 . A base of the first transistor Q 1 is electrically connected to the first resistor R 1 and the first capacitor C 1 . A collector of the first transistor Q 1 is electrically connected to the first pin 21 . An emitter of the first transistor Q 1 is electrically connected to the power source Vcc. A base of the second transistor Q 2 is electrically connected to the second resistor R 2 and the second capacitor C 2 . A collector of the second transistor Q 2 is electrically connected to the second pin 22 . An emitter of the second transistor Q 2 is electrically connected to the power source Vcc.

The switch module 50 includes a third transistor Q 3 , a fourth transistor Q 4 , a third resistor R 3 , a fourth resistor R 4 , a third capacitor C 3 , and a fourth capacitor C 4 . A base of the third transistor Q 3 is electrically connected to the first pin 21 . A collector of the third transistor Q 3 is electrically connected to the optical module 10 . An emitter of the third transistor Q 3 is electrically connected to the power source Vcc via the third resistor R 3 . One terminal of the third capacitor C 3 is electrically connected to the base of the third transistor Q 3 . The other terminal of the third capacitor C 3 is electrically connected to the power source Vcc. Abase of the fourth transistor Q 4 is electrically connected to the second pin 22 . A collector of the fourth transistor Q 4 is electrically connected to the optical module 10 . An emitter of the fourth transistor Q 4 is electrically connected to the power source Vcc via the fourth resistor R 4 . One terminal of the fourth capacitor C 4 is electrically connected to the base of the fourth transistor Q 4 . The other terminal of the fourth capacitor C 4 is electrically connected to the power source Vcc.

In this embodiment, the four transistors Q 1 , Q 2 , Q 3 , and Q 4 are PNP type bipolar junction transistors. The four resistors R 1 , R 2 , R 3 , and R 4 are configured for controlling current. The two capacitors C 1 and C 2 are configured for generating the second predetermined time for the two delay circuits 41 and 42 , respectively. The two capacitors C 3 and C 4 are used for straightening at bypass.

In this embodiment, the two pins 21 and 22 have the same working principle, and the working principle of the first pin 21 follows.

When the power source Vcc is enabled, the first capacitor C 1 is charged to behave similar to be shorted, and the delay unit 24 of the processor 20 continues to generate the delay signal for the first predetermined time. The processor 20 delays output of the first driving signal according to the delay signal generated for the first predetermined time.

The base of the first transistor Q 1 is at a low level voltage by the first capacitor C 1 which is electrically grounded. The emitter of the first transistor Q 1 is at a high level voltage by the power source Vcc. Thus, the base-emitter voltage of the first transistor Q 1 exceeds a breakover voltage of the first transistor Q 1 . The first transistor Q 1 turns on. The collector of the first transistor Q 1 outputs a high level voltage to the base of the third transistor Q 3 . The emitter of the third transistor Q 3 receives a high level voltage supported by the power source Vcc. Thus, the base-emitter voltage of the third transistor Q 3 falls below a breakover voltage of the third transistor Q 3 . The third transistor Q 3 turns off.

Thus, the third transistor Q 3 disables the electrical connection between the power source Vcc and the optical module 10 in response to determination that the power source module 30 is powered on. The optical module 10 avoids encountering high-voltage transients from the power source Vcc.

As the first capacitor C 1 is charged for the second predetermined time, the base voltage of the first transistor Q 1 becomes so great that the base-emitter voltage of the first transistor Q 1 falls below the breakover voltage of the first transistor Q 1 . The first transistor Q 1 turns off. The delay signal terminates upon determination that the first predetermined time has elapsed, and the processor 20 outputs the first driving signal to the base of the third transistor Q 3 . Thus, the base-emitter voltage of the third transistor Q 3 exceeds the breakover voltage of the third transistor Q 3 . The third transistor Q 3 turns on to enable the electrical connection between the power source Vcc and the optical module 10 . The optical module 10 is powered by the power source module 30 .

In other embodiments, the four transistors Q 1 , Q 2 , Q 3 , and Q 4 can be other electrical switches, such as metal oxide semiconductor (MOS) transistors.

It is to be understood, however, that even though numerous embodiments have been described with reference to particular embodiments, but the present disclosure is not limited to the particular embodiments described and exemplified, and the embodiments are capable of considerable variation and modification without departure from the scope of the appended claims.