Switching power supply

1. Field of the Disclosure

Embodiments of the present disclosure relate to switching power supplies.

2. Description of Related Art

Transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are widely used in modern switching power supplies. Typically, a control circuit which generates a square wave signal is used to drive the MOSFET. The square wave signal alternates regularly between two levels: a high level and a low level. When the high level is applied to the MOSFET, the MOSFET is turned on. When the low level is applied to the MOSFET, the MOSFET is turned off. The ratio of the duration of the high level to that of the low level, namely, the pulse duration ratio, determines the output voltage of the switching power supply. The greater the pulse duration ratio, the greater the output voltage is.

Typically, a feedback circuit is utilized to feedback the output voltage to the control circuit. The control circuit adjusts the pulse duration ratio automatically according to the feedback voltage. However, when the feedback circuit is broken or damaged, the feedback signal may be incorrect. As a result, the pulse duration ratio may be too great to give the wrong output voltage, and may even damage the MOSFET.

Therefore, a switching power supply having an improved driving circuit for a transistor is needed to address the aforementioned deficiency and inadequacies.

Many aspects of the embodiments can be better understood with references to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block diagram of switching power supply in accordance with a first embodiment.

FIGS. 2 a - 2 c are graphs of three waveforms generated by the switching power supply of FIG. 1 .

FIG. 3 is a block diagram of switching power supply in accordance with a second embodiment.

FIG. 4 is a circuit diagram of the switching power supply of FIG. 3 .

FIGS. 5 a - 5 c are graphs of three waveforms generated by the switching power supply of FIG. 4 .

References will now be made to the drawings to describe certain inventive embodiments of the present disclosure.

Referring to FIG. 1 , a switching power supply 100 in accordance with an exemplary embodiment includes a switching unit M 1 , a driving signal generator 102 , a control circuit 104 , and a primary power supply 106 . The switching unit M 1 is an N-Channel enhancement type metal oxide semiconductor field effect transistor (MOSFET). In other embodiments, the switching unit M 1 may be a bipolar junction transistor. The primary power supply 106 is connected to the drain of the MOSFET to power the MOSFET, and control the value of a current Id that flows through the source and drain of the MOSFET when the MOSFET turns on.

The driving signal generator 102 is operable to supply a first driving signal Vi for the MOSFET. Referring further to FIG. 2 , in the embodiment, the first driving signal Vi is a square wave signal which alternates regularly between a high level voltage Vss and a low level voltage. The low level voltage may be lower than 0.7V. As the switching unit M 1 is an N-Channel enhancement type MOSFET, the acting voltage parts, those can turn on the MOSFET, of the first driving signal are the high level voltage Vss. In other embodiments, the acting voltage parts may be the low level voltage when the switching unit M 1 is a P-Channel MOSFET.

The control circuit 104 is electrically connected between the driving signal generator 102 and the MOSFET. The control circuit 104 is configured to receive the driving signal Vi and generate a second driving signal Vg according to the first driving signal Vi. The second driving signal Vg is also a kind of pulse signals. Each of the pulses of the second driving signal Vg includes a high voltage part and a low voltage part. The high voltage part starts with a high voltage that equals to the high level voltage Vss and falls down from the high voltage to a low voltage Vt after a preset time period. The low voltage part starts with the low voltage Vt, and may finally fall to zero. The MOSFET is turned on when receiving the high voltage part of the second driving signal Vg, and is turned off when receiving the low voltage part.

In the embodiment, the control circuit 104 includes a capacitor C 1 , a first resistor R 1 , and a second resistor R 2 . The capacitor C 1 is connected between the driving signal generator 102 and the gate of the MOSFET. A terminal of the first resistor R 1 is connected to the gate of the MOSFET. The other terminal of the first resistor R 1 is connected to a terminal of the second resistor R 2 and the source of the MOSFET. The other terminal of the second resistor R 2 is grounded. The capacitor C 1 is adjustable.

Referring to FIG. 2 , when the first driving signal Vi becomes the high level voltage Vss from the low level voltage at time point t 0 , the capacitor C 1 is charged, and the high level voltage Vss is conducted to the gate of the MOSFET. Thus, a voltage at the gate of the MOSFET, that is the second driving signal Vg, becomes a high voltage at the time point t 0 . The MOSFET is turned on. After that, a voltage Vc 1 across the capacitor C 1 increases, while the second driving signal Vg decreases. When the voltage Vc 1 across the capacitor C 1 is higher than Vss-Vt (Vt is the threshold voltage of the MOSFET), and the second driving signal Vg is lower than Vt at the time point t 1 , the MOSFET is turned off.

To summarize, when a duration of a high level voltage of the first driving signal Vi is longer than the time period t 1 -t 0 and the time period t 1 -t 0 ends, the MOSFET will be turned off by the control circuit 104 . When the duration of each high level voltage of the first driving signal Vi is shorter than or equal to the time period t 1 -t 0 , and the high level voltage of the first driving signal Vi ends, the MOSFET will be turned off, thus the control circuit 104 will not diminish the effectiveness of the first driving signal Vi. Therefore, the MOSFET will not be damaged due to long-duration high level voltages of the first driving signal Vi. The time period t 1 -t 0 is adjustable to meet different design demands by adjusting the capacitor C 1 .

Referring to FIGS. 3-4 , in a second embodiment, a switching power supply 200 is used for receiving an alternating current (AC) voltage from an AC power supply 300 , and converting the received AC voltage into a second direct current (DC) voltage to power a load 400 . The switching power supply 200 includes a first rectifier and filter circuit 12 , a pulse-width modulation (PWM) circuit 14 , a control circuit 15 , a converting circuit 16 , and a second rectifier and filter circuit 20 .

The first rectifier and filter circuit 12 is configured to convert the received AC voltage to a first DC voltage, and filtering the first DC voltage. The first rectifier and filter circuit 12 may include a full-bridge rectifier and at least one filtering capacitor.

The PWM circuit 14 is configured to receive the first DC voltage and supply a pulse signal to the control circuit 15 . The PWM circuit 14 may include a PWM chip. The first DC voltage may be used to start up the PWM chip. The pulse signal is a square wave signal which alternates regularly between a high level voltage and a low level voltage. The low level voltage is lower than the threshold voltage of the transistor M 2 .

The converting circuit 16 is configured to convert the first DC voltage to the second DC voltage to power the load 400 according to the pulse signal. The converting circuit 16 includes a transistor M 2 . In the embodiment, the transistor M 2 is an N-Channel enhancement type metal oxide semiconductor field effect transistor (MOSFET). In other embodiments, the transistor M 2 may be a bipolar junction transistor. In the embodiment, the converting circuit 16 further includes a transformer T 1 . The transformer T 1 includes a primary winding L 1 , and a secondary winding L 2 connected to the second rectifier and filter circuit 20 . A terminal of the primary winding L 1 is connected to the first rectifier and filter circuit 12 to receive the first DC voltage. The other terminal of the primary winding L 1 is connected to the drain of the transistor M 2 . When the transistor M 2 is turned on, a varying current flows through the primary winding L 1 , and the secondary winding L 2 generates an inductive voltage, the second DC voltage in the embodiment.

The second rectifier and filter circuit 20 is configured to rectify and filter the second DC voltage to make the second DC voltage smoother.

The control circuit 15 is connected between the PWM circuit 14 and the gate of the transistor M 2 . The control circuit 15 is configured to turn off the transistor M 2 when a duration of a pulse of the pulse signal is longer than a preset time period. When the duration of the pulse is shorter than or equal to the preset time period, the transistor M 2 is turned off when the pulse ends. In the embodiment, the structure of the control circuit 15 is similar to that of the control circuit 104 in the first embodiment. The control circuit 15 includes a capacitor C 2 , a third resistor R 3 , and a fourth resistor R 4 . The capacitor C 2 is connected between the PWM circuit 14 and the gate of the transistor M 2 . A terminal of the third resistor R 3 is connected to the gate of the transistor M 2 . The other terminal of the third resistor R 3 is connected to a terminal of the fourth resistor R 4 and the source of the transistor M 2 . The other terminal of the fourth resistor R 4 is grounded. The capacitor C 2 is adjustable.

Referring to FIG. 5 , a voltage across the capacitor C 2 is labeled as Vc 2 . A voltage at the gate of the transistor M 2 is labeled as Vg 2 . When the pulse signal becomes a high level voltage Vss 2 from the low level voltage at time point t 2 , the capacitor C 2 is charged, and the high level voltage Vss 2 is conducted to the gate of the transistor M 2 . The transistor M 2 is turned on. After that, the voltage Vc 2 across the capacitor C 2 increases, while the voltage Vg 2 decreases. When the voltage Vc 2 is higher than Vss 2 -Vt 2 (Vt 2 is the threshold voltage of the transistor M 2 ), and the voltage Vg 2 is lower than Vt at the time point t 3 , the transistor M 2 is turned off.

To summarize, when a duration of a pulse of the pulse signal is longer than the time period t 2 -t 3 and the time period t 2 -t 3 ends, the transistor M 2 will be turned off by the control circuit 15 . When the duration of the pulse is shorter than or equal to the time period t 2 -t 3 and the pulse ends, the transistor M 2 will be turned off, and the control circuit 15 will not diminish the effectiveness of the pulse signal. Therefore, the transistor M 2 will not be damaged due to long-duration pulses of the pulse signal. The time period t 3 -t 2 is adjustable to meet different design demands by adjusting the capacitor C 2 .

It is to be understood, however, that even though numerous characteristics and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the present disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.