Power supply circuit for CPU

1. Technical Field

The present disclosure relates to power supply, and particularly to a power supply circuit for a CPU (central processing unit).

2. Description of Related Art

With the rapid development of personal computers, development of high performance components for computers has brought about a corresponding increase in power use. A CPU has a crucial effect on the stability of a computer. A power supply circuit is specially designed for providing power to the CPU.

Referring to FIG. 1 , a commonly used power supply circuit for a CPU includes a PWM (pulse-width modulation) controller 50 which provides three pulse signals of, for example, phase 1 , phase 2 , and phase 3 . Each of the three pulse signals turns a corresponding switch on or off at different times to provide multiphase power to the CPU. The PWM controller 50 is controlled by an I/O controller 40 also electrically coupled to a Southbridge chip 60 . The Southbridge chip 60 provides a 3.3V DC voltage for the I/O controller 40 when the computer is powered off. However, the Southbridge chip 60 is grounded via the CPU and discharges to ground, which generates large amounts of leakage currents on the CPU whereby the computer cannot function.

Therefore, there is room for improvement within the art.

Many aspects of the embodiments can be better understood with references to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block view of a commonly used power supply circuit for a CPU, according to the prior art.

FIG. 2 is a block view of an embodiment of a power supply circuit for a CPU as disclosed.

FIG. 3 is a circuit view of the power supply circuit of FIG. 2 .

The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to FIG. 2 , an embodiment of a power supply circuit for a CPU 30 includes an I/O controller 10 and a PWM controller 20 . The I/O controller 10 is electrically coupled to the CPU 30 via the PWM controller 20 . The I/O controller 10 is configured for receiving voltage selection signals from the CPU 30 , and outputting a control signal to the PWM controller 20 . The PWM controller 20 is configured for adjusting pulse signals provided to the CPU 30 according to the control signal.

Referring to FIG. 3 , the I/O controller 10 includes a plurality of input and output terminals, such as input terminals PD 0 ˜PD 7 for receiving voltage selection signals from the CPU 30 ; control output terminals GPIO 0 ˜GPIO 5 ; and detecting output terminal GPIO 6 , for outputting detection signals to determine whether the CPU 30 is installed in the circuit. In one embodiment, the PWM controller 20 is an ISL6312 series control chip manufactured by Intelsil. The PWM controller 20 includes a plurality of input and output terminals, such as input terminals VID 1 ˜VID 6 and output terminals PHASE 1 , PHASE 2 , PHASE 3 , for providing multiple pulse signals to the CPU 30 . The PWM controller 20 input terminals VID 1 ˜VID 6 are electrically coupled to the I/O controller 10 control output terminals GPIO 0 ˜GPIO 5 respectively. The CPU 30 includes a plurality of input and output terminals, such as input terminal VCCP, status determination terminal AE 8 , and output terminals VID 0 ˜VID 7 for outputting voltage selection signals. The CPU 30 output terminals VID 0 ˜VID 7 are electrically coupled to the I/O controller 10 input terminals PD 0 ˜PD 7 respectively.

In operation, the I/O controller 10 receives the voltage selection signals from the CPU 30 , and outputs a control signal to the PWM controller 20 . The I/O controller 10 is no longer electrically coupled to the Southbridge chip 60 as in the typical power supply circuit. The Southbridge chip 60 cannot discharge via the CPU 30 . The power supply circuit provides power to the CPU 30 smoothly and steadily. The I/O controller 10 outputs detection signals to the CPU 30 , and if the CPU 30 outputs a low level feedback signal to the I/O controller 10 , upon receiving the detection signals, the I/O controller 10 determines that the CPU 30 is installed in the circuit; if the CPU 30 outputs a high level feedback signal to the I/O controller 10 , upon receiving the detection signals, the I/O controller 10 determines that the CPU 30 is not installed in the circuit.

It is to be understood, however, that even though numerous characteristics and advantages of the embodiments have been set forth in the foregoing description, together with details of the structure and function of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.