Analog-to-digital conversion method using RC time constant calibrator and analog-to-digital converter therefor

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0012712, filed on Feb. 17, 2009, the disclosure of which is incorporated herein in its entirety by reference.

1. Technical Field

The present invention relates to an analog-to-digital conversion method, and more particularly, to an analog-to-digital conversion method using, and more particularly, to a method for analog-to-digital conversion using an RC time constant calibrator and an analog-to-digital converter therefor.

2. Discussion of the Related Art

Modem communication systems include microchips containing analog-to-digital converters (ADCs) and filters. The ADCs digitize low-frequency signals such as touch panel signals, backlight brightness control signals for liquid crystal displays (LCDs), and temperature sensor signals. The filters remove unwanted signal components and/or strengthen desired signal components.

The filters use a cut-off frequency to pass those components of the input signal that fall within a particular frequency range and block those components of the input signal that fall outside of the particular frequency range. The cut-off frequency of a filter can be controlled by a time constant. For example, a filter can include an RC time constant calibrator for controlling a time constant. The RC time constant calibrator can control a cut-off frequency that may be affected by an external environment by adjusting resistance and/or capacitance.

However, the RC time constant calibrator is used for a very short time compared to an overall system operating time. For example, the RC time constant calibrator may operate just for a moment when power is turned on in a system or at a predetermined time. In addition, with the compactness of modem chips, the ADC and the RC time constant calibrator are implemented together in a single microchip. As a result, excess layout space is used in accommodating these components.

Some exemplary embodiments of the present invention provide an analog-to-digital conversion method using an RC time constant calibrator.

Some exemplary embodiments of the present invention also provide an analog-to-digital converter for performing the analog-to-digital conversion method.

According to some exemplary embodiments of the present invention, there is provided an analog-to-digital conversion method using an RC time constant calibrator. The method includes the operations of comparing a crossing time point at which a first reference signal and a second reference signal cross each other with a target time point. An RC time constant is calibrated according to a result of the comparison. Counting is performed until a crossing time point at which a first analog signal and a second analog signal cross each other based on a calibrated RC time constant and a count value is outputted.

According to exemplary embodiments of the present invention, there is provided an analog-to-digital converter including a switching unit configured to perform a switching operation according to a control signal and to output a pair of signals forming differential outputs among a plurality of input signals. An RC time constant calibrator is configured to output a count value obtained by counting time elapsed until a crossing time point at which the pair of signals output from the switching unit cross each other based on an RC time constant.

The above and other features and aspects of the exemplary embodiments of the present invention are described in detail below with reference to the attached drawings in which:

FIG. 1 is a schematic block diagram of an analog-to-digital converter (ADC) according to exemplary embodiments of the present invention;

FIG. 2 is a schematic circuit diagram of an RC timer illustrated in FIG. 1 ;

FIG. 3 is a flowchart illustrating the operations of the ADC of FIG. 1 according to exemplary embodiments of the present invention; and

FIG. 4 is a timing chart of the operations illustrated in FIG. 3 .

Exemplary embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers may refer to like elements throughout.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

FIG. 1 is a schematic block diagram of an analog-to-digital converter (ADC) 100 according to exemplary embodiments of the present invention. Referring to FIG. 1 , the ADC 100 includes a switching unit 110 , an RC time constant calibrator 120 , and an inversion unit 130 .

The switching unit 110 performs a switching operation in response to an externally supplied control signal CNT, e.g., from an external controller (not shown). The switching unit 110 outputs differential signals among a plurality of input signals according to the switching operation. For example, the switching unit 110 receives a first reference signal V ref + , a second reference signal V ref − , a first analog signal V in + , and a second analog signal V in − from an external source. The first and second reference signals V ref + and V ref − are differential signals and the first and second analog signals V in + and V in − are differential signals. The first and second reference signals V ref + and V ref − and the first and second analog signals V in + and V in − may be voltage signals. The switching unit 110 outputs differential output voltages, for example, the first and second reference signals V ref + and V ref − or the first and second analog signals V in + and V in − , through a switching operation according to the control signal CNT.

The RC time constant calibrator 120 includes an RC timer 121 and a counter unit 123 . The RC time constant calibrator 120 performs RC time constant calibration based on the first and second reference signals V ref + and V ref − provided from the switching unit 110 or the RC time constant calibrator 120 performs analog-to-digital conversion for generating a digital value based on the first and second analog signals V in + and V in − provided from the switching unit 110 .

For example, the RC timer 121 performs the RC time constant calibration by adjusting a time when the first and second reference signals V ref + and V ref − cross each other according to an RC time constant calibration code C_C 1 output from the counter unit 123 . In addition, the RC timer 121 extracts a time when the first and second analog signals V in + and V in − cross each other according to a calibrated RC time constant and performs the analog-to-digital conversion. The RC timer 121 outputs a hold signal HS at the time when a pair of signals, for example, the first and second reference signals V ref + and V ref − or the first and second analog signals V in + and V in − cross each other.

FIG. 2 is a schematic circuit diagram of the RC timer 121 illustrated in FIG. 1 . Referring to FIG. 2 , the RC timer 121 includes a differential amplifier 240 , a first slope capacitor 260 , a second slope capacitor 270 , a hold signal generator 250 , and a plurality of switches. The plurality of switches include reset switches 211 through 214 , initialization switches 231 through 238 , and operation switches 223 and 224 , respectively. The differential amplifier 240 includes an inverting (−) input terminal, a non-inverting (+) input terminal, an inverting (−) output terminal, and a non-inverting (+) output terminal.

Capacitance of the first slope capacitor 260 and capacitance of the second slope capacitor 270 can be adjusted according to the RC time constant calibration code C_C 1 output from the counter unit 123 . A first end of the first slope capacitor 260 and a first end of the second slope capacitor 270 are connected to the inverting input terminal (−) and the non-inverting input terminal (+), respectively, of the differential amplifier 240 . A second end of the first slope capacitor 260 and a second end of the second slope capacitor 270 are connected to the non-inverting output terminal (+) and the inverting output terminal (−), respectively, of the differential amplifier 240 .

The reset switches 211 through 214 operate in response to a control code, e.g., a reset code φx. The initialization switches 231 through 238 operate in response to another control code, e.g., an initialization code φy. The operation switches 223 and 224 operate in response to another control code, e.g., an operation code φa.

The hold signal generator 250 outputs the hold signal HS at the time when a pair of signals, for example, the first and second reference signals V ref + and V ref − or the first and second analog signals V in + and V in − input to the differential amplifier 240 cross each other according to the operations of the operation switches 223 and 224 . The operation of the RC timer 121 is described in detail below.

Referring back to FIG. 1 , the counter unit 123 generates a plurality of control codes, e.g., the reset code φx, the initialization code φy, and the operation code φa for controlling the RC timer 121 based on an external clock signal, e.g., a reference clock signal CLK. In addition, the counter unit 123 outputs the RC time constant calibration code C_C 1 for the RC time constant calibration or an analog-to-digital converted value C_C 2 ′ based on a count value obtained by counting until the hold signal HS is output by the RC timer 121 , for example, until the time when the pair of signals cross each other. The operation of the counter unit 123 is described in detail below.

The inversion unit 130 inverts the analog-to-digital converted value C_C 2 ′ output from the counter unit 123 and thus outputs an inverted analog-to-digital converted value C_C 2 .

FIG. 3 is a flowchart illustrating the operations of the ADC 100 illustrated in FIG. 1 . FIG. 4 is a timing chart illustrating the operations shown in FIG. 3 . RC time constant calibration (A) and analog-to-digital conversion (B) of the ADC 100 are described in detail below reference to FIGS. 1 through 4 .

Firstly, RC time constant calibration (A) will be described. The switching unit 110 performs a switching operation according to a level of the externally provided control signal CNT and outputs the first and second reference signals V ref + and V ref − which are differential output voltages. For example, the switching unit 110 performs a switching operation according to the control signal CNT at a first level, e.g., a high level, and thus outputs the first and second reference signals V ref + and V ref − .

The counter unit 123 generates the reset code φx, the initialization code φy, and the operation code φa based on the reference clock signal CLK. The codes φx, φy, and φa are provided to the RC timer 121 .

The RC timer 121 controls the operations of the reset switches 211 through 214 according to the reset code φx from the counter unit 123 and initializes the inverting input terminal and the non-inverting input terminal of the differential amplifier 240 to a first reference voltage, e.g., V GND . At this time, the first and second slope capacitors 260 and 270 in the RC timer 121 are discharged. For example, as illustrated in FIG. 4 , when both of the inverting input terminal and the non-inverting input terminal of the differential amplifier 240 receive the first reference voltage V GND , the non-inverting output terminal and the inverting output terminal of the differential amplifier 240 output voltages having the same level, e.g., V DD /2.

Upon receiving the initialization code φy from the counter unit 123 , the RC timer 121 controls the operations of the initialization switches 231 through 238 , maintains the non-inverting output terminal and the inverting input terminal of the differential amplifier 240 at the first reference voltage V GND , and initializes the inverting output terminal and the non-inverting input terminal of the differential amplifier 240 to a second reference voltage, e.g., V DD , that is higher than the first reference voltage V GND . Thereafter, the RC timer 121 charges the first slope capacitor 260 and discharges the second slope capacitor 270 . For example, as illustrated in FIG. 4 , the non-inverting output terminal of the differential amplifier 240 is maintained at the first reference voltage V GND and the inverting output terminal of the differential amplifier 240 is initialized to the second reference voltage V DD .

Upon receiving the operation code φa and the reference clock signal CLK, the RC timer 121 receives the first and second reference signals V ref + and V ref − from the switching unit 110 and integrates them. For example, during a period from a time t 0 to a time t 1 on the time axis “t” illustrated in FIG. 4 , a voltage V DO1 of the non-inverting output terminal of the differential amplifier 240 increases and a voltage V DO2 of the inverting output terminal thereof decreases.

The output voltages V DO1 and V DO2 of the differential amplifier 240 satisfy Equation (1):

V DO ⁢ ⁢ 1 ⁡ ( t ) = V GND + Δ ⁢ ⁢ V RC ⁢ t V DO ⁢ ⁢ 2 ⁡ ( t ) = V VDD - Δ ⁢ ⁢ V RC ⁢ t , ( 1 )

where V DO1 is the voltage of the non-inverting output terminal of the differential amplifier 240 , V DO2 is the voltage of the inverting output terminal of the differential amplifier 240 , and ΔV is a voltage difference satisfying

Accordingly, a time when the voltage V DO1 of the non-inverting output terminal of the differential amplifier 240 crosses the voltage V DO2 of the inverting output terminal thereof satisfies Equation (2):

V DO ⁢ ⁢ 1 ⁡ ( T D ) = V DO2 ⁡ ( T D ) = V GND + Δ ⁢ ⁢ V RC ⁢ T D = V VDD - Δ ⁢ ⁢ V RC ⁢ T D 2 ⁢ Δ ⁢ ⁢ V RC ⁢ T D = V VDD ⁡ ( V GND = 0 ) T D = V VDD 2 ⁢ Δ ⁢ ⁢ V ⁢ RC = V VDD V ref + - V ref - ⁢ RC , ( 2 )

where T D is a time delay value till the time when the first and second reference signals V ref + and V ref − cross each other. As is shown in Equation (2), the time delay value T D till the time when the voltage V DO1 of the non-inverting output terminal of the differential amplifier 240 crosses the voltage V DO2 of the inverting output terminal thereof may be proportional to the capacitance of the first slope capacitor 260 and the capacitance of the second slope capacitor 270 .

For example, an increasing slope of the voltage V DO1 output from the non-inverting output terminal of the differential amplifier 240 may be in inverse proportion to the capacitance of the first slope capacitor 260 and a decreasing slope of the voltage V DO2 output from the inverting output terminal of the differential amplifier 240 may be in inverse proportion to the capacitance of the second slope capacitor 270 . For example, the time when the voltages V DO1 and V DO2 cross each other may be determined based on the product of a calibration constant indicating a ratio between the first and second reference signals V ref + and V ref − and a variable RC time constant controlled according to the RC time constant calibration code C_C 1 output from the counter unit 123 so that the time does not depend upon the change in processes.

The hold signal generator 250 compares a first output signal of the differential amplifier 240 , for example, the voltage V DO1 output from the non-inverting output terminal of the differential amplifier 240 with a second output signal of the differential amplifier 240 , for example, the voltage V DO2 output from the inverting output terminal of the differential amplifier 240 in response to the operation code φa provided from the counter unit 123 and outputs the hold signal HS at a time when the two voltages V DO1 and V DO2 have the same level. For example, the hold signal HS may be output at a time when levels of the first and second output signals of the differential amplifier 240 cross each other (hereinafter, referred to as a crossing time point).

The counter unit 123 compares the crossing time point with a target time point in step S 10 and generates the RC time constant calibration code C_C 1 according to a result of the comparison in step S 20 . For example, the counter unit 123 may receive a target count value T_C corresponding to the target time point from an external source. Thereafter, the counter unit 123 may perform counting from a time when the initialization code φy is output to the RC timer 121 to a time when the RC timer 121 outputs the hold signal HS, for example, during the time delay T D and compare an actual count value resulting from the counting with the target count value T_C in step S 10 .

The counter unit 123 outputs the RC time constant calibration code C_C 1 according to the comparison result. For example, the counter unit 123 may output the RC time constant calibration code C_C 1 that controls the time at which the RC timer 121 outputs the hold signal HS when the actual count value obtained in the time delay T D is greater or less than the target count value T_C. When the actual count value obtained in the time delay T D is the same as the target count value T_C, the counter unit 123 may output the count value as the RC time constant calibration code C_C 1 .

The RC time constant calibration code C_C 1 output from the counter unit 123 is input to the RC timer 121 and changes the capacitance of the first slope capacitor 260 and the capacitance of the second slope capacitor 270 in the RC timer 121 so that an RC time constant is calibrated in step S 30 . For example, the RC timer 121 may control the crossing time point, at which the levels of two voltage signals output from the differential amplifier 240 cross each other, to be the same as the target time point using the first and second slope capacitors 260 and 270 whose capacitance changes according to the RC time constant calibration code C_C 1 provided from the counter unit 123 .

The RC time constant calibration code C_C 1 may be set by the counter unit 123 in order starting with a most significant bit (MSB) to a least significant bit (LSB). Thereafter, when it is determined that the target time point is greater than the crossing time point as a result of comparing the actual count value obtained at the crossing time point with the target count value T_C corresponding to the target time point, the bits set in the RC time constant calibration code C_C 1 may be maintained. When it is determined that the target time point is less than the crossing time point, the bits set in the RC time constant calibration code C_C 1 may be reset.

Referring to FIG. 4 , during the period from the time t 0 to the time t 1 , the counter unit 123 outputs the RC time constant calibration code C_C 1 for controlling the crossing time point of two voltage signals output from the differential amplifier 240 of the RC timer 121 to be the same as the target time point. The RC timer 121 calibrates the RC time constant by changing the capacitance of each of the first and second slope capacitors 260 and 270 according to the RC time constant calibration code C_C 1 output from the counter unit 123 and thus controls the crossing time point to be the same as the target time point.

The above-described operations of outputting the RC time constant calibration code C_C 1 using the counter unit 123 and calibrating the RC time constant using the RC timer 121 are repeated and, when the crossing time point becomes the same as the target time point, for example, at a time t RC on the time axis “t” in FIG. 4 , the counter unit 123 outputs a RC time constant calibration code C_C 1 of “10000”. When the RC time constant calibration (A) is completed through those operations, the RC timer 121 may have the capacitance of the first slope capacitor 260 and the capacitance of the second slope capacitor 270 , which have been fixed by the final RC time constant calibration code C_C 1 of “10000”.

Thereafter, the ADC 100 performs the analog-to-digital conversion (B).

The switching unit 110 performs a switching operation according to the control signal CNT at a second level, e.g., a low level, and thus outputs the first and second analog signals V in + and V in − which are differential output voltages. The counter unit 123 generates the reset code φx, the initialization code φy, and the operation code φa based on the reference clock signal CLK. The codes φx, φy, and φa are provided to the RC timer 121 .

The RC timer 121 detects a crossing time point of the first and second analog signals V in + and V in − provided from the switching unit 110 in step S 110 . For example, the RC timer 121 may initialize the inverting input terminal and the non-inverting input terminal of the differential amplifier 240 to the first reference voltage V GND and discharge the first and second slope capacitors 260 and 270 according to the reset code φx from the counter unit 123 . In addition, according to the initialization code φy, the RC timer 121 may maintain the non-inverting output terminal and the inverting input terminal of the differential amplifier 240 at the first reference voltage V GND and initialize the inverting output terminal and the non-inverting input terminal of the differential amplifier 240 to the second reference voltage V DD higher than the first reference voltage V GND . Thereafter, the RC timer 121 charges the first slope capacitor 260 and discharges the second slope capacitor 270 .

Upon receiving the operation code φa and the reference clock signal CLK, the RC timer 121 receives the first and second analog signals V in + and V in − from the switching unit 110 and integrates them. For example, during a period from the time t 1 to a time t 2 on the time axis “t” illustrated in FIG. 4 , the voltage V DO1 of the non-inverting output terminal of the differential amplifier 240 increases and the voltage V DO2 of the inverting output terminal thereof decreases.

The output voltages V DO1 and V DO2 of the differential amplifier 240 satisfy Equation (1). According to the RC time constant calibrated by the RC time constant calibration code C_C 1 provided from the counter unit 123 through the RC time constant calibration (A), a time when the voltage V DO1 of the non-inverting output terminal of the differential amplifier 240 crosses the voltage V DO2 of the inverting output terminal thereof satisfies Equation (3):

where T AD is a time delay value till the time when the first and second analog signals V in + and V in − cross each other. Since the RC timer 121 has the fixed capacitance, for example, the fixed capacitance of the first slope capacitor 260 and the fixed capacitance of the second slope capacitor 270 according to the RC time constant calibration (A), the crossing time point of the first and second analog signals V in + and V in − may be determined by a difference therebetween.

The hold signal generator 250 of the RC timer 121 compares a first output signal of the differential amplifier 240 , for example, the voltage V DO1 output from the non-inverting output terminal of the differential amplifier 240 with a second output signal of the differential amplifier 240 , for example, the voltage V DO2 output from the inverting output terminal of the differential amplifier 240 in response to the operation code φa provided from the counter unit 123 and outputs the hold signal HS at a time when the two voltage signals have the same level. For example, the hold signal HS may be output at a time when levels of the first and second output signals of the differential amplifier 240 cross each other.

The counter unit 123 performs counting from a time when the initialization code φy is output to the RC timer 121 to a time when the RC timer 121 outputs the hold signal HS, for example, during the time delay T AD , and outputs the count value C_C 2 ′ in step S 120 . The first and second analog signals V in + and V in − input to the RC timer 121 may cross each other due to the first and second slope capacitors 260 and 270 each having the fixed capacitance and the count value C_C 2 ′ corresponding to the time delay T AD till the crossing time point of the first and second analog signals V in + and V in − may be an analog-to-digital converted value of the two signals V in + and V in − .

For example, as illustrated in FIG. 4 , during the period from the time t 1 to the time t 2 , the RC time constant calibrator 120 outputs a count value, e.g., “01000”, obtained by counting till the crossing time point of the first and second analog signals V in + and V in − , for example, during the time delay T AD . During a period from the time t 2 to a time t 3 , the RC time constant calibrator 120 outputs a count value, e.g., “01100”, obtained by counting till the crossing time point of the first and second analog signals V in + and V in − , for example, during the time delay T AD . During a period from the time t 3 to a time t 4 , the RC time constant calibrator 120 outputs a count value, e.g., “01010”, obtained by counting till the crossing time point of the first and second analog signals V in + and V in − , for example, during the time delay T AD .

The count value C_C 2 ′ output from the RC time constant calibrator 120 is provided to the inversion unit 130 . The inversion unit 130 inverts the count value C_C 2 ′ and outputs the analog-to-digital converted value C_C 2 in step S 130 . This is because the time delay T AD , for example, the crossing time point of the first and second analog signals V in + and V in − , is in inverse proportion to the difference between the first and second analog signals V in + and V in − . The count value C_C 2 ′ output from the RC time constant calibrator 120 decreases as the difference between the first and second analog signals V in + and V in − increases, and therefore, the count value C_C 2 ′ is inverted before being output.

For example, the count value C_C 2 ′ of “01000” output from the RC time constant calibrator 120 during the period from the time t 1 to the time t 2 may be output as the analog-to-digital converted value C_C 2 of “10111” by the inversion unit 130 . The count value C_C 2 ′ of “01100” output from the RC time constant calibrator 120 during the period from the time t 2 to the time t 3 may be output as the analog-to-digital converted value C_C 2 of “10011” by the inversion unit 130 . The count value C_C 2 ′ of “01010” output from the RC time constant calibrator 120 during the period from the time t 3 to the time t 4 may be output as the analog-to-digital converted value C_C 2 of “10101” by the inversion unit 130 .

According to some exemplary embodiments of the present invention, an externally provided analog signal is converted into a digital signal using an RC time constant calibrator. The RC time constraint calibrator may thereby function as a low frequency analog-to-digital converter, thereby reducing a layout area of a small modem chip having a limited layout and thus increasing efficiency.

While exemplary embodiments of the present invention have been particularly shown and described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in forms and details may be made therein without departing from the spirit and scope of the present invention.