Combined matching and filter circuit

This is a continuation of U.S. Ser. No. 10/872,947, filed Jun. 21, 2004 now U.S. Pat. No. 7,660,562, which is incorporated by reference.

The present invention relates to impedance matching and harmonic filtering for power amplifiers, and in particular to impedance matching and harmonic filtering for cellular phone transmission amplifiers.

Cellular phones typically transmit at radio frequencies (RF) in the 1 to 5 GHz range. At these frequencies, transmission lines have an impedance of approximately 50 Ohms, while typical cellular phone transmission power amplifiers have output impedances in the range of 1 to 5 Ohms. Cellular phones therefore require an impedance matching circuit between their power amplifiers and transmission lines.

In addition, regulatory bodies such as the Federal Communications Commission (FCC) have strict regulations regarding harmonic suppression in cellular phones. This suppression, if properly implemented, prevents cellular phone use from interfering with communications equipment operating at the higher frequencies harmonics.

Traditionally, cellular phone handsets have been manufactured to meet these two requirements by having two separate circuits, one for impedance matching and one for harmonic suppression. It is also usual to construct each circuit using discrete passive elements, i.e. inductors, capacitors and chip resistors, mounted on printed circuit (PC) boards, because of the typical capacitor and inductor values required by such separate circuits.

Circuits made using discrete components tend to be large and bulky. Moreover, multilayer PC board ground effects tend to introduce excess inductances that make obtaining the required level of harmonic suppression difficult. It is therefore desirable to have circuit designs in which the inductance and capacitance values allow monolithic integrated circuit implementation, as the associated batch manufacturing processes are less expensive, while the resultant circuits avoid the inductance problems associated with PC boards and are smaller and less bulky.

Another approach to reducing the size of a low loss circuit is to combine the impedance matching and filtering functions into a single circuit. This can be done, for instance, by first designing a circuit that matches input impedance to output load at a particular transmission frequency (also referred to as the fundamental frequency). A low loss, minimum delay version of such an impedance matching circuit typically consists of at least one series arm, having several inductors, and at least one shunt arm, consisting of capacitors. By suitable choice of capacitor and inductor values, input and output impedance can be matched at the fundamental frequency. It is also possible to replace a shunt capacitor with a somewhat smaller capacitor and a suitably chosen inductor connected in series. At the fundamental frequency the capacitor/inductor pair behaves essentially like the original, somewhat larger shunt capacitor. Not only does this reduce the size of the required capacitor, but the capacitor/inductor pair may also be used as a harmonic filter. This additional benefit is possible because a capacitor/inductor pair connected in series has a resonance frequency (also known as the series resonance frequency) at which the combination essentially acts as a short circuit. If the capacitor and inductor values are chosen judiciously, this series resonance can be made to occur at a harmonic of the fundamental frequency. The shunt capacitance element of the matching circuit then also acts as a harmonic filter by essentially becoming a short circuit to ground at the harmonic frequency, thereby preventing transmission of that frequency to the output.

A problem of designing such combined impedance matching and filtering circuits (also known as matching filter circuits) is that there are a limited number of shunt elements in a typical matching circuit. Effective harmonic suppression requires filtering at multiple harmonics. Moreover, a capacitor/inductor series resonance typically has a high quality factor (Q), i.e. the width of the resonance is narrow. One way to improve the bandwidth of such filters is to have two or more capacitor/inductor series resonance filters, each offset by a suitably small frequency, on either side of the harmonic frequency being filtered. Such designs require a relatively large number of filter elements. The problem, therefore, is how to design a matching filter circuit having a sufficient number of filters (also known as harmonic traps) to provide the required level of harmonic rejection, given the limited number of conductive shunt arms in a typical, low loss minimum delay matching circuit.

Briefly described, the invention provides a combined impedance matching and harmonic rejection circuit (also known as a matching filter circuit) having increased harmonic rejection capability. The increased harmonic rejection of the circuit is achieved by providing a split, or dual, resonance for one or more of the capacitive or inductive elements of the circuit.

In one embodiment, the matching filter circuit comprises a series arm, which, at the fundamental frequency, is essentially a series of inductors, with one or more shunt arms, which, at the fundamental frequency, are essentially capacitors. The first shunt arm requires a certain capacitance (the impedance-matching-required capacitance) for the circuit to achieve impedance matching at the fundamental frequency for which the circuit is designed. By providing that match-required capacitance using two parallel paths, each having a capacitor and an inductor in series, the matching filter circuit can be made to reject two separate harmonics represented by the series resonance of each of the parallel paths. In this manner, an extra null in the stop-bands of the circuit can be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency for which the circuit is designed.

An objective of the design is to provide matching filters with increased harmonic suppression in a more compact design that is capable of being implemented as a monolithic circuit suitable for low cost, batch manufacture.

These and other features of the invention will be more fully understood by reference to the following drawings.

FIG. 1 is a circuit diagram of an impedance matching circuit operation at a single, fundamental frequency.

FIG. 2 is a circuit diagram of a matching filter circuit with capacitance split shunt resonance, exemplifying the inventive concepts of one embodiment of the present invention.

FIG. 3 is a circuit layout diagram of a matching filter circuit exemplifying the inventive concepts of one embodiment of the present invention.

FIG. 4 is a plot of the S11 and S21 scattering parameters versus frequency for the circuit of FIG. 1 .

FIG. 5 is a circuit diagram of a matching filter circuit with inductive split dual resonance, exemplifying the inventive concepts of one embodiment of the present invention.

FIG. 6 is a plot of the S11 and S21 scattering parameters versus frequency for the circuit of FIG. 4 .

The present invention provides for combining impedance matching and harmonic filtering functions into a single match-and-filter circuit in a way that significantly improves the harmonic filtering. The invention will now be described in more detail by reference to the attached figures in which like numbers refer to like elements.

FIG. 1 is a circuit diagram of an impedance matching circuit, designed to operate at a single, fundamental frequency. The circuit has an inductive series arm 8 , comprising inductors L 1 , L 2 and L 3 in series and capacitor C 4 . The circuit also has capacitive shunt arms, each arm including a separate capacitor C 1 , C 2 , and C 3 . Components L 1 , L 2 , L 3 , C 1 , C 2 and C 3 are chosen so that the circuit has a first effective impedance “A” at port P 1 and a second, effective impedance “B” at port P 2 . In this way the circuit can, for instance, match an amplifier having an output impedance “A”, to a transmission line having an input impedance “B”. Capacitor C 4 is included so that an amplifier bias feed can be applied at port P 3 without any direct current getting to port P 2 .

FIG. 2 is a circuit diagram of a matching filter 10 , with capacitance split shunt resonance, exemplifying the inventive concepts of one embodiment of the present invention. The matching filter 10 , is a low-loss, minimum-delay filter comprising an input port P 1 , an output port P 2 , an amplifier bias-power port P 3 , a series arm, indicated by dashed box 12 , comprising transmission line TL 1 , inductors L 3 and L 5 as well as capacitors C 5 , C 3 and C 7 , and shunt arms, indicated by dashed boxes 14 , 16 and 18 , comprising capacitors C 1 , C 2 , C 4 and C 6 as well as inductors L 1 , L 2 , L 4 and L 6 . Transmission line TL 1 feeds the input signal from input port P 1 to the matching circuit, and acts substantially like an inductor. Although capacitors C 1 -C 6 and inductors L 1 -L 6 may be discrete passive elements, in a preferred embodiment, they are formed as part of a monolithic integrated circuit, using any of the well known technologies for producing such integrated circuits. The components of matching filter 10 are chosen so that the output impedance of a power amplifier connected to input port P 1 is matched to the transmission line attached to output port P 2 at a fundamental or transmission frequency F 0 .

In a typical cellular phone application, the transmission frequency F 0 is in the range of 0.8 to 5 GHz. For instance, the well-known Advanced Mobile Phone System (AMPS) standard uses a transmission frequency in the region of 850 MHz (0.85 GHz), the Global System for Mobile Communications (GSM) standard uses a transmission frequency in the region of 900 MHz (0.9 GHz), the Digital Cellular System (DCS) standard uses a transmission frequency in the region of 1.8 GHz and the Personal Communications System (PCS) standard uses a frequency in the region of 1.9 GHz.

In a typical cellular phone application, input port P 1 is connected to the output of a power amplifier having an output impedance in the range of 1-5 Ohms. For instance, a typical power amplifier operating at the GSM frequency of 900 MHz has an output impedance of about 1.5 Ohms, while, at the DCS frequency of 1.8 GHz, a typical power amplifier output impedance is 2.5 Ohms. This has to be matched to an output transmission line having an impedance of about 50 Ohms connected to output port P 2 . Port P 3 is used to provide DC bias voltage to the power amplifier connected to input port P 1 . Blocking capacitor C 7 prevents this DC bias voltage from reaching output port P 2 .

At the fundamental frequency F 0 , the impedance matching of circuit 10 may be approximated as a series arm consisting of transmission line TL 1 followed by two inductors L 3 and L 5 , with three shunt arms having capacitances roughly equal to the values of capacitors C 1 +C 2 , C 4 and C 6 . The component values may be approximately calculated by well known impedance matching formulas and algorithms. (The values calculated in this manner may be made more accurate by, for instance, further considering the reduction in capacitance at the fundamental frequency due to series inductors L 1 , L 2 , L 4 and L 6 as well as the increase in inductance of L 3 due to parallel capacitor C 3 ).

In a preferred embodiment, sufficient harmonic suppression to meet FCC rules may be provided by having broad suppression at frequencies in the vicinity of the second harmonic (2F 0 ) combined with suppression of harmonics up to the fifth harmonic, i.e., at frequencies in the vicinity of 3F 0 , 4F 0 and 5F 0 . If the broad suppression (also known as providing a wider band of rejection) of the second harmonic is achieved by having filters (also known as harmonic traps) at a frequency 2F 0 +, just above the second harmonic, and at a frequency 2F 0 −, just below the second harmonic, there is a requirement for a total of five filters from a circuit that has only three shunt arms.

In a preferred embodiment of the invention, a solution is to provide two of the required filters by means of a split shunt resonance. A split shunt resonance is formed from a single shunt arm 14 by splitting that shunt arm into two paths, as is done with the first shunt arm in FIG. 2 . The first shunt arm 14 in FIG. 2 comprises two paths of capacitor/inductor pairs, the pairs being C 1 /L 1 and C 2 /L 2 . In a preferred embodiment C 1 and L 1 are chosen to have a series resonance at a frequency in the vicinity of four times the fundamental frequency (4F 0 ) and thereby provide a harmonic filter for the fourth harmonic by effectively shorting any signal in the vicinity of that frequency to ground. Similarly, C 2 and L 2 are chosen to have a series resonance at a frequency 2F 0 −, just slightly less than twice the fundamental frequency and thereby provide part of a second harmonic filter by effectively shorting any signal in the vicinity of that frequency to ground. The values of C 1 , L 1 , C 2 and L 2 are also required to combine to form a first, impedance-matching-required, effective capacitance at the fundamental frequency, F 0 .

A further restriction is that the shunt arm circuit element 14 , comprised of the circuit elements C 1 , L 1 , C 2 and L 2 , also has a parallel resonance frequency Fp, at a frequency somewhere between the filter frequencies of 2F 0 − and 4F 0 . At this parallel resonance frequency, the first shunt arm is effectively an open circuit. Therefore, this resonance should be placed at a frequency where it is benign with respect to required circuit functionality. This may be accomplished by, for instance, selecting values for the components so as to place the parallel resonance in the vicinity of the frequency of another harmonic trap in the circuit, such as a third harmonic trap provided, by the shunt arm 18 , comprising the elements C 6 and L 6 .

The values of C 1 , L 1 , C 2 and L 2 may be obtained by starting with values indicated by well known circuit design equations and algorithms, placing these values in well known circuit simulation software and observing the predicted circuit behavior. Component values can then be iteratively adjusted to produce the required behavior at the various frequencies.

In a preferred embodiment, filtering of the third harmonic (3F 0 ) and widening of the second harmonic (2F 0 ) rejection may be achieved by providing harmonic traps on the second and third capacitance shunt arms, 16 and 18 . The second shunt arm components C 4 and L 4 may, for instance, be chosen to have both a required capacitance at the transmission frequency F 0 and a series resonance at a frequency 2F 0 +, just above the second harmonic, thereby providing part of a second harmonic filter by effectively shorting any signal in the vicinity of that frequency to ground. This second shunt arm 16 portion of the second harmonic filter in the vicinity of frequency 2F 0 +, combines with the portion of the second harmonic filter in the vicinity of frequency 2F 0 −, in the first shunt arm, to provide broad rejection of signals in the vicinity of the second harmonic frequency 2F 0 . The third shunt arm 18 components C 6 and L 6 may, for instance, be chosen to have both an impedance-matching-required, effective capacitance at the transmission frequency F 0 and a series resonance at 3F 0 , thereby providing a third harmonic filter by effectively shorting any signal in the vicinity of that frequency to ground.

In a preferred embodiment, fifth harmonic (5F 0 ) rejection may be achieved by, for instance, placing a harmonic trap in the series arm of the circuit using the open circuit, parallel resonance of an inductor and capacitor in series, as shown by elements L 3 and C 3 . These series arm components may be chosen to have a required inductance at the transmission frequency F 0 and to have a parallel resonance at a frequency in the vicinity of five times the fundamental frequency 5F 0 , thereby providing a fifth harmonic filter by effectively becoming an open circuit with large (ideally infinite) impedance at that frequency, preventing any signal in the vicinity of that frequency from being transmitted.

In FIG. 2 , the transmission line TL 1 is required to transfer the signal from the input port to capacitors C 1 and C 2 and inductor L 3 . In a practical implementation capacitor C 5 is placed in parallel with TL 1 to increase the effective inductance of the transmission line TL 1 at the second harmonic frequency (2F 0 ). In particular, it is chosen to provide suitable impedance for the power amplifier in the vicinity of this frequency.

Exemplary values for the components of FIG. 2 to implement an impedance matching and harmonic filtering circuit operating at a transmission or fundamental frequency of about 800 MHz include the following values: C 1 about 6.25 pF, L 1 about 0.33 nH, C 2 about 31.25 pF, L 2 about 0.22 nH, C 3 about 0.5 pF, L 3 about 1.78 nH, C 4 about 6.3 pF, L 4 about 1.45 nH, C 5 about 1 pF, C 6 about 4.3 pF, L 6 about 0.87 nH, C 7 about 30 pF.

FIG. 3 is a circuit layout diagram of a matching filter circuit exemplifying the inventive concepts of one embodiment of the present invention. FIG. 3 shows the filter matching circuit 10 implemented as a monolithic integrated circuit. The implementation may be undertaken using any well-known integrated circuit fabrication technology, including the use of gallium arsenide (GaAs) technology. The circuit of FIG. 3 may be implemented using for instance, a layer of GaAs that is 6 mils thick with a total length L, of about 2.2 mm and a width W, of about 1.38 mm. The pad P 1 may be a metallic pad, intended for wire bonding to the output of a power amplifier. Pad P 3 may then be used, in conjunction with appropriate inductors, to supply bias voltage to the output of the attached power amplifier, thereby allowing a simplified bias injection circuit on the power amplifier.

The elements in FIG. 3 correspond to like labeled elements in FIG. 2 . In the layout of matching filter 10 shown in FIG. 3 , inductor L 3 is shown close to L 6 and similarly inductor L 4 is shown close to L 5 . With such a compact layout, there will be mutual inductance between these inductors which will depend both on the proximity and the winding sense of each inductor relative to the others. This mutual inductance will affect the performance of the overall matching filter 10 . By using well-known electro-magnetic (EM) modeling and circuit performance prediction models that incorporate mutual inductance, the required values of the components can be arrived at by repetitive iterations in which performance-versus-frequency is fine-tuned by empirically adjusting component values starting from, for instance, a design calculated analytically using approximations such as, but not limited to, zero mutual inductance.

FIG. 4 is a plot of the S11 and S21 scattering parameters as a function of frequency for the shunt capacitance split resonance circuit of FIG. 2 . Curve 25 is the S21 scattering curve that effectively shows the amount of signal that gets into the next device, i.e. the device attached to output terminal P 2 , by displaying the amount of the incident signal that passes through the filter. The higher the value of S21 as measured in the vertical axis using scale 26 , the more signal that gets to the next device via terminal P 2 . For instance, a zero reading for S21 indicates that all of the signal is transmitted through the circuit and reaches P 2 . At a frequency m 1 of 825 MHz, S21 is about −1.274 dB, indicating that, at this frequency, most of the signal is being transmitted to the next device. In the vicinity of the second harmonic frequency, most of the signal is reflected back, as shown at frequency m 2 of 1.7 GHz where the S21 value is −71.575 dB, indicating that almost no signal reaches the next device via output P 2 .

Curve 22 of FIG. 4 is an S11 curve showing how much power is reflected by the circuit, as measured on the scale 24 . As the matching filtering 10 is a passive device, the maximum power throughput is 1 (1 may also be represented as 0 dB). In the vicinity of the design transmission frequency of 825 MHz, marked as m 1 , the power reflected back by the device as indicated by the S11 curve 22 is approximately −25 dB, indicating very little power reflected by the device. In the vicinity of the second harmonic frequency, at the frequency of 1.7 GHz, marked by m 2 , the S11 value is approximately −1 dB, indicating that most of the power is reflected by the device at this frequency. Similarly, in the vicinity of the third harmonic, very little power flows through the circuit as shown by the S21 value of −74.066 dB at the frequency of 2.625 GHz, marked as m 3 .

FIG. 5 is a circuit diagram of a matching filter with inductive split dual resonance, exemplifying the inventive concepts of one embodiment of the present invention. The matching filter 30 may initially be approximated by an impedance matching circuit operating at the transmission frequency (F 0 ), having a series arm comprising transmission line TL 1 , and inductances given by inductors L 3 and L 5 +L 7 , and three shunt arms having capacitances given by capacitors C 2 , C 4 and C 6 .

The harmonic filtering function of the circuit may be incorporated by, for instance, implementing each of the shunt arm capacitances as a capacitor and inductor in series, as shown by capacitor/inductor pairs C 2 /L 2 , C 4 /L 4 and C 6 /L 6 . By judicious choice of the inductors, the capacitor/inductor pair may satisfy the capacitance requirements at F 0 , and have a series resonance that creates a harmonic trap at a second frequency by effectively functioning as a closed circuit (also known as a short circuit) at that second frequency. For instance, C 2 /L 2 may be chosen to series resonate at 4F 0 , C 4 /L 4 may be chosen to series resonate at 2F 0 −, and C 6 /L 6 may be chosen to series resonate at 4F 0 , thereby creating harmonic filters at these frequencies by effectively becoming a closed circuit and shorting any signal in the vicinity of those frequencies to ground.

Additional harmonic filtering may be accomplished by parallel resonances that create open circuit conditions. For instance, C 3 and L 3 may be chosen so that, in addition to providing the required effective inductance at F 0 , the inductor/capacitor pair parallel resonate at a second frequency, thereby effectively blocking any signal in the vicinity of that second frequency.

In order to provide more resonance traps and to broaden the bandwidth of others, the parallel resonance can be split as shown by the circuit elements C 5 , L 5 , C 7 and L 7 in FIG. 5 . L 5 and L 7 are chosen to provide appropriate inductance for the impedance matching function at F 0 . By splitting the total inductance into two components, it is then possible to have two separate parallel resonance filters in series, one at the parallel resonance frequency of C 5 and L 5 and one at the parallel resonance frequency of C 7 and L 7 . In FIG. 5 , these parallel resonance frequencies are chosen to be 2F 0 + and 2F 0 −−, thereby providing a broader bandwidth filter in the vicinity of the second harmonic of the fundamental or transmission frequency.

An important factor in such a series inductance split dual resonance 32 , is that, between the two parallel resonances, there is effectively a series resonance frequency at which the combined elements act as a closed circuit. To prevent harmonic leakage at this frequency it is important to also include a shunt filter at this frequency. In circuit 30 this matching shunt filter is provided by capacitor/inductor pair C 4 /L 4 .

In FIG. 5 , the transmission line TL 1 is required to transfer the signal from the input port to the inductor L 3 and the capacitors C 3 and C 2 . Capacitor C 1 in parallel with transmission line TL 1 is chosen so that, at the series resonance frequency of the first shunt arm, i.e., the series resonance of capacitor C 2 and inductor L 2 , the effective impedance of transmission line TL 1 is suitable as an output for the power amplifier attached at P 1 .

In FIG. 5 , capacitor C 8 is a blocking capacitor that prevents current leakage to output port P 2 from any DC bias voltage applied at port P 3 . DC voltage may be applied at port P 3 as, for instance, bias voltage for the power amplifier attached to input port P 1 .

Exemplary values for the components required to implement an impedance matching and harmonic filter 30 , operating at a transmission or fundamental frequency of about 800 MHz, include the following values C 1 about 1 pF, C 2 about 44 pF, L 2 about 0.05 nH, C 3 about 0.5 pF, L 3 about 1.78 nH, C 4 about 6.3 pF, L 4 about 1.45 nH, C 5 about 5 pF, L 5 of about 1.6 nH, C 6 about 4.3 pF, L 6 about 0.87 nH, C 7 about 6 pF, L 7 about 1.5 nH and C 8 of about 30 pF.

FIG. 6 is a a plot of the S11 and S21 scattering parameters versus frequency for the matching filter circuit with series inductance split resonance of FIG. 4 . Comparison of S11 curve 42 to S11 curve 22 of FIG. 4 , shows that in the region of the 825 MHz fundamental or transmission frequency, the matching filter with series inductance split resonance has a broader transmission bandwidth than the matching filter with capacitance split shunt resonances of FIG. 2 . Additionally, by comparing the S21 curve 46 with the S21 curve 25 of FIG. 3 , the improved filtering in the region of 1800 MHz of the matching filter circuit with series inductance split resonance is apparent.

Although the invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claimed invention.