Window comparator circuit for limiting input voltage applied to object circuit

This application is related to Japanese Patent Application NO. 2009-12952 filed on Jan. 23, 2009, the contents of which are hereby incorporated by reference.

1. Field of the Invention

The present invention relates to a comparator circuit used for a protection circuit, more particular to a window comparator circuit to is protect an object circuit to be protected from an excessively high or low input voltage.

2. Description of the Related Art

A type of window comparator circuit has been known as a circuit which is used for protecting an object circuit (hereinafter referred to a protected circuit) suffering from excessively high or low input voltage. For instance, Japanese Patent Laid-open Publication Number JP-1982-40657 discloses a circuit configuration comprising two comparator circuits and resistors which are connected in series to generate two reference voltages, each reference voltage is applied to either a non-inverting input terminal or an inverting input terminal of the two comparators. The output terminals of the comparators are configured as open collector circuits and are pulled up with resistors. In this configuration, the input voltage is inputted to a non-inverting input terminal and an inverting input terminal of the two comparators and the input voltage is compared with the two reference voltages so as to limit the input voltage being exceed an upper limit voltage and a lower limit voltage. In addition, patent documents, Japanese Patent Laid-open Publication Number JP-2004-301709 and JP-2008-170285 can be listed as related arts of the present invention.

In the document of the Japanese patent laid open number JP-1982-40657, operational amplifiers (hereinafter referred to op-amp) have been used in order to limit the input voltage being exceed the upper voltage limit and the under voltage limit. However, an op-amp circuit employs approximately 20 transistors so that the circuit scale will be increased. Since the technical features of the JP-2004-301709 and JP-2008-170285 include using a large number of op-amp circuits, similar problem arises as well as the document S57-40567.

The present invention has been made in light of the problem mentioned above, and has as its object to provide a window comparator circuit which is able to shrink its circuit scale having an equivalent function as the related art.

According to a first aspect of the present invention, following effects can be achieved. A reference voltage generation block generates first and second reference voltages on the basis of a voltage applied between a first power supply node and a second power supply node. A first transistor having a first control terminal is connected to a portion between the first power source node and the second power source node as a diode-connection. Also, the first transistor is connected to a first node at which a first current is supplied by a first current source. At the first node, the first reference voltage is applied. On the other hand, a second transistor having a second control terminal is connected to a portion between the first power source node and the second power source node as a diode-connection. Also, the second transistor is connected to a second node at which a second current is supplied by a second current source. At the second node, the second reference voltage is applied.

A third transistor has a third control terminal and outputs the first reference voltage from a first output terminal when a voltage between the third control terminal and the first output terminal becomes a predetermined voltage or more. A fourth transistor has a fourth control terminal and outputs the second reference voltage from a second output terminal which is tied together with the first output terminal when a voltage between the fourth control terminal and the second output terminal becomes a predetermined voltage or more. Thus, a limited voltage is inputted to the protected circuit. In this case, the first transistor or the fourth transistor mainly behaves as a voltage limiting operation.

Conventionally, for instance, it is required to employ at least 20 is or more transistors if the circuit is configured to be used as an op-amp. In contrast, according to the first aspect of the present invention, the first or fourth transistor mainly contributes the circuit operation. Hence, the circuit scale for protecting the protected circuit suffering from excessively high or low input voltage can be significantly reduced. Also, similar voltage limiting function can be implemented by the circuit configuration as well as the related art described above.

According to a second aspect of the present invention, the reference voltage generation block constitutes a plurality of the resistors that are connected in series between the first power source node and the second power source node. Therefore, the first and second reference voltage can be changed easily by adjusting the value of the plurality of resistors. As a result, a voltage limiting range for the input voltage of the protected circuit can be adjusted easily.

In the drawings:

FIG. 1 is a circuit diagram showing an electrical configuration according to the first embodiment of the present invention;

FIG. 2 is a graph showing an input voltage characteristic of a protected circuit;

FIG. 3 is a circuit diagram showing a state of the current flowing when the output voltage of a voltage generating circuit is in higher voltage range;

FIG. 4 is a circuit diagram showing a state of the current flowing when the output voltage of the voltage generating circuit is in lower to voltage range;

FIG. 5 is a circuit diagram showing a state of the current flowing when the output voltage of the voltage generating circuit is in intermediate voltage range;

FIG. 6 is a circuit diagram corresponding to the FIG. 1 according to the second embodiment of the present invention;

FIG. 7 is a circuit diagram corresponding to the FIG. 1 according to the third embodiment of the present invention; and

FIG. 8 is a circuit diagram corresponding to the FIG. 1 according to the fourth embodiment of the present invention.

With reference to the accompanying drawings, hereinafter will be described embodiments of the present invention.

First Embodiment

Hereinafter will be described the first embodiment with reference to FIGS. 1 to 5 . FIG. 1 illustrates a circuit diagram showing a configuration of a window comparator circuit. As shown in the FIG. 1 , the window comparator circuit 1 is configured to protect an input of a protected circuit 2 suffering from an excessively high or low input voltage. The protected circuit 2 includes a circuit having limited input voltage range. For example, the protected circuit 2 comprises a sensor circuit that operates when a necessary input voltage is applied. Regarding a voltage generation circuit 3 , for instance, the circuit 3 generates a feedback voltage based on the output voltage of the sensor circuit provided in the protected circuit 2 and constitutes a feedback circuit such that the output voltage of the voltage generation circuit 3 shows over voltage when an output signal of the sensor circuit exceeds predetermined upper side voltage range and shows under voltage when the output signal of the sensor circuit becomes below predetermined lower side voltage range. Accordingly, an unexpected abnormal operation on the protected circuit 2 might occur when the input voltage of the protected circuit 2 becomes out of predetermined voltage range. For this reason, the first embodiment provides the Window comparator circuit 1 . The window comparator circuit according to the present invention will be used for various sensor circuits which is mounted on a vehicle system such as sensors used for air/fuel ratio (i.e., A/F ratio) detecting unit or the like.

The window comparator circuit 1 comprises a current source Is 1 , PNP type bi-polar junction transistors (hereinafter referred to as transistor) Qa 1 to Qa 6 , NPN type bi-polar junction transistors (hereinafter referred to as transistor) Qb 1 to Qb 7 and resistors R 1 to R 3 . In addition, R 4 is connected to an input side of the circuit. The resistor 4 is arranged at a portion between an output terminal 3 a of voltage generation circuit 3 and the protected circuit 2 .

A power supply voltage Vd (e.g. 5V) is supplied to a power source node N 0 (i.e., corresponds to a first power source node) and the resistors R 1 to R 3 are connected in series between the power source node N 0 and the ground GND (i.e., corresponds to a second power source node). In the embodiment, a single power supply circuit is used. However, a configuration of a dual power supply may be used.

A reference voltage generation circuit 4 serving as a reference voltage generation block comprises the resistors R 1 to R 3 . The reference voltage generation circuit 4 generates divided voltages corresponding to values of R 1 to R 3 and supplies the divided voltages to a node N 1 and a node N 2 , where the N 1 is a common node at which R 1 and R 2 are connected and the N 2 is a common node at which R 2 and R 3 are connected. The current source Is 1 and the transistor Qb 1 that forms a diode connection are connected in series between the power source node N 0 and the ground GND.

The base terminal of the transistor Qb 1 and base terminals of the transistors Qb 2 to Qb 4 are connected together. Among these transistors, current mirror circuits CM 1 , CM 2 and CM 3 are formed by the transistors Qb 1 and Qb 2 , the transistors Qb 1 and Qb 3 , and the transistors Qb 1 and Qb 4 , respectively. The emitter terminals of the transistors Qb 1 to Qb 4 are connected to the GND. Each mirror ratio of the CM 1 to CM 3 corresponding to the transistor pairs of the Qb 1 -Qb 2 , the Qb 1 -Qb 3 and the Qb 1 -Qb 4 are designed as 1:1.

With regard to the transistor Qa 1 , the emitter terminal is connected to the power source node N 0 and the base and the collector terminals are tied together. Also, the collector terminal of the Qa 1 and the collector terminal of the Qb 2 are tied together. The base terminal of the Qa 1 is connected to the both base terminals of the Qa 2 and Qa 3 . The emitter terminals of the transistors Qa 2 and Qa 3 are connected to the power source node N 0 .

The collector terminal of the transistor Qa 2 is connected to the node N 1 . Also, the emitter terminal of the transistor Qa 4 is connected to the node N 1 . The base terminal and collector terminal of the transistor Qa 4 are tied together and the collector terminal of Qa 4 is connected to the collector terminal of the Qb 3 .

The emitter terminal of the transistor Qa 3 is connected to the power source node N 0 . The collector terminal of the transistor Qa 3 is connected to the base terminal and collector terminal of the Qb 5 . The emitter terminal of the Qb 5 is connected to the node N 2 . Also node N 2 is connected to the collector terminal of the transistor Qb 4 . A current mirror circuit CM 4 is formed by the transistors Qa 1 and Qa 2 and a current mirror circuit CM 5 is formed by the transistors Qa 1 and Qa 3 . Each mirror ratio of the CM 4 and CM 5 corresponding to the transistor pairs of Qa 1 -Qa 2 and Qa 1 -Qa 3 are designed as 1:1.

In the transistors Qb 5 and Qb 6 , base terminals are tied together. With respect to the power source node N 0 , the emitter terminal of the transistor Qa 6 and one end of the resistor R 5 are connected to the node N 0 . The other end of the resistor 5 is connected to the collector terminal of transistor Qb 6 and base terminal of the transistor Qa 6 . The emitter terminal of the transistor Qb 6 is connected to the emitter terminal of transistor Qa 5 . Hereinafter will be described a node N 3 at which the emitter terminal of transistor Qb 6 and the emitter terminal of the transistor Qa 5 are connected together. The base terminal of the transistor Qa 4 and the base terminal of the Qa 5 are tied together.

The collector terminal of the transistor Qa 5 is connected to the is base terminal of the transistor Qb 7 and connected to the one end of the resistor R 6 . The other end of the resistor R 6 is connected the ground GND. Therefore, the resistor R 5 , the collector-emitter of the Qb 6 , the emitter-collector of the Qa 5 and the resistor R 6 are connected in series between the power source node N 0 and the ground GND. Each resistor R 5 and R 6 has a resistor value e.g. several kΩ and the resistor values of R 5 and R 6 may be selected as the same value in order to keep a symmetric characteristic of the circuit.

The emitter-collector of transistor Qa 6 and the collector-emitter of the transistor Qb 7 are connected in series between the power source node N 0 and the ground GND. These transistors Qb 6 and Qb 7 are connected at the common node N 3 . Also, the node N 3 acts as a node for the input terminal of the protected circuit 2 . In addition, the node N 3 is connected to the output terminal of the voltage generation circuit 3 via the resistor R 4 .

Hereinafter will be described effects of the circuit configuration as described above. FIG. 2 roughly illustrates a voltage characteristic of the window comparator circuit when the window comparator circuit protects the input voltage of the protected circuit. With reference to the FIG. 2 , a bias condition of the window comparator circuit when the circuit is in the steady state will be explained as follows.

As shown in FIG. 2 , in the window comparator circuit 1 , theoretically, the voltage Vh is limited (i.e., protected) to a predetermined voltage range (i.e., ranges from V 23 that is a voltage at the node N 2 to V 12 which is a voltage at the node N 1 ) against the dc (i.e., direct current) voltage V 0 that is an output voltage from the voltage generation circuit 3 . The window comparator circuit 1 is configured such that in the predetermined voltage range as described above, the voltage V 0 is applied to the protected circuit 2 without any changes and the voltage V 23 is applied to the protected circuit 2 when the voltage V 0 is in a range less than the voltage V 23 at the node N 2 , is similarly, the voltage V 12 is applied to the protected circuit 2 when the voltage V 0 is in a range more than the voltage V 12 at the node N 1 . Also, the window comparator circuit 1 protects the node N 3 such that a voltage V 0 exceeding the predetermined voltage range is not directly applied to the N 3 with a path from the voltage generation circuit 3 to the node N 3 via the resistor R 4 .

When a steady current is flowing from the current source Is 1 via the transistor Qb 1 , the same amount of current as a current I 1 that is flowing through the current source Is 1 flows as a collector current of the transistors Qb 2 , Qb 3 , and Qb 4 .

Due to the circuit configuration, a current value flowing through the collector of the transistor Qb 2 is equivalent to the value of the current flowing through the transistor Qa 1 . Since the transistors Qa 1 and Qa 2 work as the current mirror circuit CM 2 of which mirror ratio is 1:1, value of the collector current of the transistor Qa 2 is equivalent to the current I 1 . In addition, the collector current of the transistor Qb 3 is equivalent to the current I 1 . Therefore, the collector current I 1 of the transistor Qa 2 flows to the transistor Q 4 via the node N 1 . Theoretically, the current from the transistor Qa 4 does not flow on the resistor R 2 and R 3 via the node N 1 . Since the current I 1 is always flowing through the transistor Qa 4 , the transistor Qa 4 remains ON state.

Similarly, the collector current of the transistor Qa 3 and the collector current of the transistor Qb 4 are equivalent to the current so that the current I 1 flows through the transistor Qb 5 . However, the current I 1 does not flow through the resistor R 3 via the node N 2 . The current I 1 is always applied on the transistor Qb 5 whereby the transistor Qb 5 remains ON state. Such a bias conditions are made in the window comparator circuit 1 .

FIG. 3 roughly illustrates the ON/OFF states of the transistors when the input voltage Vh (i.e., the voltage at the node N 3 ) of the protected circuit 2 satisfies a voltage condition V 12 <Vo. In the steady state as described above, the transistors Qa 4 and Qb 5 stay ON state. The voltage at the node N 4 at which both of the base terminals of the transistors Qa 4 and Qa 5 are connected each other, becomes a voltage that is decreased from the voltage V 12 at the node N 1 by the base-emitter voltage of Qa 4 . Therefore, the transistor Qa 5 turns ON when the voltage at the node N 3 increases from the voltage at the node N 4 by the voltage between the base and emitter terminal of the transistor Qa 5 .

Assuming the base-emitter voltages (i.e., Vbe) of the Qa 4 and Qa 5 are the same voltage, if the voltage N 3 increases more than the voltage at the node N 1 , the transistor Qa 5 sink the current to the resistor R 6 . Hence, the voltage at the node N 3 becomes the same voltage as the voltage V 12 at the node N 1 . As a result, the voltage at the node N 3 does not exceed the voltage V 12 . If the current more than a predetermined value flows through the resistor R 6 , the base-emitter voltage of the transistor Qa 7 increases and therefore, transistor Qb 7 turns ON state.

As described above, in the steady state, the transistor Qb 5 is always in the ON state so that the voltage of the node N 5 at which the bases of the transistors Qb 5 and Qb 6 are connected each other, becomes a voltage increased from the voltage at the node N 2 by the base-emitter voltage Vbe of Qb 5 . Accordingly, when the voltage at the node N 3 exceeds the voltage V 12 , the voltage between the node N 5 and the node N 3 does not become the saturation voltage of the transistor Qb 6 when the Qb 6 is ON. For instance, the transistor Qb 6 becomes OFF state and also the transistor Qa 6 becomes OFF state.

FIG. 4 roughly illustrates the ON/OFF states of the each transistor when the input voltage Vh (i.e., voltage at the node N 3 ) of the protected circuit 2 satisfies a voltage condition V 23 >Vo. As described above, in the steady state, the transistors Qa 4 and Qb 5 stay ON state. Regarding the voltage at the node N 5 at which the bases of the transistors Qb 5 and Qb 6 are connected each other, becomes a voltage increased from the voltage at the node N 2 by the base-emitter voltage Vbe of Qb 5 . Therefore, when the voltage at the node N 3 is decreased from the voltage at the node N 5 by the base-emitter voltage Vbe of transistor Qb 6 , the transistor Qb 6 turns ON.

Assuming the base-emitter voltages (i.e., Vbe) of the Qb 5 and Qb 6 are the same voltage, if the voltage N 3 decreases less than the voltage at the node N 2 , the current start to flow through the resistor R 5 via the transistor Qb 6 . Therefore, the voltage at the node N 3 becomes the same voltage as the V 23 at the node N 2 and never becomes a voltage lower than the voltage V 23 . When the current flows through the resistor R 5 of which current value is more than a predetermined value, then the base-emitter voltage of the transistor Qa 6 increases. As a result, the transistor Qa 6 turns ON.

As described above, in the steady state, the transistor Qa 4 turns ON. Hence, the voltage at the node N 4 at which the bases of the transistors Qa 4 and Qa 5 are connected each other, becomes a voltage decreased from the voltage at the node N 1 by the base-emitter voltage. When the voltage at the node N 3 is lower than the voltage V 23 , the voltage between the node N 3 and the node N 4 does not reach the saturation voltage in the ON state of the transistor Qa 5 and for instance, the transistor Qa 5 turns OFF. Therefore, the transistor Qb 7 turns OFF as well.

FIG. 5 roughly illustrates state of the each transistor when the input voltage Vh (i.e., voltage at the node N 3 ) of the protected circuit 2 satisfies a voltage condition; V 12 >Vo>V 23 . As shown in FIG. 5 , when the voltage Vh satisfies the condition V 12 >Vo>V 23 , the voltage between the node N 5 and the node N 3 becomes a voltage lower than the base-emitter voltage Vbe of the transistor Qb 6 . Therefore, the transistor Qb 6 turns OFF. Also, the voltage between the node N 4 and the node N 3 becomes a voltage lower than the base-emitter voltage Vbe of the transistor Qa 5 so that the transistor Qa 5 turn OFF. Then, the voltages between both ends of the resistors R 5 and R 6 become 0V. Therefore, the transistors Qa 6 and Qb 7 turn OFF.

Accordingly, since the current does not flow into the window comparator circuit 1 via the node N 3 , the output voltage V 0 of the voltage generation circuit 3 is directly applied to the protected circuit 2 .

As described above, according to the first embodiment of the present invention, significant effects can be produced as follows. The reference voltage generation circuit 4 generates the reference voltage V 12 and the reference voltage 23 based on the power supply voltage Vd (e.g. 5V) being supplied to the power source node N 0 . The reference voltage V 12 and the reference V 23 are applied to the node N 1 and the node N 2 respectively. The current mirror circuit CM 4 and CM 5 supplies the same current as the I 1 being supplied by the current source Is 1 and the current mirror circuit CM 1 to CM 3 sink the same current as I 1 being supplied by the current source Is 1 .

The emitter terminal of the transistor Qa 4 is connected to the node N 1 at which the resistors R 1 and R 2 are connected each other and the emitter terminal of the transistor Qb 5 is connected to the node N 2 at which the resistors R 1 and R 2 are connected each other. However, as described above, the identical current flows through the current mirror circuits CM 1 to CM 5 . Accordingly, no current exchange take place between the reference voltage generation circuit 4 and the current mirror circuit CM 1 to CM 3 .

The emitter terminal of the transistor Qa 4 is connected to the node N 1 and the current I 1 is flowing between the emitter-collector terminals of the transistor Qa 4 . Hence, the circuit is in the steady state, the transistor Qa 4 turns ON. On the other hand, the emitter terminal of the transistor Qb 5 is connected to the node N 2 and the current I 1 is flowing between the emitter-collector terminals of the transistor Qb 5 . Accordingly, the transistor Qb 5 turns on when the circuit is in the steady state.

When the voltage generation circuit 3 applies a voltage higher than the voltage 12 to the node N 3 , the transistors Qa 5 and Qb 7 turn ON at the same time and the transistors Qb 6 and Qa 6 turn OFF as well. Therefore, the voltage at the node N 3 is held with the voltage V 12 theoretically. Reversely, when the voltage generation circuit 3 applies a voltage lower than the voltage V 23 to the node N 3 , the transistor Qb 6 and Qa 6 turn ON at the same time and the transistors Qa 5 and Qb 7 turn OFF as well. Therefore, the voltage of the node N 3 is held to the voltage 23 theoretically. Thus, the voltages can be restricted to a certain value.

The four transistors Qb 5 , Qb 6 , Qa 4 and Qa 5 are provided to contribute for a primary operation in this embodiment, with these transistors, the voltages can be restricted in a predetermined voltage range. Accordingly, unlike the circuits described as related arts (i.e., S57-40567, JP-2004-301709 and JP-2008-170285), it is not necessary to employ plurality of op-amp circuits in the embodiment of the present invention. Generally, an op-amp circuit comprises 20 or more transistors so that the number of transistors can be significantly reduced. Therefore, the circuit size can be shrunk.

Moreover, the window comparator circuit 1 can be formed in a semiconductor integrated circuit (IC) where the area (volume) occupied by the window comparator circuit 1 can be reduced even with the same circuit configuration as the prior art.

Also, it is only required to adjust resistor values for resistors R 1 , R 2 and R 3 in order to change the divided voltage V 12 at the node N 1 as an upper limit voltage and the divided voltage V 23 at the node N 2 as a lower limit voltage.

Second Embodiment

FIG. 6 illustrates a second embodiment of the present invention. In the second embodiment, a configuration of the output stage of the window comparator 1 is changed from the configuration of the first embodiment. In particular, the second embodiment provides a configuration of the window comparator circuit when the sink current being flow into the window comparator circuit is lower than the configuration of the first embodiment.

As shown in FIG. 6 , a window comparator circuit 11 which is the alternative circuit of the window comparator circuit 1 , provides a circuit configuration of the output stage circuit being arranged from the output stage of the window comparator 1 such that the transistor Qa 6 and Qb 7 are removed from the window comparator circuit 1 . Since the window comparator circuit 1 according to the first embodiment is capable of sinking high current, when the output current of the voltage generation circuit 3 is high, the circuit configuration of the first embodiment may be used.

In the window comparator circuit 11 , the resistor value of the R 4 is relatively high. Therefore, it is suitable to use the circuit configuration of the second embodiment when the current I 2 flowing in the window comparator circuit 11 is relatively low. In this embodiment, similar advantages as the first embodiment can be achieved even if the transistors Qa 6 and Qa 7 are removed from the circuit configuration.

Third Embodiment

FIG. 7 illustrates a third embodiment in which a reference voltage generation device newly added as an alternative circuit of the voltage divide circuit consisting of the resistors R 1 to R 3 used in the configurations of the embodiments as described above. Specifically, the window comparator circuit 21 which is alternative circuit of the window comparator circuit 1 includes a reference voltage generation circuit 22 instead of the voltage divide circuit consisting of the resistors R 1 to R 3 . In the window comparator circuit 21 , the reference voltage generation circuit 22 generates a reference voltage V 12 which is applied to the node N 1 and also generates the reference voltage V 23 which is applied to the node N 2 . Thus, the another circuit configuration without using the resistors R 1 to R 3 can provide similar advantages as well as the embodiments 1 to 2 as described above. Moreover, the reference voltage generation device can be a semiconductor integrated circuit device which is arranged apart from the window comparator circuit. The device supplies the reference voltages to the window comparator circuit 21 externally.

Fourth Embodiment

FIG. 8 illustrates a fourth embodiment of the present invention in which another current mirror circuits are used instead of the current mirror circuits of the configurations in the embodiments 1 to 3 as described above. Portions indicating the same configuration as previously described embodiments 1 to 3 have been marked with the same symbols and the explanation thereof are omitted. Hereinafter will be described the portions differs from the embodiments 1 to 3.

FIG. 8 illustrates a window comparator circuit being applied another type of current source. As shown in FIG. 8 , a window comparator circuit 31 as an alternative circuit of the window comparator circuit 1 does not include the current mirror circuits CM 1 to CM 5 , instead of these circuits, the window comparator circuit 31 includes current source circuits Is 3 to Is 6 . The current source Is 3 is connected to a portion between the power source node N 0 and the node N 1 . The current source Is 4 is connected to a portion between the collector terminal of the transistor Qa 4 (i.e., node N 4 ) and the ground GND. The current values for the current source Is 3 and Is 4 are designed to use the same amount of the current I 3 . Hence, the current source Is 4 sink whole amount of the current supplied by the current source Is 3 .

The current source Is 5 is connected to a portion between the power source node N 0 and the collector terminal of the transistor Qb 5 (i.e., node N 5 ). The current source Is 6 is connected to a portion between the emitter terminal of the transistor Qb 5 (i.e., node N 2 ) and the ground GND. The current values for the current source Is 5 and Is 6 are designed to use the same amount of the current I 4 . Hence, the current source Is 6 sink whole amount of the current supplied by the current source Is 5 . Therefore, the circuit configuration according to this is embodiment, the voltage V 12 at the node N 1 indicates a constant voltage and also the voltage V 23 of the node N 2 indicates a constant voltage. As a result, similar advantages as described in the embodiments 1 to 3 can be achieved in this embodiment.

Other Embodiment

The present invention is not limited to the above-described embodiments. Accordingly, following various embodiments or extendable embodiments may be applied. Above-described embodiments are applied for circuits which operate with a DC (direct current) input voltage signal. However, embodiments that protect the circuits suffering from over/under AC (alternate current) signal can be applied if the each transistor satisfies a required speed of response.

The embodiments as described above use a feedback circuit configuration in which a feedback voltage is applied to the protected circuit 2 from the protected circuit 2 via the voltage generation circuit 3 in order to protect the protected circuit 2 suffering from the over/under input voltage. However, a circuit configuration without using the feedback circuit configuration may be applied.