Nonvolatile semiconductor memory device capable of preventing write-disturb and method of programming

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. P2009-8145, filed on Jan. 16, 2009, the entire contents of which are incorporated herein by reference.

The invention relates to an electrically readable and writable nonvolatile semiconductor memory device, and to a method of programming for the same.

In a semiconductor integrated circuit (LSI), a relatively small-type nonvolatile semiconductor memory device is required, which can be embedded together with other elements in a single chip and which is capable of retaining stored data even after a power supply is cut off. The embedded-type nonvolatile semiconductor memory devices are used for a various purposes such as providing redundancy for large-capacity memories including dynamic random access memories (DRAMs) and static random access memories (SRAMs), storing codes including cryptographic keys managing manufacturing history, or tuning analog circuits. Conventionally, laser fuses have been used as memory elements for nonvolatile semiconductor memory devices used for the above-mentioned purposes. A laser fuse needs a special fuse blowing apparatus and a process associated with the special fuse blowing apparatus. In addition, laser fuses are difficult to miniaturize. Using laser fuses results in increase in the proportion of the area occupied by each laser fuse in the chip. Such a problem of the higher occupancy of laser fuses encourages development of anti-fuse storage elements having a MOS structure, for example, to replace the laser fuses. An anti-fuse storage element is disclosed in Japanese Patent Application Publication No. 2008-171477.

In a memory that employs MOS-structure anti-fuse storage elements, an erroneous writing may occur in a MOS-structure anti-fuse storage element. Such a write an erroneous writing is a write disturb fault. To avoid occurrence of the write disturb fault, each memory cell is provided with two ports. Consequently, the number of elements and the number of signals increase in the memory cell. Such increases result in a problem that the memory cells occupy a larger area.

According to an aspect of the invention is provided a nonvolatile semiconductor memory device, comprising a memory cell including an anti-fuse storage element and a selection transistor, a first terminal of the selection transistor being connected to one end of the anti-fuse storage element, a control terminal of the selection transistor being connected to a word line, and a second terminal of the selection transistor being connected to a bit line, a precharge control circuit to receive an input of a write enable signal and to generate a bit line control signal, a word line control signal, a write permission signal and a first control signal in response to the write enable signal, a power supply circuit to receive an input of the write permission signal and to supply a write voltage to the other end of the anti-fuse element in response to the write permission signal, a bit line potential control unit to receive inputs of an address control signal, the bit line control signal and the first control signal, and to control the potential of the bit line in response to the address control signal, the bit line control signal and the first control signal and a word line potential control unit to receive inputs of the address control signal, the word line control signal and the first control signal, and to control the potential of the word line in response to the address control signal, the word line control signal and the first control signal, wherein before a write operation of the anti-fuse storage element is executed, the potential of the one end of the anti-fuse storage element is raised, so that the anti-fuse storage element is set to be in a precharged state.

According to another aspect of the invention is provided a nonvolatile semiconductor memory device, comprising a memory cell array including a plurality of memory cells arranged in a matrix form, each memory cell including an anti-fuse storage element and a selection transistor, a first terminal of the selection transistor being connected to one end of the anti-fuse storage element, a control terminal of the selection transistor being connected to a word line, and a second terminal of the selection transistor being connected to a bit line, a precharge control circuit to receive an input of a write enable signal and to generate a bit line control signal, a word line control signal, a write permission signal and a first control signal in response to the write enable signal, a power supply circuit to receive an input of the write permission signal and to supply a write voltage to the other end of the anti-fuse element in response to the write permission signal, a bit line potential control unit to receive inputs of a first address control signal outputted from a bit line control circuit, the bit line control signal and the first control signal, and to control the potential of the bit line in response to the first address control signal, the bit line control signal and the first control signal and a word line potential control unit to receive inputs of a second address control signal outputted from a word line control circuit, the word line control signal and the first control signal, and to control the potential of the word line in response to the second address control signal, the word line control signal and the first control signal, wherein before a write operation of the anti-fuse storage element is executed, the potential of the one end of the anti-fuse storage element is raised, so that the anti-fuse storage element is set to be in a precharged state.

According to further another aspect of the invention is provided a method of programming for a nonvolatile semiconductor memory device including, a memory cell having an anti-fuse storage element and a selection transistor, a power supply circuit, a bit line potential control unit and a word line potential control unit, a first terminal of the selection transistor being connected to one end of the anti-fuse storage element, a control terminal of the selection transistor being connected to a word line, and a second terminal of the selection transistor being connected to a bit line, the method comprising, setting the bit line at a first high potential by the bit line potential control unit, raising the potential of the word line up to a second high potential by the word line potential control unit so as to activate the word line, to setting the anti-fuse storage element in a precharged state, lowering the potential of the word line by the word line potential control unit so as to deactivate the word line, to keep the precharged state of the anti-fuse storage element and supplying a write voltage outputted from the power supply circuit to the other end of the anti-fuse storage element after the deactivation of the word line, so that data is written into the anti-fuse storage element.

FIG. 1 is a circuit diagram illustrating a nonvolatile semiconductor memory device according to a first embodiment of the invention.

FIG. 2 is a circuit diagram illustrating a nonvolatile semiconductor memory device according to a comparative example of a first embodiment of the invention.

FIG. 3 is a flowchart illustrating a precharge operation and a write operation of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 4 is a timing chart illustrating the precharge operation and the write operation of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 5 is a circuit diagram illustrating a nonvolatile semiconductor memory device according to a second embodiment of the invention.

FIG. 6 is a flowchart illustrating a precharge operation and a write operation of the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 7 is a timing chart illustrating the precharge operation and the write operation of the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 8 is a timing chart illustrating the precharge operation and the write operation of the nonvolatile semiconductor memory device according to a third embodiment of the invention.

Hereinafter, embodiments of the invention will be described by referring to the drawings.

A nonvolatile semiconductor memory device and its programming method according to a first embodiment of the invention will be described below by referring to the drawings. FIG. 1 is a circuit diagram illustrating a nonvolatile semiconductor memory device of the first embodiment. FIG. 2 is a circuit diagram illustrating a nonvolatile semiconductor memory device of a comparative example. In the first embodiment, a precharge operation of an anti-fuse storage element is set up before a write operation of the anti-fuse storage element is executed.

As FIG. 1 shows, a nonvolatile semiconductor memory device 50 includes a memory cell 1 , a precharge control circuit 2 , a power supply circuit 3 , a bit line driver DRBL, a word line driver DRWL, a multiplexer 103 a , and a multiplexer 103 b . The nonvolatile semiconductor memory device 50 has low redundancy, but has a fast operation speed. The nonvolatile semiconductor memory device 50 is used for a wide variety of purposes such as: providing redundancy for large-capacity memories including dynamic random access memories (DRAMs) and static random access memories (SRAMs); storing codes including cryptographic keys; managing manufacturing history; and tuning analog circuits. In addition, the memory cell 1 is used for a field programmable gate array (FPGA) or the like.

The memory cell 1 includes an anti-fuse storage element 100 and a selection transistor HNMT 1 . The memory cell 1 serves as an anti-fuse memory cell.

In the anti-fuse storage element 100 , the source, the drain, and the body (also known as the “back gate”) are connected to a node N 2 , whereas the gate is connected to a node N 1 . The input into the Node N 2 is a write signal Swd outputted from the power supply circuit 3 . The node N 1 is connected to one of the source and the drain (first terminal) of the selection transistor HNMT 1 . The power supply circuit 3 is used as the power supply for the writing of the anti-fuse storage element 100 . The anti-fuse storage element 100 includes a P-channel MOS transistor. The anti-fuse storage element 100 stores data having a value “0” before the breaking of the fuse, and stores data having a value “1” after the breaking of the fuse.

One of the source and the drain (first terminal) of the selection transistor HNMT 1 is connected to the anti-fuse storage element 100 . The gate (control terminal) of the selection transistor HNMT 1 is connected to a word line WL. The other of the source and the drain (second terminal) of the selection transistor HNMT 1 is connected to a bit line BL. The selection transistor HNMT 1 includes an N-channel MOS transistor. The breakdown voltages (i.e., a breakdown voltage for the gate and a breakdown voltage between the source and the drain) of the selection transistor HNMT 1 are higher than the corresponding breakdown voltages of each of the transistors included in, for example, the precharge control circuit 2 , the bit line driver DRBL, the word line driver DRWL, the multiplexer 103 a , and the multiplexer 103 b.

At the time of the write operation, the other of the source and the drain (the second terminal) on the bit line side of the selection transistor HNMT 1 is set at a lower voltage source voltage (specifically, the ground potential) VSS. In the other occasions, the other of the source and the drain (the second terminal) on the bit line side of the selection transistor HNMT 1 is set at a higher voltage source voltage VDD. At the time of writing data having a value “1”, the gate (control terminal) on the word line WL is set at the higher voltage source voltage VDD. At the time of writing data having a value “0”, the gate (control terminal) on the word line (WL) is set at the lower voltage source voltage (ground potential) VSS.

The precharge control circuit 2 includes delay circuits 101 a to 101 d , a two-input AND circuit 102 a , and a two-input AND circuit 102 b . The precharge control circuit 2 generates a signal that turns the memory cell 1 into a precharged state before the write operation of the memory cell 1 .

A write-enable signal Swe is inputted into the delay circuit 101 a. The delay circuit 101 a delays the write-enable signal Swe by a first delay time, and outputs the resultant signal as a bit line control signal Scbl. The delay circuit 101 a serves as a first delay unit.

The bit line control signal Scbl outputted from the delay circuit 101 a is inputted into the delay circuit 101 b . The delay circuit 101 b delays the bit line control signal Scbl by a second delay time, and outputs the resultant signal as a delay signal Sdl 1 . The delay circuit 101 b serves as a second delay unit.

The delay signal Sdl 1 outputted from the delay circuit 101 b is inputted into the delay circuit 101 c . The delay circuit 101 c delays the delay signal Sdl 1 by a third delay time, and outputs the resultant signal as a delay signal Sdl 2 . The delay circuit 101 c serves as a third delay unit.

The delay signal Sdl 2 outputted from the delay circuit 101 c is inputted into the delay circuit 101 d . The delay circuit 101 d delays the delay signal Sdl 2 by a fourth delay time, and outputs the resultant signal as a write permission signal Swp. The delay circuit 101 d serves as a fourth delay unit.

Each of the delay circuits 101 a to 101 d is configured of inverters in an even number of stages. Alternatively, each of the delay circuits 101 a to 101 d may be configured of buffers in plural stages. In addition, the delay circuits 101 a to 101 d are used as the delay units, but instead, such delay elements as resisters and capacitors may be used as the delay units.

The two-input AND circuit 102 a receives an input of the delay signal Sdl 1 outputted from the delay circuit 101 b and an input of the delay signal Sdl 2 outputted from the delay circuit 101 c . The two-input AND circuit 102 a executes a logical operation with these inputs, and outputs the resultant signal as a word line control signal Scwl.

The two-input AND circuit 102 b receives an input of the write enable signal Swe and an input of the write permission signal Swp outputted from the delay circuit 101 d . The two-input AND circuit 102 b executes a logical operation with these inputs, and outputs the resultant signal as a multiplexer control signal Scmux.

Here, the two-input AND circuits 102 a and 102 b are used. Alternatively, they may be replaced by other types of logic circuits to form the logic configuration.

The multiplexer 103 a receives an input of the bit line control signal Scbl outputted from the delay circuit 101 a and an input of an address control signal Scad. In response to the multiplexer control signal Scmux outputted from the two-input AND circuit 102 b , the multiplexer 103 a outputs, selectively, one of the bit line control signal Scbl and the address control signal Scad. The signal outputted from the multiplexer 103 a is then inputted into the bit line driver DRBL, which drives this inputted signal and outputs the signal into the bit line BL.

The multiplexer 103 b receives an input of the word line control signal Scwl outputted from the two-input AND circuit 102 a and an input of an address control signal Scad. In response to the multiplexer control signal Scmux outputted from the two-input AND circuit 102 b , the multiplexer 103 b outputs, selectively, one of the word line control signal Scwl and the address control signal Scad. The signal outputted from the multiplexer 103 b is then inputted into the word line driver DRWL, which drives this inputted signal and outputs the signal into the word line WL.

Here, the multiplexer 103 a and the bit line driver DRBL serve as a bit line potential control unit. The multiplexer 103 b and the word line driver DRWL serve as a word line potential control unit.

The power supply circuit 3 receives an input of the write permission signal Swp outputted from the delay circuit 101 d . When the write operation of memory cell 1 is executed, the power supply circuit 3 outputs the write signal Swd that has a higher potential than the higher voltage source voltage VDD to the anti-fuse storage element 100 (i.e., the node N 2 ) of the memory cell 1 .

FIG. 2 shows that in the nonvolatile semiconductor memory device of the comparative example, a memory cell 11 has a two-port configuration so as to prevent write disturb fault from occurring. The memory cell 11 includes an anti-fuse storage element 100 , a write port 12 , and a read port 13 .

In the anti-fuse storage element 100 , a write signal Swd is input into the source, the drain and the body (i.e., into the node N 2 side). The gate (i.e., the node N 1 side) of the anti-fuse storage element 100 is connected to the write port 12 and the read port 13 .

The write port 12 includes a control transistor SNMT 1 and another control transistor SNMT 3 .

One of the source and the drain of the control transistor SNMT 3 is connected to the gate (i.e., the node N 1 ) of the anti-fuse storage element 100 . A write enable signal Swe is inputted into the gate of the control transistor SNMT 3 . One of the source and the drain of the control transistor SNMT 1 is connected to the other of the source and the drain of the control transistor SNMT 3 . The gate of the control transistor SNMT 1 is connected to a write word line WLW. The other of the source and the drain of the control transistor SNMT 1 is connected to a write bit line BLW.

The read port 13 includes a control transistor SNMT 2 and another control transistor SNMT 4 .

One of the source and the drain of the control transistor SNMT 4 is connected to the gate (i.e., the node N 1 ) of the anti-fuse storage element 100 . The gate of the control transistor SNMT 4 is connected to the higher voltage source voltage VDD. One of the source and the drain of the control transistor SNMT 2 is connected to the other of the source and the drain of the control transistor SNMT 4 . The gate of the control transistor SNMT 2 is connected to a read word line WLR. The other of the source and the drain of the control transistor SNMT 2 is connected to a read bit line BLR. Note that neither the description nor the drawing of the write operation and the read operation will be provided for the comparative example.

Subsequently, the precharge operation and the write operation of the nonvolatile semiconductor memory device will be described by referring to FIGS. 3 and 4 . FIG. 3 is a flowchart illustrating a precharge operation and a write operation of the nonvolatile semiconductor memory device. FIG. 4 is a timing chart illustrating the precharge operation and the write operation of the nonvolatile semiconductor memory device. Here, the data having a value “1” represents the write operation.

FIGS. 3 and 4 show that in the nonvolatile semiconductor memory device 50 , the write signal Swd, the bit line BL, and the word line WL are set at the lower voltage source voltage (ground potential) VSS before the precharge operation is executed.

Next, at a time T 1 , the voltage of the bit line BL is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD, for example, up to 3V (step S 1 ).

Subsequently, at a time T 2 , the voltage of the word line WL is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. When the voltage of the word line WL reaches the higher voltage source voltage VDD (i.e., when the word line WL is activated), the selection transistor HNMT 1 is turned ON. The voltage of one of the source and the drain of the selection transistor HNMT 1 (i.e., the gate (the node N 1 ) of the anti-fuse storage element 100 ) is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. Thus, the precharge of the anti-fuse storage element 100 is executed (step S 2 ).

Then, at a time T 3 , the voltage of the word line WL is lowered from the higher voltage source voltage VDD down to the lower voltage source voltage (ground potential) VSS, so that the word line WL is deactivated. The anti-fuse storage element 100 is kept in the precharged state. Note that the period of precharge operation starts from the time T 1 and ends immediately before a time T 4 when the voltage of the write signal Swd is raised up (step S 3 ).

Next, at the time T 4 , the voltage of the write signal Swd is raised from the lower voltage source voltage (ground potential) VSS up to a voltage that is higher than the higher voltage source voltage VDD (3V); for example, the voltage of the write signal Swd may be raised up to 6V (application of the voltage for writing). Here, the node N 2 of the anti-fuse storage element 100 is at 6V. The node N 1 of the anti-fuse storage element 100 is at 3V. This means that the potential difference between the node N 2 and the node N 1 is 3V. Accordingly, no electrical breakdown of the anti-fuse storage element 100 takes place at this moment (step S 4 ).

Subsequently, at a time T 5 , the voltage of the bit line BL is lowered from the higher voltage source voltage VDD down to the lower voltage source voltage (ground potential) VSS, so that the bit line BL is deactivated. After that, at a time T 6 , the voltage of the word line WL is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. Accordingly, the anti-fuse storage element 100 is turned ON. The voltage of one of the source and the drain of the selection transistor HNMT 1 (the gate (the node N 1 ) of the anti-fuse storage element 100 ) is lowered down. The potential difference between the node N 2 and the node N 1 increases, resulting in the electrical breakdown of the anti-fuse storage element 100 . Consequently, data having a value “1” is written in the anti-fuse storage element 100 (step S 5 ).

Then, at a time T 7 , the voltage of the word line WL is lowered from the higher voltage source voltage VDD down to the lower voltage source voltage (ground potential) VSS, so that the selection transistor HNMT 1 is turned OFF. Consequently, the voltage of the node N 1 is uppered from the lower voltage source voltage (ground potential) VSS up to the middle voltage between the voltage (6V) for writing and the lower voltage source voltage (ground potential) VSS. After that, at a time T 8 , the voltage of the write signal Swd is lowered from 6V down to the lower voltage source voltage (ground potential) VSS, and one of the source and the drain of the selection transistor HNMT 1 (i.e., the gate (the node N 1 ) of the anti-fuse storage element 100 ) is set up at the lower voltage source voltage (ground potential) VSS. Note that the period of write operation starts from the time T 4 and ends at the time T 8 (step S 6 ).

As has been described thus far, the nonvolatile semiconductor memory device, which the first embodiment of the invention provides together with its programming method, includes the memory cell 1 , the precharge control circuit 2 , the power supply circuit 3 , the bit line driver DRBL, the word line driver DRWL, the multiplexer 103 a , and the multiplexer 103 b . The memory cell 1 includes the anti-fuse storage element 100 and the selection transistor HNMT 1 . The precharge control circuit 2 includes the delay circuits 101 a to 101 d , two-input AND circuit 102 a , and two-input AND circuit 102 b . The precharge control circuit 2 receives an input of the write enable signal Swe, and generates the bit line control signal Scbl, the word line control signal Scwl, the multiplexer control signal Scmux, and the write permission signal Swp. Before the data are written into the anti-fuse storage element 100 of the memory cell 1 , the anti-fuse storage element 100 is set up in the precharged state by the precharge control circuit 2 , the bit line driver DRBL, the word line driver DRWL, the multiplexer 103 a , and the multiplexer 103 b . After the anti-fuse storage element of each memory cell, which is either a writing target or a non-writing target, is set up in the precharged state, the power supply circuit 3 outputs the write signal Swd that has a higher potential than the higher voltage source voltage VDD, and the write signal Swd is supplied to the anti-fuse storage element 100 .

Accordingly, during the write operation, no large potential difference occurs between the two ends of the anti-fuse storage element 100 of each memory cell that is the non-writing target. Consequently, the write-disturb fault can be prevented from occurring. In addition, each memory cell 1 includes the anti-fuse storage element 100 and the selection transistor HNMT 1 , and thus the number of elements and the number of signals in the memory cell 1 are reduced significantly. Accordingly, even if the nonvolatile semiconductor memory device 50 is highly integrated, the increase in the area occupied by the memory cell can be reduced significantly.

Note that the nonvolatile semiconductor memory device 50 of the first embodiment is made of MOS transistors, but MIS transistors may be used in place of the MOS transistors. Incidentally, both the MOS transistors and the MIS transistors are known as the insulated gate field effect transistors.

A nonvolatile semiconductor memory device and its programming method according to a second embodiment of the invention will be described below by referring to the drawings. FIG. 5 is a circuit diagram illustrating a nonvolatile semiconductor memory device. In the second embodiment, memory cells each including an anti-fuse storage element and selection transistor are arranged in a matrix, and a precharge operation of each anti-fuse storage element is set up before a write operation of the anti-fuse storage element is executed.

As FIG. 5 shows, a nonvolatile semiconductor memory device 51 includes a memory cell array 40 , a precharge control circuit 2 a , a power supply circuit 3 , a bit line control circuit 4 , a word line control circuit 5 , plural bit line drivers DRBL, plural word line drivers DRWL, plural multiplexers 103 a , and plural multiplexers 103 b . In the memory cell array 40 of the nonvolatile semiconductor memory device 51 , m memory cells 1 are arranged in the word line WL direction, and n memory cells 1 are arranged in the bit line BL direction. So, the memory cell array 40 of the nonvolatile semiconductor memory device 51 is formed by arranging the memory cells 1 in an (m×n) matrix.

The memory cell 1 includes an anti-fuse storage element 100 and a selection transistor HNMT 1 (a similar structure to the memory cell of the first embodiment). One end of the anti-fuse storage element 100 receives an input of a write signal Swd outputted from the power supply circuit 3 . The other end of the anti-fuse storage element 100 is connected to one of the source and the drain of the selection transistor HNMT 1 . The gate of the selection transistor HNMT 1 is connected to word lines WLx. The other one of the source and the drain is connected to bit lines BLx.

The precharge control circuit 2 a has a similar structure to the structure of the precharge control circuit 2 of the first embodiment (except that the precharge control circuit 2 a outputs more lines of signals). The precharge control circuit 2 a receives an input of a write enable signal Swe. In response to the write enable signal Swe, the precharge control circuit 2 a outputs word line control signals Scwlx corresponding respectively to m word lines WLx, bit line control signals Scblx corresponding respectively to n bit lines BLx, a write permission signal Swp, and a multiplexer control signal Scmux.

The power supply circuit 3 receives an input of the write permission signal Spw outputted from the precharge control circuit 2 a . At the time of a writing operation of the (m×n) memory cells 1 provided in the memory cell array 40 , the power supply circuit 3 outputs a write signal Swd, which has a higher potential than the higher voltage source voltage VDD, to the anti-fuse storage element 100 of the memory cell 1 .

The bit line control circuit 4 generates address control signals Scadbx that control individually the addresses of the n bit lines BLx. The bit line control circuit 4 outputs the address control signals Scadbx to the multiplexers 103 a corresponding respectively to the n bit lines BLx.

The n multiplexers 103 a are placed so as to be opposed to the bit line control circuit 4 . Each multiplexer 103 a receives an input of the bit line control signal Scblx outputted from the precharge control circuit 2 a and an input of the address control signal Scadbx outputted from the bit line control circuit 4 . In response to the multiplexer control signal Scmux outputted from the precharge control circuit 2 a , each of the n multiplexers 103 a outputs, selectively, either the bit line control signal Scblx or the address control signal Scadbx.

The n bit line drivers DRBL are placed so as to be opposed to the bit line control circuit 4 and opposed respectively to the multiplexers 103 a. Each of the n bit line drivers DRBL receives an input of the signal outputted from the corresponding multiplexer 103 a . Each bit line driver DRBL drives the signal thus inputted and outputs the signal to the corresponding bit line BLx.

The word line control circuit 5 generates address control signals Scadwx that control individually the addresses of the m word lines WLx. The word line control circuit 5 outputs the address control signals Scadwx to the multiplexers 103 b corresponding respectively to the m word lines WLx.

The m multiplexers 103 b are placed so as to be opposed to the word line control circuit 5 . Each multiplexer 103 b receives an input of the word line control signal Scwlx outputted from the precharge control circuit 2 a and an input of the address control signal Scadwx outputted from the word line control circuit 5 . In response to the multiplexer control signal Scmux outputted from the precharge control circuit 2 a , each of the m multiplexers 103 b outputs, selectively, either the word line control signal Scwlx or the address control signal Scadwx.

The m word line drivers DRWL are placed so as to be opposed to the word line control circuit 5 and opposed respectively to the multiplexers 103 b. Each of the m word line drivers DRWL receives an input of the signal outputted from the corresponding multiplexer 103 b . Each bit line driver DRWL drives the signal thus inputted and outputs the signal to the corresponding word line WLx.

Here, the multiplexer 103 a and the bit line driver DRBL serve as a bit line potential control unit. The multiplexer 103 b and the word line driver DRWL in the second embodiment serve as a word line potential control unit.

The power supply circuit 3 receives an input of the write permission signal Swp outputted from the precharge control circuit 2 a . When the write operation of (m×n) memory cells 1 provided in the memory cell array 40 is executed, the power supply circuit 3 outputs the write signal Swd that has a higher potential than the higher voltage source voltage VDD to the anti-fuse storage elements 100 of the memory cells 1 .

Next, the precharge operation and the write operation of the nonvolatile semiconductor memory device will be described by referring to FIGS. 6 and 7 . FIG. 6 is a flowchart illustrating a precharge operation and a write operation of the nonvolatile semiconductor memory device. FIG. 7 is a timing chart illustrating the precharge operation and the write operation of the nonvolatile semiconductor memory device.

FIGS. 6 and 7 show that in the nonvolatile semiconductor memory device 51 , the write signal Swd, the bit lines BL, and the word lines WL are set at the lower voltage source voltage (ground potential) VSS before the precharge operation is executed.

Then, at a time T 1 , the voltage of each bit line BL (each of all the bit lines BLx) is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD, for example, up to 3V (step S 1 ).

Subsequently, at a time T 21 , the voltage of, for example, the first one of all the word lines WLx is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. When the voltage of the first word line WLx reaches the higher voltage source voltage VDD (i.e., when the word line WL is activated), the selection transistors HNMT 1 of the n memory cells 1 connected to the first word line WLx are turned ON. The voltage of one of the source and the drain of the selection transistor HNMT 1 (i.e., the gate (the node N 1 ) of the anti-fuse storage element 100 ) of each of the n memory cells connected to the first word line WLx is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. Thus, the precharge of the anti-fuse storage elements 100 of the n memory cells connected to the first word line WLx is executed (step S 2 ).

Then, at a time T 31 , the voltage of the first word line WLx is lowered from the higher voltage source voltage VDD down to the lower voltage source voltage (ground potential) VSS, so that the first word line WLx is deactivated. The anti-fuse storage elements 100 of the n memory cells connected to the first word line WLx are kept in the precharged state (step S 3 ).

Next, the anti-fuse storage elements 100 in the memory cells for the second and the subsequent word lines WLx are likewise set up to be in a precharged state. The voltage of the ultimate, that is, the mth word line WLx is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. When the voltage of the ultimate, that is, the mth word line WLx reaches the higher voltage source voltage VDD (i.e., when the word line WL is activated), the selection transistors HNMT 1 of the n memory cells connected to the ultimate, that is, the mth word line WLx are turned ON. Then, the voltage of one of the source and the drain of each of the selection transistors HNMT 1 (the gate (node N 1 ) of each anti-fuse storage element 100 ) of the n memory cells connected to the ultimate, that is, the mth word line WLx is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. Thus, the precharge of the anti-fuse storage elements 100 of the n memory cells connected to the ultimate, that is, the mth word line WLx is executed (step S 14 ).

Subsequently, once the setting-up of the precharge operation is finished for all the memory cells 1 (i.e., all the (m×n) memory cells 1 ), the writing of data into the memory cells 1 of the writing target is executed (the writing of data is executed following similar procedures to those described in steps S 4 to S 6 of the first embodiment).

Here, the anti-fuse storage elements 100 of all the (m×n) memory cells 1 are set up to be in the precharged state before the execution of the writing of data into the anti-fuse storage elements 100 of the memory cells 1 of the writing target. Accordingly, during the write operation, no large potential difference occurs between the two ends of the anti-fuse storage element 100 (the potential difference between the node N 2 and the node N 1 ) of each memory cell that is the non-writing target. Consequently, erroneous writing can be prevented from occurring in the anti-fuse storage element 100 of each memory cell 1 that is the non-writing target. To put it briefly the write-disturb fault can be prevented from occurring.

As has been described thus far, the nonvolatile semiconductor memory device, which the second embodiment of the invention provides together with its programming method, includes the memory cell array 40 , the precharge control circuit 2 a , the power supply circuit 3 , the bit line control circuit 4 , the word line control circuit 5 , the plural bit line drivers DRBL, the plural word line drivers DRWL, the plural multiplexers 103 a , and the plural multiplexers 103 b . The memory cell array 40 of the nonvolatile semiconductor memory device 51 includes (m×n) memory cells 1 arranged in a matrix in which m memory cells 1 are arranged in the word line WL direction and n memory cells 1 are arranged in the bit line BL direction. Each memory cell 1 includes the anti-fuse storage element 100 and the selection transistor HNMT 1 . The precharge control circuit 2 a receives an input of the write enable signal Swe, and generates the plural bit line control signals Scblx, the plural word line control signals Scwlx, the multiplexer control signal Scmux, and the write permission signal Swp. Before the data are written into the anti-fuse storage element 100 of each memory cell 1 , the anti-fuse storage elements 100 of the (m×n) memory cells 1 are set up in the precharged state by the precharge control circuit 2 a , the bit line driver DRBL, the word line driver DRWL, the multiplexers 103 a , and the multiplexers 103 b . After the anti-fuse storage element of each memory cell, which is either the writing target or the non-writing target, is set up in the precharged state, the power supply circuit 3 outputs the write signal Swd that has a higher potential than the higher voltage source voltage VDD, and the write signal Swd is supplied to the anti-fuse storage elements 100 of the (m×n) memory cells 1 .

Accordingly, during the write operation, no large potential difference occurs between the two ends of the anti-fuse storage element 100 of each memory cell that is the non-writing target. Consequently, the write-disturb fault can be prevented from occurring. In addition, each memory cell 1 includes the anti-fuse storage element 100 and the selection transistor HNMT 1 , and thus the number of elements and the number of signals in the memory cell 1 are reduced significantly. Accordingly, even if the nonvolatile semiconductor memory device 51 is highly integrated, the increase in the area occupied by the memory cells can be reduced significantly.

Note that, in the second embodiment, the anti-fuse storage elements 100 of the n memory cells connected to each word line WLx are precharged simultaneously. Alternatively, the (m×n) memory cells 1 may be precharged sequentially.

A nonvolatile semiconductor memory device and its programming method according to a third embodiment of the invention will be described below by referring to the drawings. FIG. 8 is a timing chart illustrating a precharge operation of the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device of the third embodiment has a similar configuration to the configuration of the nonvolatile semiconductor memory device of the first embodiment. In addition, the selective transistor of each memory cell of the third embodiment has a threshold voltage Vthn that is higher than the corresponding voltage of the first embodiment.

FIG. 8 show that in the nonvolatile semiconductor memory device of the third embodiment, the write signal Swd, the bit line BL, and the word line WL are set at the lower voltage source voltage (ground potential) VSS before the precharge operation is executed.

Next, at a time T 1 , the voltage of the bit line BL is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD, for example, up to 3V.

Subsequently, at a time T 2 a , the voltage of the word line WL is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD, which is, for example, 3V. When the voltage of the word line WL reaches the higher voltage source voltage VDD (i.e., when the word line WL is activated), the selection transistor HNMT 1 is turned ON. The voltage of one of the source and the drain of the selection transistor HNMT 1 (i.e., the gate (the node N 1 ) of the anti-fuse storage element 100 ) is raised from the lower voltage source voltage (ground potential) VSS up to the higher voltage source voltage VDD. Thus, the precharge of the anti-fuse storage element 100 is executed. Here, the threshold voltage Vthn of the selection transistor HNMT 1 is set at a value that is higher than the corresponding voltage of the first embodiment. Accordingly, the potential of one of the source and the drain of the selection transistor HNMT 1 (the gate (node N 1 ) of the anti-fuse storage element 100 ) is set at (3V−Vthn).

Then, at a time T 3 a , the voltage of the word line WL is lowered from the higher voltage source voltage VDD down to the lower voltage source voltage (ground potential) VSS, so that the word line WL is deactivated. The anti-fuse storage element 100 is kept in the precharged state.

Next, at a time T 4 a , the voltage of the write signal Swd is raised from the lower voltage source voltage (ground potential) VSS up to a voltage that is higher than the higher voltage source voltage VDD (3V); for example, the voltage of the write signal Swd may be raised up to 6V (application of the voltage for writing). Here, the potential of one of the source and the drain of the selection transistor HNMT 1 (the gate (node N 1 ) of the anti-fuse storage element 100 ) is raised up to approximately 3V because a rise of potential is caused by a coupling that is caused by the write signal Swd of 6 V. To put it briefly, irrespective of how high the threshold voltage Vthn of the selection transistor HNMT 1 is, the potential of one of the source and the drain of the selection transistor HNMT 1 (the gate (node N 1 ) of the anti-fuse storage element 100 ) can be set at the higher voltage source voltage VDD before the execution of the writing.

As has been described thus far, the nonvolatile semiconductor memory device, which the third embodiment of the invention provides together with its programming method, includes the memory cell 1 , the precharge control circuit 2 , the power supply circuit 3 , the bit line driver DRBL, the word line driver DRWL, the multiplexer 103 a , and the multiplexer 103 b . The memory cell 1 includes the anti-fuse storage element 100 and the selection transistor HNMT 1 that has the high threshold voltage Vthn. Before the data is written into the anti-fuse storage element 100 of the memory cell 1 , the potential of the gate (node N 1 ) of the anti-fuse storage element 100 is set at (3V−Vthn) by the precharge control circuit 2 , the bit line driver DRBL, the word line driver DRWL, the multiplexer 103 a , and the multiplexer 103 b . Thus, the anti-fuse storage element 100 is set to be in the precharged state. When a voltage that is higher than the higher voltage source voltage VDD is applied to the node N 2 of the anti-fuse storage element 100 , the potential of the gate (node N 1 ) of the anti-fuse storage element 100 is raised up to approximately 3 V by the coupling.

Accordingly, during the write operation, no large potential difference occurs between the two ends of the anti-fuse storage element 100 of each memory cell that is the non-writing target. Consequently, the write-disturb fault can be prevented from occurring. In addition, each memory cell 1 includes the anti-fuse storage element 100 and the selection transistor HNMT 1 , and thus the number of elements and the number of signals in the memory cell 1 are reduced significantly. Accordingly, even if the nonvolatile semiconductor memory device 50 is highly integrated, the increase in the area occupied by the memory cell can be reduced significantly.

The above-described embodiments are not the only forms of carrying out the invention. Various modifications may be made without departing from the scope of the invention.

For example, in the above-described embodiments, P-channel MOS transistors are used as the anti-fuse storage elements, and N-channel MOS transistors are used as the selection transistors. Alternatively, N-channel MOS transistors may be used as the anti-fuse storage elements, and P-channel MOS transistors may be used as the selection transistors. In this case, it is preferable that the setting of the potentials of the node N 1 , the node N 2 , the bit line BL, the word line WL should be changed.