Dual-mode charger circuit

1. Technical Field

The present disclosure relates to a dual-mode charger circuit.

2. Description of Related Art

Portable devices, such as cordless phones and mobile phones, for example, utilize integrated circuits (ICs) to perform charge and protection functions. These ICs are generally expensive especially in mass quantities.

FIG. 1 is a block diagram of one embodiment of a dual-mode charger circuit; and

FIG. 2 is a detailed circuit diagram of the dual-mode charger circuit of FIG. 1 .

FIG. 1 is a block diagram of one embodiment of a dual-mode charger circuit 20 . The dual-mode charger circuit 20 may be used to charge a battery 30 of a portable mobile device (not shown), such as a cordless phone, a mobile phone, for example. The dual-mode charger circuit 20 comprises a first charge circuit 201 , a second charge circuit 202 , a mode switch circuit 203 , a temperature detection circuit 204 and a central processing unit (CPU) 205 .

The first charge circuit 201 and the second charge circuit 202 are connected in parallel between a power source 10 and the battery 30 , to provide a first charge path 206 and a second charge path 206 ′. In one embodiment, the battery 30 may be slowly charged only through the first charge path 206 , which is defined as a slow charge mode of the dual-mode charger circuit 20 . In another embodiment, the battery 30 may be charged quickly through both the first charge path 206 and the second charge path 206 ′, which is defined as a quick charge mode of the dual-mode charger circuit 20 .

The CPU 205 is connected to the battery 30 , to detect a capacity of the battery 30 and determine whether the detected capacity exceeds a predetermined capacity, such as 80% of the battery 30 being fully charged, and output a mode control signal according to the determination. The mode switch circuit 203 is connected between the CPU 205 and the second charge circuit 202 , to switch the second charger circuit 202 on/off according to the mode control signal. At the same time, the mode switch circuit 203 is also connected to the power source 10 .

The temperature detection circuit 204 is connected to the CPU 205 , to detect a temperature of the battery 30 and output to the CPU 205 . Thus, the CPU 205 outputs a temperature protection signal according to the detected temperature, and also switches the second charge circuit 202 on/off.

In one embodiment, when the dual-mode charger circuit 20 starts to charge the battery 30 , the CPU 205 detects the capacity of the battery 30 . If the detected capacity does not exceed the predetermined capacity, the CPU 205 outputs a high level signal, such as 3.3V, to the mode switch circuit 203 . Thus, the mode switch circuit 203 switches the second charge circuit 202 on, and the battery 30 is charged through both the first charge path 206 and the second charge path 206 ′ under the quick charge mode accordingly. If the detected capacity exceeds the predetermined capacity, the CPU 205 outputs a low level signal, such as 0V, to the mode switch circuit 203 . Thus, the mode switch circuit 203 switches the second charge circuit 202 off, and the battery 30 is charged only through the first charge path 206 under the slow charge mode accordingly.

Similarly, the temperature detection circuit 204 detects a temperature of the battery 30 and outputs to the CPU 205 . The CPU 205 determines whether the detected temperature exceeds a predetermined value and outputs a temperature protection signal. In one embodiment, the temperature protection signal is also a high level signal or a low level signal, which controls the mode switch circuit 203 to switch the second charge circuit 202 on/off.

In other words, if the detected temperature of the battery 30 exceeds the predetermined value, the CPU 205 outputs a low level signal of the temperature protection signal to the mode switch circuit 203 . Thus, the second charge circuit 202 is off, and the battery 30 is charged under the slow charge mode in order to achieve temperature protection function. In contrast, if the temperature of the battery 30 does not exceed the predetermined value, the CPU 205 outputs a high level signal of the temperature protection signal to the mode switch circuit 203 . Thus, the second charge circuit 202 is on, and the battery 30 is also charged under the quick charge mode.

It should be understood that as battery 30 is being charged by the dual-mode charger circuit 20 , the first charge circuit 201 always switches on. Thus, the battery 30 is charged under the slow charge mode consistently. However, the second charge circuit 202 is switched on/off based on the capacity and the temperature of the battery 30 . That is, the dual-mode charger circuit 20 determines whether battery 30 is charged under the quick charge mode based on the battery capacity or the temperature of the battery 30 .

FIG. 2 is a detailed circuit diagram of the dual-mode charger circuit 20 of FIG. 1 . The first charge circuit 201 comprises a first resistor R 1 , a first transistor Q 1 , a second transistor Q 2 and a second resistor R 2 . The first transistor Q 1 has a control end connected to the power source 10 via the first resistor R 1 , and a first output connected to the power source 10 directly. The second transistor Q 2 has a control end connected to a second output of the first transistor Q 1 , a first output connected to the control end of the first transistor Q 1 , and a second output connected to the battery 30 . The second resistor R 2 is connected to the control end of the second transistor Q 2 and ground. In one embodiment, the second transistor Q 2 and the second resistor R 2 form a bias circuit, to provide a bias voltage to the first transistor Q 1 in order to keep the first transistor Q 1 on. The first resistor R 1 limits current flowing through the first charge path 206 . The first transistor Q 1 and the second transistor Q 2 are pnp transistors, each having a base defined as the control end, an emitter defined as the first output and a collector defined as the second output.

Structures of the second charge circuit 202 are substantially the same as those of the first charge circuit 201 , which also comprises a first resistor R 3 , a first transistor Q 3 , a second transistor Q 4 and a second resistor R 4 , thus, description thereof is omitted. The only difference is that the second resistor R 4 is connected between the control end of the second transistor Q 4 and mode switch circuit 203 in the second charge circuit 202 .

The mode switch circuit 203 comprises a third transistor Q 5 . The third transistor Q 5 has a control end connected to the CPU 205 , a first output grounded and a second output connected to the second resistor R 4 of the second charge circuit 202 , and is switched on/off based on the mode control signal. Accordingly, the first transistor Q 3 and the second transistor Q 4 in the second charge circuit 202 can be also switched on/off. In one embodiment, the third transistor Q 5 is an npn transistor, which has a base defined as the control end, an emitter defined as the first output and a collector defined as the second output.

The temperature detection circuit 204 comprises a third resistor R 5 and a temperature detection resistor Rs connected in series between a power source Vcc and ground, and a junction of the third resistor R 5 and the temperature detection resistor Rs is connected to the CPU 205 . In one embodiment, the temperature detection resistor Rs is disposed close to the battery 30 to detect a temperature variation of the battery 30 and output to the CPU 205 . The temperature detection resistor Rs is a thermal resistor.

In one embodiment, when the dual-mode charger circuit 20 starts to charge the battery 30 , the CPU 205 detects the capacity of the battery 30 and outputs the mode control signal. If the detected capacity is lower than the predetermined capacity, the CPU 205 outputs the high level signal. The transistor Q 5 is on, and the transistors Q 3 , Q 4 of the second charge circuit 202 are switched on accordingly. Therefore, the battery 30 is charged through both the first charge path 206 and the second charge path 206 ′ under the quick charge mode. If the capacity of the battery 30 is higher than the predetermined capacity, the CPU 205 outputs the low level signal. The transistor Q 5 is off, and the transistors Q 3 , Q 4 of the second charge circuit 202 are switched off accordingly. Therefore, the battery 30 is charged only through the first charge path 206 under the slow charge mode.

Similarly, the temperature detection circuit 204 also detects the temperature of the battery 30 and outputs the detected temperature to the CPU 205 . Accordingly, the CPU 205 outputs to the temperature protection signal to protect the battery 30 .

In one embodiment, because a voltage difference between the base and the emitter of the transistors Q 1 or Q 3 is about 0.6V, a voltage added to the resistor R 1 or R 3 is also about 0.6V. Thus, when a short circuit occurs, no inrush current flows through the first charge circuit 201 and the second charge circuit 202 . In addition, in order to achieve the quick charge mode resistance of the resistor R 3 is smaller than that of the resistor R 1 , which reduces the current flowing through the first charge circuit 201 below that through the second charge circuit 202 .

The mode control signal and the temperature protection signal output from the CPU 205 are often influenced by noise to fluctuate, which leads the transistor Q 5 to switch on/off frequently. Consequently, the dual-mode charger circuit 20 lacks stability and components thereof have shortened life. In order to solve above problem, the dual-mode charger circuit 20 further comprises a fourth resistor R 6 and a fifth resistor R 7 . In one embodiment, the fourth resistor R 6 and the fifth resistor R 7 are connected in series between the power source 10 and the mode switch circuit 203 , to divide a voltage of the power source 10 . A junction of the fourth resistor R 6 and the fifth resistor R 7 is connected to the CPU 205 or the temperature detection circuit 204 , such that the divided voltage of the power source is added to the mode control signal or the temperature protection signal, which pulls up a direct current level of the mode control signal or the temperature protection signal. Therefore, the transistor Q 5 of the switch circuit 203 is controlled more precisely.

In detail, the fourth resistor R 6 is connected between the power source 10 and the CPU 205 , and the fifth resistor R 7 is connected between the CPU 205 and the mode switch circuit 203 . When the mode control signal or the temperature protection signal is at high level signal, a signal combining the divided voltage of the power source with the high level signal output from the CPU 205 directs the transistor Q 5 of the mode switch circuit 203 to switch on precisely. When the mode control signal or the temperature protection signal is at low level signal, no divided voltage of the fourth resistor R 6 and the fifth resistor R 7 is combined into the low level signal, thus, the transistor Q 5 of the mode switch circuit 203 does not operate.

In the present disclosure, the dual-mode charger circuit 20 utilizes discrete components to achieve charge and protection functions, at a low cost.

Although the features and elements of the present disclosure are described in various inventive embodiment in particular combinations, each feature or element can be configured alone or in various within the principles of the present disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.