Snapshot pixel circuit for minimizing leakage current in an imaging sensor having a two-pole integration switch

This application claims the benefit of provisional patent application Ser. No. 61/207,186 filed Feb. 9, 2009.

Applicants and their fellow workers have developed the Photoconductor on Active Pixel (POAP) image sensor technology for the last decade. Examples of these sensors are provided in U.S. Pat. Nos. 6,730,914, 7276,749 and 7,436,038 all of which are incorporated herein by reference. They have developed an amorphous silicon (a-Si:H) p-i-n photodiode coating (0.4 micron-0.7 micron spectrum). This photodiode coating is deposited on a pixelated CMOS readout array for visible imaging applications. Applicants are presently developing a microcrystalline germanium (μc-Ge) p-i-n photodiode coating (0.4 micron-1.6 micron spectrum). This photodiode coating is deposited on a pixelated CMOS readout array for visible (VIS), near infrared (NIR) and short wave infrared (SWIR) imaging applications. U.S. Pat. No. 6,730,914 teaches the use of direct injection pixel circuits for POAP image sensor applications.

Applicants' experiments have shown that microcrystalline germanium photodiode coatings and microcrystalline silicon photodiode coatings produce relatively very high leakage currents. And that prior art pixel circuits are not compatible with these microcrystalline photodiode coatings. The present invention provides pixel circuits, capable of operating in either “snapshot” or “rolling integration” mode, and compatible with a conformal photodiode coating. Preferred embodiments of the present invention are compatible with these coating materials, as well as others, including amorphous Silicon. The preferred pixel circuits includes additional transistors not provided in prior art pixel circuits to divert leakage current away from integration nodes when not integrating, to reset the integration node, and to buffer and select the integrated voltage.

In a first preferred embodiment, a six transistor (6T) circuit with five control lines, can provide conventional (i.e. kTC-noise limited) snapshot integration-then-read (ITR) capability, and also off-chip correlated double sampling (CDS) capability. In a second preferred embodiment, an eight transistor (8T) circuit with seven control lines, can provide conventional (i.e. kTC-noise limited) snapshot integration-then-read (ITR) capability and integrate-while-read (IWR) capability; and also off-chip correlated double sampling (CDS) capability.

The advantages of the first preferred embodiment are: less control lines (5 versus 7) routed to each pixel, less circuitry in a relatively small pixel (6 MOSFETS and one capacitor versus 8 MOSFETS and two capacitors), and lower readout noise. The additional circuitry and control lines required for the second preferred embodiment may require a pixel size larger than 6 microns×6 microns to accommodate but may also further reduce noise.

FIG. 1 is a drawing of a pixel circuit of the present invention.

FIG. 2 shows injection efficiency versus a current ratio.

FIG. 3 describes current flowing in two paths.

FIG. 4 shows and integration sequence.

FIG. 5 shows and off-chip readout sequence.

FIG. 6 shows a pixel circuit including a photodiode and additional features.

FIG. 7 shows noise simulations.

Pixel Circuit # 1

Pixel Circuit # 1 , displayed in FIG. 1 , includes the POAP photodiode, six MOSFETs, an integration capacitor, and five control lines. This circuit is designed to collect electrons (versus holes) from the photodiode. A direct injection input circuit interfaces with the POAP photodiode coating and attempts to maintain the voltage across the photodiode at a constant value. An integration switch controls the snapshot integration time. The integration capacitor collects electric charge from the photodiode. When the row readout select switch is closed, a source follower trans-impedance amplifier provides a current that is proportional to the collected charge. This current is directed to the periphery of the pixel array for amplification, digitization, and digital readout. The row reset switch, when closed, dumps the integrated charge and resets the voltage across the integration capacitor to zero. This pixel circuit can provide 1) snapshot integrate-then-read capability whereby all pixels in the array integrate at the same time over a period T INT followed by progressive row readout of the stored pixel charges, 2) rolling reset integration capability, and 3) off-chip CDS readout capability.

The pixel circuit can be divided into three sub-circuits; detector, integration switch, and readout sub-circuits. The basic operation of this pixel circuit is described here.

Detector

The detector sub-circuit (“Detector”) includes the POAP photodiode and the direct injection transistor T DI . This circuit attempts to hold the voltage across the photodiode, V PD , at a constant value, independent of the integrated charge on the capacitor C INT . This enables photodiode operation at a bias voltage that attempts to minimize dark current from the photodiode.

The injection efficiency η of the photodiode current through transistor T DI , dependent on the relative values (current divider) of the shunt resistance of the photodiode and the input impedance of transistor T DI , is

and

We can approximate the shunt resistance of our photodiode as

The injection efficiency η versus I PD /I dark @−1 V bias is displayed in FIG. 2 .

Integration Switch

The integration switch sub-circuit includes the two transistors T INTCTL and T CASCODE . The differential gate voltage, ΔV INT =V INTCTL −V CASCODE controls the current I o =I 1 +I 2 flowing through the two paths of the switch.

and

The currents I 1 /I o and I 2 /I o versus ΔV INT are displayed in FIG. 3 .

Readout Circuit

The readout sub-circuit includes the integration capacitor C INT , the source follower transistor T SF , the select transistor T SEL , and the reset transistor T RST . The integration capacitor C INT collects electric charge from the photodiode. When the select switch T SEL is closed, the source follower transistor T SF (trans-impedance amplifier) provides a current that is proportional to the collected charge on C INT . This current is directed to the periphery of the pixel array for amplification, digitization, and digital readout. The reset switch T RST , when closed, dumps the integrated charge on C INT and resets the voltage across C INT to zero.

Snapshot Integration

Integration-Then-Read

The snapshot integration readout sequence for Pixel Circuit # 1 is displayed in FIG. 4 . The reset switch T RST is opened, then the integration switch is opened (ΔV INT =V INTCTL −V CASCODE =1 V) to enable the photodiode current I o to flow to the integration capacitor C INT . After an integration time T INT , the integration switch is closed (ΔV INT =V INTCTL −V CASCODE =−1 V) to stop collection of charge on the integration capacitor C INT and to direct the photodiode current I o directly to the power supply. The charges on all of the pixels are then progressively readout row-by-row (approximately 90 ms readout time for a 14 kpixel×14 kpixel sensor). The charge values are digitized and stored off-chip.

Rolling Reset Integration

The rolling reset integration mode for Pixel Circuit # 1 is implemented by keeping the integration switch always opened (ΔV INT =V INTCTL −V CASCODE =1 V) to enable the photodiode current I o to flow continuously to the integration capacitor C INT . The rolling reset integration is then implemented in the same manner as a conventional 3T (source follower transistor T SF , select transistor T SEL and reset transistor T RST ) pixel circuit.

Correlated Double Sampling Integration

Pixel Circuit # 1 can also provide off-chip CDS readout, displayed in FIG. 5 . The reset switch T RST is opened, while keeping the integration switch closed (ΔV INT =V INTCTL −V CASCODE =−1 V). The initial charge on the integration capacitor C INT (after opening the reset switch T RST ) is the kTC (switching noise) charge (randomly different on each pixel). The kTC charges on all of the pixels are progressively readout row-by-row, digitized, and stored off-chip. Then the integration switch is opened (ΔV INT =V INTCTL −V CASCODE =1 V) to enable the photodiode current I o to flow to the integration capacitor C INT . After an integration time T INT , the integration switch is closed (ΔV INT =V INTCTL −V CASCODE =−1 V) to stop collection of charge on the integration capacitor C INT and to direct the photodiode current I o directly to the power supply. The final charge on each pixel is the signal (S) plus kTC charge. The charges S+kTC on all of the pixels are then progressively readout row-by-row, digitized, and stored off-chip. The two pixel images S+kTC and kTC are then digitally subtracted (S+kTC−kTC=S) to provide an image with the kTC noise removed.

Pixel Circuit # 2

Alternate Embodiment

Pixel Circuit # 2 , displayed in FIG. 6 , includes the POAP photodiode, eight MOSFETs, an integration capacitor, and seven control lines. This circuit is designed to collect electrons (versus holes) from the photodiode. A direct injection input transistor T DI interfaces with the POAP photodiode coating and attempts to maintain the voltage across the photodiode at a constant value. An integration switch (T INTCTL and T CASCODE ) controls the snapshot integration time. Two integration capacitors C 1 and C 2 collect electric charge from the photodiode. When the row readout select switch T SEL is closed, a source follower trans-impedance amplifier T SF provides a current that is proportional to the collected charge. This current is directed to the periphery of the pixel array for amplification, digitization, and digital readout. The row reset switches T RST1 and T RST2 when closed, dump the integrated charge and resets the voltage across the integration capacitors C 1 and C 2 to zero. This pixel circuit can provide 1) snapshot integrate-then-read capability whereby all pixels in the array integrate on capacitors C 1 and C 2 (transfer gate open) at the same time over a period T INT followed by progressive row readout of the stored pixel charges, 2) snapshot integrate-while-read capability whereby all pixels in the array integrate on capacitor C 1 (transfer gate T X closed) at the same time over a period T INT , followed by a transfer of charge (transfer gate T X open) from capacitor C 1 to capacitor C 2 , followed by progressive row readout of the stored pixel charges on capacitor C 2 , 3) rolling reset integration capability, and 4) off-chip CDS readout capability.

Pixel Circuitry

Pixel Circuit # 2 is essentially the same as Pixel Circuit # 1 , with the addition of a transfer gate T X and a second integration/charge storage capacitor C 2 .

Snapshot Integration

Integrate-Then-Read

The snapshot integration readout sequence for Pixel Circuit # 2 , displayed in FIG. 4 , is essentially the same as for Pixel # 1 . The transfer gate T X is kept always open for this integration mode. The reset switches T RST1 and T RST1 are opened, then the integration switch is opened (ΔV INT =V INTCTL −V CASCODE =1 V) to enable the photodiode current I o to flow to the integration capacitors C 1 and C 2 . After an integration time T INT , the integration switch is closed (ΔV INT =V INTCTL −V CASCODE =−1 V) to stop collection of charge on the integration capacitors C 1 and C 2 and to direct the photodiode current I o directly to the power supply. The charges on all of the pixels are then progressively readout row-by-row (approximately 90 ms readout time for a 14 kpixel×14 kpixel sensor). The charge values are digitized and stored off-chip.

Snapshot Integration Integrate-While-Read

The reset switch T RST1 is opened, then the integration switch is opened (ΔV INT =V INTCTL −V CASCODE =1 V) to enable the photodiode current I o to flow to the integration capacitor C 1 . After an integration time T INT , the integration switch is closed (ΔV INT =V INTCTL −V CASCODE =−1 V) to stop collection of charge on the integration capacitor C 1 and to direct the photodiode current I o directly to the power supply. The transfer gate T X is then opened to allow one half of the charge on capacitor C 1 to flow to capacitor C 2 (i.e. the two capacitor voltages will equalize). The transfer gate T X is then closed. The charges on capacitors C 2 on all of the pixels are then progressively readout row-by-row (approximately 90 ms readout time for a 14 kpixel×14 kpixel sensor). The charge values are digitized and stored off-chip. During this readout period, the pixel can integrate simultaneously on capacitor C 1 .

Rolling Reset Integration

The rolling reset integration mode for Pixel Circuit # 2 is essentially the same as for Pixel # 1 . The transfer gate T X is kept always open for this integration mode. The rolling reset integration mode is implemented by keeping the integration switch always opened (ΔV INT =V INTCTL −V CASCODE =1 V) to enable the photodiode current I o to flow continuously to the integration capacitors C 1 and C 2 . The rolling reset integration is then implemented in the same manner as a conventional 3T (source follower transistor T SF , select transistor T SEL , and reset transistor T RST ) pixel circuit.

Correlated Double Sampling Integration

The CDS integration mode for Pixel Circuit # 2 , displayed in FIG. 5 , is essentially the same as for Pixel # 1 . The transfer gate T X is kept always open for this integration mode. The reset switches T RST1 and T RST2 are opened, while keeping the integration switch closed (ΔV INT =V INTCTL −V CASCODE =−1 V). The initial charge on the integration capacitor C INT (after opening the reset switches T RST1 and T RST2 ) is the kTC (switching noise) charge (randomly different on each pixel). The kTC charges on all of the pixels are progressively readout row-by-row, digitized, and stored off-chip. Then the integration switch is opened to enable the photodiode current I o to flow to the integration capacitors C 1 and C 2 . After an integration time T INT , the integration switch is closed (ΔV INT =V INTCTL −V CASCODE =−1 V) to stop collection of charge on the integration capacitors C 1 and C 2 and to direct the photodiode current I o directly to the power supply. The final charge on each pixel is the signal (S) plus kTC charge. The charges S+kTC on all of the pixels are then progressively readout row-by-row, digitized, and stored off-chip. The two pixel images S+kTC and kTC are then digitally subtracted (S+kTC−kTC=S) to provide an image with the kTC noise removed.

Pixel Readout Noise

Noise simulations for the pixel circuits and integration modes are displayed in FIG. 7 . The snapshot integrate-while-read mode produces the most noise due to the added kTC noise incurred by the extra storage capacitor.

While there have been shown what are presently considered to be preferred embodiments of the present invention, it will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the scope and spirit of the invention.

For example, the polarity of the photodiode layer could be reversed so that electrons are collected on the pixel electrodes during pixel integration. Thus, the scope of the invention is to be determined by the appended claims and their legal equivalents.