Semiconductor device having a plurality of repair fuse units

The present application claims priority of Korean Patent Application No. 10-2009-0062905, filed on Jul. 10, 2009, which is incorporated herein by reference in its entirety.

Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a technology which processes information indicating whether through chip vias are defective.

In order to highly integrate a semiconductor device, various types of package methods have been proposed. In a chip stack method in which a plurality of semiconductor chips are stacked to form a semiconductor device, a through-chip-via is used to commonly transfer a signal to a plurality of semiconductor chips. In general, since semiconductor chips are fabricated of a silicon wafer, the through-chip-via is also called a Through-Silicon-Via (TSV).

When a defect occurs in a TSV, a repair operation is performed to substitute a normal TSV with a redundant TSV. The defect information of the TSV is desired to be provided to an internal circuit, in order to ensure normal operations of the semiconductor device. In other words, the internal circuit of the semiconductor device receiving information as to the defect selectively drives TSVs which may transfer a signal, among the plurality of SVs. That is, the internal circuit selectively drives the redundant TSVs and the normal TSVs. Therefore, the semiconductor device fabricated by the chip stack method is desired to be provided with a circuit capable of effectively transferring information as to defects of the TSVs.

An embodiment of the present invention is directed to a semiconductor device which stores defect information of TSVs outputted from repair fuse units into a plurality of latch units.

Another embodiment of the present invention is directed to a semiconductor device which stores defect information of TSVs outputted from repair fuse units into a plurality of latch units, and sequentially transfers the defect information through a defect information transfer TSV.

In accordance with an embodiment of the present invention, a semiconductor device includes: a plurality of stacked semiconductor chips; and a plurality of TSVs including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes: a plurality of repair fuse units configured to store information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units.

In accordance with another embodiment of the present invention, a semiconductor device includes: a plurality of stacked semiconductor chips; a plurality of TSVs including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of semiconductor chips; a plurality of repair fuse units provided in the respective semiconductor chips and configured to store information indicating at least one defect of the TSVs; and a TSV selection unit configured to selectively drive the plurality of TSVs depending on the stored defect information. The TSV selection unit selectively drives redundant TSVs and first TSVs, each of the semiconductor chips includes a plurality of latch units configured to store a plurality of signals indicating at least one TSV defect, outputted from the corresponding repair fuse units and allocated to the respective TSVs, and the plurality of TSV defect information signals are sequentially transferred to the TSV selection unit through a TSV for transferring the defect information.

FIG. 1 is a diagram conceptually illustrating the cross section of a semiconductor device in accordance with an embodiment of the present invention.

FIG. 2 illustrates an internal circuit of the semiconductor device of FIG. 1 .

Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

In general, logic signals and binary data of a circuit have a high level or a low level, depending on the logic levels thereof, and may be represented by “1” or “0”. Furthermore, the logic signals and data may have a high-impedance (Hi-Z) state, if necessary.

FIG. 1 is a diagram conceptually illustrating the cross section of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device includes a plurality of stacked semiconductor chips CHIP 1 to CHIP 4 , a plurality of normal TSVs 1 A to 3 A, a plurality of redundant TSVs 1 B to 3 B, a plurality of repair fuse units 21 _ 1 to 21 _ 3 , 22 _ 1 to 22 _ 3 , and 23 _ 1 to 23 _ 3 , and a TSV selection unit 6 . The plurality of TSVs 1 A- 1 B, 2 A- 2 B, and 3 A- 3 B are configured to commonly transfer a signal to the plurality of semiconductor chips CHIP 1 to CHIP 4 . The plurality of repair fuse units 21 _ 1 to 21 _ 3 , 22 _ 1 to 22 _ 3 , and 23 _ 1 to 23 _ 3 are provided in the respective semiconductor chips to store information as to defects in the TSVs. The TSV selection unit 6 is configured to selectively drive the plurality of TSVs 1 A- 1 B, 2 A- 2 B, and 3 A- 3 B in accordance with the defect information of the repair fuse units 21 _ 1 to 21 _ 3 , 22 _ 1 to 22 _ 3 , and 23 _ 1 to 23 _ 3 . In this case, the TSV selection unit 6 selectively drives redundant TSVs and normal TSVs.

The plurality of stacked semiconductor chips CHIP 1 to CHIP 3 include a plurality of latch units 11 _ 1 to 11 _ 6 , 12 _ 1 to 12 _ 6 , and 13 _ 1 to 13 _ 6 , respectively, which are configured to store a plurality of TSV defect information signals (that is, signals indicating defects in TSVs) outputted from the corresponding repair fuse units. The latch units are allocated to the respective TSVs. The plurality of TSV defect information signals stored in the plurality of latch units 11 _ 1 to 11 _ 6 , 12 _ 1 to 12 _ 6 , and 13 _ 1 to 13 _ 6 are sequentially transferred to the TSV selection unit 6 through a defect information transfer TSV 4 .

In this embodiment of the present invention, it has been described that each of the semiconductor chips CHIP 1 to CHIP 4 includes the plurality of repair fuse units and the plurality of latch units. However, it is also possible that any one or more of the semiconductor chips includes the plurality of repair fuse units and the plurality of latch units based on design needs.

The operation of the semiconductor device configured in such a manner will be described as follows.

The plurality of latch units 11 _ 1 to 11 _ 6 , 12 _ 1 to 12 _ 6 , and 13 _ 1 to 13 _ 6 provided in the respective semiconductor chips store a plurality of TSV defect information signals outputted from the repair fuse units of the corresponding semiconductor chip, and sequentially outputs the TSV defect information signals. That is, the plurality of latch units of the corresponding memory chip, which are implemented as shift registers, store a plurality of TSV defect information signals outputted from the corresponding repair fuse units, and then sequentially transfer the stored signals to the defect information transfer TSV 4 .

In the following description, it is assumed that a defect has occurred in the first normal TSV 1 A among the plurality of TSVs 1 A- 1 B, 2 A- 2 B, and 3 A- 3 B, and the first normal TSV 1 A is repaired by using the first redundant TSV 1 B.

The first normal TSV 1 A for commonly transferring a signal to the plurality of semiconductor chips CHIP 1 to CHIP 4 physically connects the plurality of semiconductor chips CHIP 1 to CHIP 4 . Therefore, even when a defect occurs in only a portion of the first normal TSV 1 A passing through a specific semiconductor chip, a repair operation for the normal TSV 1 A is performed in all of the semiconductor chips CHIP 1 to CHIP 4 such that the normal TSV 1 A is substituted with the first redundant TSV 1 B. Therefore, repair fuses included in the repair fuse units 21 _ 1 to 23 _ 1 of the respective semiconductor chips, which are allocated to the first normal TSV 1 A, are cut by the repair operation and indicate that a repair has occurred for the respective semiconductor chips.

As an example, the internal operations of the repair fuse units 23 _ 1 to 23 _ 3 and the latch units 13 _ 1 to 13 _ 6 provided in the third semiconductor chip CHIP 3 will be described. The repair fuse units 23 _ 1 to 23 _ 3 output a plurality of TSV defect information signals that indicate whether the repair fuses are cut or not, and the latch units 13 _ 1 to 13 _ 6 store the outputted TSV defect information signals. Then, the latch units 13 _ 1 to 13 _ 6 sequentially transfer the stored signals to the defect information transfer TSV 4 , and the transferred defect information signals are provided to the TSV selection unit 6 through the defect information transfer TSV 4 .

Through the plurality of TSV defect information signals, the TSV selection unit 6 selectively drives TSVs for transferring a signal, among the plurality of TSVs 1 A- 1 B, 2 A- 2 B, and 3 A- 3 B. That is, the TSV selection unit 6 selectively drives the redundant TSVs and the normal TSV (which operates in normal conditions), in order to commonly transfer a signal to the plurality of semiconductor chips CHIP 1 to CHIP 4 .

According to an example, the defect information transfer TSV 4 which sequentially transfers the plurality of TSV defect information signals includes a plurality of TSVs ( 4 A and 4 B) which are connected through a plurality of connection lines 5 _ 1 to 5 _ 4 in parallel (for example, by using a multi-parallel method). Therefore, reliability for accurately transferring the signals further increases. In such a parallel connection method, however, a large area is occupied. Therefore, the TSVs for transferring the TSV defect information signals may be configured through a single connection line or multiple parallel connection lines as appropriate.

FIG. 2 illustrates an internal circuit of the semiconductor device of FIG. 1 .

Referring to FIG. 2 , the internal operations of the repair fuse units 23 _ 1 to 23 _ 3 and the latch units 13 _ 1 to 13 _ 6 provided in the third semiconductor chip CHIP 3 are described in detail.

The repair fuse units 23 _ 1 to 23 _ 3 output a plurality of TSV defect information signals FUSE_OUT<0:5> corresponding to whether the repair fuses are cut or not, and the latch units 13 _ 1 to 13 _ 6 store the plurality of TSV defect information signals FUSE_OUT<0:5> outputted from the repair fuse units 23 _ 1 to 23 _ 3 .

Since the repair fuse of the first repair fuse unit 23 _ 1 is cut, the first TSV defect information signal FUSE_OUT<0> having a low level is transferred to the first latch unit 13 _ 1 allocated to the first normal TSV 1 A, and the second TSV defect information signal FUSE_OUT<1> having a high level is transferred to the second latch unit 13 _ 2 allocated to the first redundant TSV 1 B.

Since the repair fuse of the second repair fuse unit 23 _ 2 is not cut, the third TSV defect information signal FUSE_OUT<2> having a high level is transferred to the third latch unit 13 _ 3 allocated to the second normal TSV 2 A, and the fourth TSV defect information signal FUSE_OUT<3> having a low level is transferred to the fourth latch unit 13 _ 4 allocated to the second redundant TSV 2 B.

Since the repair fuse of the third repair fuse unit 23 _ 3 is not cut, the fifth TSV defect information signal FUSE_OUT<4> having a high level is transferred to the fifth latch unit 13 _ 5 allocated to the third normal TSV 3 A, and the sixth TSV defect information signal FUSE_OUT<5> having a low level is transferred to the sixth latch unit 136 allocated to the third redundant TSV 3 B.

When a shift signal SHIFT is activated, a plurality of multiplexers MUX, while not transferring the output signals of the repair fuse units 23 _ 1 to 23 _ 3 to the latch units 13 _ 1 to 13 _ 6 , transfer signals outputted from the latch units to each other to shift the signals through the latch units. When the shift signal SHIFT is activated, the latch units 13 _ 1 to 13 _ 6 operate like shift registers, and sequentially transfer the stored signals through the defect information transfer TSV 4 . The plurality of TSV defect information signals FUSE_OUT<0:5> transferred through the defect information transfer TSV 4 are finally provided to the TSV selection unit 6 . Through the plurality of TSV defect information signals FUSE_OUT<0:5>, the TSV selection unit 6 selectively drives TSVs among the plurality of TSVs 1 A- 1 B, 2 A- 2 B, and 3 A- 3 B for transferring a signal. That is, the TSV selection unit 6 selectively drives the redundant TSVs and the normal TSV for transferring signals, in order to commonly transfer a signal to the plurality of semiconductor chips CHIP 1 to CHIP 4 .

The semiconductor device in accordance with the embodiment of the present invention may store the defect information (that is, information as to defects) of the TSVs in the plurality of latch units. Furthermore, the semiconductor device sequentially receives the defect information of the TSVs and then selectively drive the TSVs among the plurality of TSVs for transferring a signal.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. For example, additional components may be used in addition to the above-described components of the exemplary embodiments of the present invention. Furthermore, the polarity of active high or active low for indicating an activation state of signal or circuit may be changed depending on different design needs. Furthermore, in implementing a same function, different configuration of transistors/elements may be used depending on different design needs.

In other words, PMOS transistors and NMOS transistors may be substituted for each other, and various types of transistors may be used as needed. Furthermore, logic gate combinations may be changed in implementing a same function. For example, NAND unit or NOR unit may be implemented by various combinations of NAND gates, NOR gates, and inverters. Such modifications would be apparent to those skilled in the art. Therefore, the enumeration thereof is omitted.