Calibration apparatus and method for capacitive sensing devices

The disclosed generally relates to a calibration apparatus and method for capacitive sensing devices.

The capacitance and capacitance sensitivity of capacitive sensing devices usually deviate from the design due to the non-ideal manufacturing and assembly process. Not only the capacitances of the components in a device may vary, but also the capacitance sensitivity of the components in the device may vary. This type of capacitance error and capacitance sensitivity error, through the amplification of the reading circuit, will be reflected to the zero-offset and the capacitance sensitivity for the overall device. Hence, the calibration method and circuit must be used to rectify the zero-offset and capacitance sensitivity back to within the specification tolerance.

Several calibration technologies for device offset are disclosed, such as, U.S. Pat. No. 5,659,262, U.S. Pat. No. 7,155,979, and U.S. Pat. No. 7,461,553. U.S. Pat. No. 5,659,262 disclosed a technology for offset trimming for a micromachined sensing device, using variable resistor to change the amplitude of input signal so as to control the voltages on the capacitor plates to achieve compensating the drift during the manufacturing process.

U.S. Pat. No. 7,155,979 and U.S. Pat. No. 7,461,533 disclosed self-calibrating oversampling electromechanical modulator and self-calibration method, for detecting the values at the equilibrium state, and calibrating the device's offset by changing the value of calibration capacitance.

A technology for calibrating shift and sensitivity of device is disclosed in U.S. Pat. No. 5,528,520. As shown in the calibration circuit of FIG. 1A and the calibration method of FIG. 1B , the calibration technology is to use two dependent digital codes of input voltages V 1 , V 2 , marked as 101 , 102 , and a code mirror 120 to generate four analog calibration codes. Then, the following fractional pulse density (FPD) equation is used to calibrate the zero-offset and sensitivity of the device:

FPD= B+G [( CA−CB )/( CA+CB )],

where zero-offset B=(½)+[VCM−(V 1 +V 2 )/2]/(V 1 −V 2 ), and sensitivity G=(VDD−VCM)(V 1 −V 2 ).

The disclosed exemplary embodiments may provide a calibration apparatus and method for capacitive sensing devices.

In an exemplary embodiment, the disclosed relates a calibration apparatus for capacitive sensing devices. The apparatus may comprise a calibration capacitor device, an integration circuit with latch function, at least two first switches, and at least a third switch. One end of the calibration capacitor device is connected to a capacitive sensing device. The integration circuit is connected to the capacitive sensing device and generates a voltage output and a latch output. A transforming circuit transforms a sensitivity calibration parameter into two corresponding analog signal outputs, and transforms a zero-offset calibration parameter into a corresponding analog signal output. The at least two first switches switch between the two corresponding analog signal outputs and a fixed voltage according to a system clock. The third switch switches between the corresponding analog signal output and another fixed voltage according to the system clock. The calibration apparatus also determines the switching between the two corresponding analog signal outputs according to the level of the latch output of the integration circuit.

In another exemplary embodiment, the disclosed relates to a calibration method for capacitive sensing devices. The calibration method may comprise: transforming an input sensitivity calibration parameter into two corresponding analog signals and outputting to two ends of a pair of sensing capacitor, transforming an inputted zero-offset calibration parameter into a corresponding analog signal and outputting to a calibration capacitive device; through a plurality of switches and according to a system clock and a latch output result of an integration circuit, performing the switching for the two corresponding analog signal outputs, the corresponding analog signal output and two fixed voltages; independently adjusting the value of the sensitivity calibration parameter and the value of the zero-offset calibration parameter so that the characteristics of a sensing device formed by a pair of sensing capacitors matching a sensitivity specification and a zero offset specification; and reading the output of the pair of sensing capacitors and generating a calibrated voltage output.

The foregoing and other features and aspects of the disclosed exemplary embodiments will become better understood from a careful reading of a detailed description provided herein below with appropriate reference to the accompanying drawings.

FIG. 1A and FIG. 1B are exemplary schematic views, illustrating a calibration circuit and method for any offsets or sensitivity variation of devices.

FIG. 2 shows an exemplary schematic view of a calibration apparatus for capacitive sensing devices, consistent with certain disclosed embodiments.

FIG. 3 shows an exemplary connection structure between a calibration capacitive device and a sensing device in a normal mode, consistent with certain disclosed embodiments.

FIG. 4 shows an exemplary connection structure between a calibration capacitive device and a sensing device in a self-test mode, consistent with certain disclosed embodiments.

FIG. 5A shows a schematic view of an exemplary transformer, consistent with certain disclosed embodiments.

FIG. 5B shows a schematic view of another exemplary transformer, consistent with certain disclosed embodiments.

FIG. 6 shows an exemplary schematic view of voltage transformation of a calibration voltage, consistent with certain disclosed embodiments.

FIG. 7A-FIG . 7 D show the use of two independent calibration codes to control the voltages of the upper and lower electroplates of capacitive device, by a system clock and an output of an integration circuit, consistent with certain disclosed embodiments.

FIG. 8 shows the change of slope of a calibration curve by adjusting the calibration capacitance of a programmable capacitor, consistent with certain disclosed embodiments.

FIG. 9 shows an exemplary flowchart of a calibration method for capacitive sensing devices, consistent with certain disclosed embodiments.

FIG. 10 shows an exemplary flowchart of changing zero offset parameter or sensitivity calibration parameter alone to independently calibrate zero offset or sensitivity, consistent with certain disclosed embodiments.

FIG. 11 shows an exemplary schematic view illustrating how to use switch outputs and a fixed voltage/self-test voltage to perform normal mode or self-test mode, consistent with certain disclosed embodiments.

The disclosed exemplary embodiments use two independent digital calibration codes to handle voltage control of the zero offset and sensitivity analog drive of the sensing device. By changing any calibration code of the device offset or sensitivity alone, the exemplary embodiments may accomplish the independent calibration of the zero offset or sensitivity of a sensing device, where the capacitor used in calibration may be a programmable calibration capacitor to improve the calibration precision of zero offset.

FIG. 2 shows an exemplary schematic view of a calibration apparatus for capacitive sensing devices, consistent with certain disclosed embodiments. Referring to FIG. 2 , calibration apparatus 200 may comprise a calibration capacitive device 205 , a transformer 210 , an integration circuit 220 with a latch function, at least two first switches 230 , and at least a third switch 250 . One end of calibration capacitive device 205 is connected to a capacitive sensing device 260 . Calibration capacitive device 205 includes at least a calibration capacitor.

Integration circuit 220 is connected to capacitive sensing device 260 , and is responsible for reading a sensing capacitance and generating a corresponding voltage output V OUT and a latch output.

Transformer 210 transforms an inputted zero offset calibration parameter 211 into a corresponding analog signal output, such as, analog calibration voltage V 3 , and transforms an inputted sensitivity calibration parameter 222 into two corresponding analog signal outputs, such as, a pair of analog calibration voltages (V 1 and V 2 ). Analog calibration voltage V 3 may be outputted through third switch 250 to calibration capacitive device 205 , and analog calibration voltages V 1 and V 2 , for example, may be outputted through at least a second switch 240 and at least two first switches 230 to the ends of a pair of sensing capacitors (CA and CB) so as to adjust the characteristic to match an zero offset specification and a sensitivity specification.

In other words, transformer 210 transforms inputted sensitivity calibration parameter 211 and zero offset calibration parameter 222 into calibration voltages, such as, calibration voltages V 1 , V 2 , V 3 , and outputs the voltages through the switches to the ends of a capacitive sensing device and a calibration capacitor so as to adjust the characteristic to within the specifications of zero offset and sensitivity.

At least two first switches 230 and at least a third switch 250 , according to the high and low of a clock level, performs switching of analog calibration voltages, such as, V 1 , V 2 , V 3 . Based on the high and low levels of the latch output of integration circuit 220 , calibration apparatus 200 determines the switching of two corresponding signal outputs. For example, based on the latch output result of integration circuit 220 , the calibration apparatus may use at least a second switch 240 to switch between the two corresponding signal outputs. In other words, through at least two first switches 230 and at least a second switch 240 and at least a third switch 250 , calibration apparatus 200 may use the clock and the high and low levels 220 a of the latch output of integration circuit 220 to control the voltages on the upper and lower electroplates of the capacitive device.

Take FIG. 2 as an example. Two first switches 230 perform the switching of two corresponding analog signals (V 1 , V 2 ) provided by transformer 210 and a fixed voltage VR according to the high and low levels of a system clock. Third switch 250 performs the switching of a corresponding analog signals V 3 provided by transformer 210 and a fixed voltage VCM according to the high and low levels of system clock. The two outputs of second switch 240 perform the switching of two analog signals V 1 , V 2 provided by transformer 210 according to the high and low levels of latch output 220 a of integration circuit 220 . Fixed voltage VR is higher than or equal to zero voltage and is lower than or equal to power supply voltage, and voltage VR may be power supply voltage, zero voltage or other fixed voltages. Another fixed voltage VCM is higher than or equal to zero voltage and is lower than or equal to power supply voltage, and voltage VCM may be half of the power supply voltage or other fixed voltages.

Calibration apparatus 200 may comprise sensing capacitance 260 . Sensing capacitance 260 may be a three-end capacitive sensing device formed by sensing capacitors CA and CB, where one end is common to sensing capacitors CA and CB and the other two ends are the other two ends of sensing capacitors CA and CB. Sensing capacitors CA and CB may be differential, at least one variable capacitor, at least a fixed capacitor, or any combination of the above capacitors, where nodes VCJ, VCA and VCB are the two voltages of calibration capacitive device 205 , sensing capacitors CA and CB, respectively. Calibration capacitive device 205 may be programmable capacitor or fixed capacitance or any combination of the above.

Calibration apparatus 200 may operate in a normal mode or in a self-test mode. When operating in a normal mode, as shown in FIG. 3 , node VCA is connected to sensing capacitor CA, node VCB is connected to sensing capacitor CB, while one end of calibration device 205 is connected to node VCJ and the other end is connected to a fixed voltage 308 . Calibration capacitive device 205 may be realized in various structures; for example, calibration capacitive device 205 may include a first calibration capacitor 305 a and a second calibration capacitor 305 b , where one end of first calibration capacitor 205 a is connected to node VCJ and the other end of first calibration capacitor 305 a is the common end with second calibration node 305 b and is connected to capacitive sensing device 260 , while the other end of second calibration capacitor 305 b is connected to fixed voltage 308 . When calibration apparatus 200 operates in the normal mode, calibration apparatus 200 reads the values of sensing capacitors CA and CB. First calibration capacitor 305 a and second calibration capacitor 305 b may both be programmable capacitors, fixed capacitors, or any combination of the above.

When operating in self-test mode, as shown in FIG. 4 , node VCA is connected to sensing capacitor CA, node VCB is connected to one end of second calibration capacitor 305 b , node VCJ is connected to one end of first calibration capacitor 305 a while a self-test voltage VST is connected to sensing capacitor CB. External voltage VST may use electrostatic force to change the capacitance of differential capacitors CA and CB to perform self test.

As shown in FIG. 5A , transformer 210 may include a decoder 511 and a digital-to-analog converter (DAC) 512 . Decoder 511 decodes sensitivity parameter 222 into two symmetric parameters 511 a , 511 b , and DAC 512 transforms symmetric parameters 511 a , 511 b into two analog output voltages V 1 , V 2 . DAC 512 transforms input parameters, including two symmetric parameters 511 a , 511 b and zero offset calibration parameter 211 into analog voltage outputs, including V 1 , V 2 and V 3 .

As shown in FIG. 5B , at least a second switch 240 may be placed inside transformer 210 between decoder 511 and DAC 512 , to perform switching between two symmetric parameters 511 a , 511 b according to the high and low levels of latch output 220 a of integration circuit 220 , and outputs to DAC 512 .

Integration circuit 240 may be a Sigma-Delta modulator realized, for example, with an integrator, a comparator and a latch.

FIG. 6 shows an exemplary schematic view of voltage transformation of a calibration voltage, consistent with certain disclosed embodiments, where VDG is the voltage difference between V 1 and VCM, or between V 2 and VCM. VCM is the common mode voltage, and GND is the ground. As shown in FIG. 6 , the voltage transformation relation among VDG, VCM, V 1 and V 2 is:

VDG =( V 1− V 2)/2, VCM =( V 1+ V 2)/2;

i.e., V 1 =VCM+VDG, V 2 =VCM−VDG.

The overall output voltage VOUT of calibration apparatus 200 may be expressed as the following equation:

V OUT= VDD×{ ½+( VJ/ 2 VDG )×[ CJ /( CA+CB )]+( VCM/ 2 VDG )×[( CA−CB )/( CA+CB )]},

where CJ is the calibration capacitance of calibration capacitive device 205 , VJ=V 3 −VCM.

As shown in the above equation, through changing VJ and CJ, the zero offset may be adjusted, i.e., the result of {½+(VJ/2VDG)×[CJ/(CA+CB)]}. The calibration of two parameters may greatly improve the precision of zero offset, while changing VDG may adjust sensitivity, i.e., the output result of {(VCM/2VDG)×[(CA−CB)/(CA+CB)]}. Because VDG and VJ are independent calibration parameters, changing any parameter of zero offset or sensitivity of the device alone may accomplish the independent calibration of the zero offset or sensitivity. In comparison with the dependent calibration, this independent calibration method may improve the ease of calibration.

FIG. 7A-FIG . 7 D further show the use of two independent codes VDG, VJ through clock and the output of integration circuit to control the voltages of the upper and lower electroplates of the capacitive device, consistent with certain disclosed embodiments. FIG. 7A shows the voltage transformation of VCA, FIG. 7B and FIG. 7C show voltage transformations of VCB and VCJ respectively, and FIG. 7D shows an exemplary schematic view of the clock switching.

In the examples of FIGS. 7A-7C , at least two first switches 230 and at least a second switch 240 may be, such as, Delta Sigma symmetric design, and control the voltages of the upper and lower electroplates of the capacitive device through clock and the latch output of the integration circuit. When latch output is logic 0 (low), second switch 240 stays the same, and directly passes outputs V 1 , V 2 from transformer 210 to the first switch set for clock switching. When latch output is logic 1 (high), second switch 240 exchanges outputs V 1 , V 2 from transformer 210 , and passes to first switch 230 for clock switching. In this manner, the switching between different voltages may be used to accomplish the calibration of zero offset and sensitivity of the capacitive device.

FIGS. 7A-7C show how to use the clock and latch output of the integration circuit to control the voltage of the upper and lower electroplates of a differential capacitive device. In the example of FIG. 7A , the upper electroplate uses calibration voltage V 1 =VCM+VDG when latch output LATCH=0 (low), and uses calibration voltage V 2 =VCM−VDG when latch output LATCH=1 (high), and outputs to sensing capacitor CA for the independent calibration of sensitivity. In the example of FIG. 7C , the lower electroplate uses calibration voltage V 2 =VCM−VDG when latch output LATCH=0 (low), and uses calibration voltage V 1 =VCM+VDG when latch output LATCH=1 (high), and outputs to sensing capacitor CB for the independent calibration of sensitivity.

FIG. 7B describes the use of zero offset calibration parameter. Output V 3 of transformer 210 , through clock control, is outputted to the common end of the sensing capacitor through programmable calibration capacitor CJ to perform the independent calibration of the zero offset. Hence, the disclosed calibration apparatus 200 may use two independent calibration codes VDG, VJ to independently change the offset and sensitivity of the sensing device.

Calibration parameters, such as, zero offset calibration parameter 211 , sensitivity calibration parameter 222 , or capacitive calibration parameter, may be pre-stored in a storage device. The storage device may also store at least an adjustment value of sensitivity calibration parameter 222 , and at least an adjustment value of zero offset calibration parameter 211 .

The adjustment of the capacitance of calibration capacitor CJ of calibration capacitive device 205 may change the slope of the calibrates curve, i.e., CJ/(CA+CB), so that the circuit may effectively reduce the margin tolerance of zero offset when calibrating the offset, as shown in the example of FIG. 8 . In FIG. 8 , the x-axis is the analog calibration voltage VJ, with unit volt, and the y-axis is the count of latches, with a clock of 500 KHZ. Calibration curves 810 , 820 , 830 are the transformation results of CJ/(CA+CB) at the ratio of 0.5, 1.0, 1.5, respectively.

FIG. 9 shows an exemplary flowchart of a calibration method for capacitive sensing devices, consistent with certain disclosed embodiments. Referring to FIG. 9 , an inputted sensitivity calibration parameter is transformed into two corresponding analog signals then the two corresponding analog signals are outputted to two ends of a pair of sensing capacitors, and an input zero offset calibration parameter is transformed into a corresponding analog signal then the corresponding analog signal is outputted to a calibration capacitor, as shown in step 910 . In step 920 , according to a system clock and a latch output of an integration circuit, a plurality of switches are used to perform the switching for the two corresponding signal outputs, the corresponding analog signal output and two fixed voltages.

In step 930 , the method independently adjusts the value of sensitivity calibration parameter and the value of zero offset calibration parameter so that the characteristics of a sensing device formed by a pair of sensing capacitors meet a sensitivity specification and a zero offset specification. In step 940 , the output of the sensing capacitor is read and a calibrated voltage output is generated.

In step 920 , the plurality of switches at least includes a second switch, two first switches, and a third switch. As described, second switch switches between two corresponding analog signal outputs according to the high and low levels of the latch output of the integration circuit, two first switches switch between the two corresponding analog signal outputs and the fixed voltage VR according to the high and low levels of system clock, and third switch switches between the corresponding analog signal output and another fixed voltage VCM according to the high and low levels of system clock. Through these switches, the switching of three analog calibration signal outputs may be performed by such as, Delta Sigma symmetric design.

The exemplary flowchart of FIG. 10 further describes how step 920 independently adjust the characteristics of sensing device to respectively meet a zero offset specification and a sensitivity specification, consistent with certain disclosed embodiments. As shown in FIG. 10 , the independent adjustment of sensitivity and zero offset calibration parameters may be executed until the specifications are met.

First, the value of sensitivity calibration parameter is adjusted (step 1010 ) and whether the sensitivity meets the specification is checked (step 1015 ), until the sensitivity specification is met. Then, whether the zero offset specification is met is checked (step 1020 ); if so, the process terminates; otherwise, after inputting zero offset calibration parameter, the value of zero offset calibration parameter is adjusted (step 1025 ), and whether the zero offset meets the zero offset specification is checked (step 1030 ), until the zero offset specification is met.

Recall the exemplary embodiment of FIG. 4 . The disclosed calibration apparatus may also operate in a self-test mode. The exemplary embodiment may further include two switches to perform the self-test mode. FIG. 11 shows an exemplary schematic view illustrating how to use switch outputs and a fixed voltage VR/self-test voltage VST to perform normal mode or self-test mode, consistent with certain disclosed embodiments.

Referring to FIG. 11 , calibration apparatus 200 may further include a switch 1122 and another switch 1124 . In normal mode, switch 1122 is switched to fixed voltage VR, therefore, one end of second calibration capacitor 305 b is connected to the fixed voltage VR. In addition, switch 1124 is switched to the output of first switch 230 , therefore, sensing capacitor CB is connected to VCB. In self-test mode, switch 1122 is switched to the output of first switch 230 , therefore, one end of second calibration capacitor 305 b is connected to VCB. In addition, switch 1124 is switched to self-test voltage VST, i.e., sensing capacitor CB is connected to self-test voltage VST, therefore, the test of the sensing device may be performed with voltage VST.

In summary, the disclosed calibration apparatus and method for capacitive sensing devices use independent digital calibration parameters and uses a system clock and integration circuit output to control the voltages of capacitive devices so that a calibration capacitive device may change the calibration voltage according to the system clock. In this manner, the overall voltage of the sensing device may be adjusted for calibrating the zero offset and sensitivity. In addition to providing the independent zero offset and sensitivity and greatly reducing calibration complexity, the disclosed exemplary embodiments may effectively reduce the zero offset margin tolerance in the calibration capacitive device design to achieve high precision. The disclosed calibration apparatus for a capacitive sensing device may also perform the self test.

Although the present invention has been described with reference to the disclosed exemplary embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.