Power supply circuit

1. Technical Field

The present disclosure relates to power supply circuits and, particularly, to a power supply circuit to supply a voltage to an element of a circuit board.

2. Description of Related Art

Most motherboards include memory chips. Power supply circuits are used to provide voltages to the memory chips. These power supply circuits may include some voltage converting chips. However, these voltage converting chips are very expensive and complicated.

The drawing is a circuit diagram of an exemplary embodiment of a power supply circuit.

Referring to the drawing, an exemplary embodiment of a power supply circuit 100 is arranged in a motherboard to supply a 1.5 volts (V) voltage to an element, such as a memory 200 . The power supply circuit 100 includes a single-phase pulse width modulation (PWM) signal controller U, two npn transistors Q 1 and Q 2 , two n-channel metal-oxide semiconductor field-effect transistors (NMOSFETs) Q 3 , Q 4 , fourteen resistors R 1 -R 14 , nine capacitors C 1 -C 9 , two inductors L 1 , L 2 , a diode device D 1 , and a 5 V power supply Vcc. In one embodiment, the PWM signal controller U is an ISL6341CRZ single-phase PWM signal controller. The diode device D 1 is a BAT54C diode device including two parallel diodes. The memory 200 may be a double data rate 3 (DDR3) memory.

An enable pin COM/EN of the PWM signal controller U is connected to a collector of the transistor Q 2 . An emitter of the transistor Q 2 is grounded. A base of the transistor Q 2 is connected to a collector of the transistor Q 1 and connected to the power supply Vcc via the resistor R 1 . An emitter of the transistor Q 1 is grounded. A base of the transistor Q 1 is connected to an enable control signal receiving terminal SLP_S4_N via the resistor R 2 , to receive an enable control signal. The enable pin COM/EN of the PWM signal controller U is also connected to a feedback pin FB of the PWM signal controller U via the capacitor C 3 .

A first terminal of the resistor R 7 is connected to the enable pin COM/EN of the PWM signal controller U. A second terminal of the resistor R 7 is connected to the feedback pin FB of the PWM signal controller U via the capacitor C 4 . The feedback pin FB of the PWM signal controller U is grounded via the resistor R 8 , and connected to a voltage output terminal P1V5_DDR3 via the resistor R 9 . The voltage output terminal P1V5_DDR3 is used to connect to the memory 200 to provide the 1.5V voltage to the memory 200 . A detecting pin VOS of the PWM signal controller U is grounded via the resistor R 11 , and connected to the voltage output terminal P1V5_DDR3 via the resistor R 12 . A first terminal of the capacitor C 5 is connected to a node between the resistor R 9 and the feedback pin FB of the PWM signal controller U. A second terminal of the capacitor C 5 is connected to a node between the resistor R 9 and the voltage output terminal P1V5-DDR3 via the resistor R 10 . The capacitor C 6 is connected between the voltage output terminal P1V5_DDR3 and ground.

A power pin VCC of the PWM signal controller U is connected to the power supply Vcc via the resistor R 14 and grounded via the capacitor C 9 . A boot pin BOOT of the PWM signal controller U is connected to a cathode C of the diode device D 1 . Two anodes A, B of the diode device D 1 are connected to the power supply Vcc. The boot pin BOOT is also connected a first terminal of the resistor R 6 . A second terminal of the resistor R 6 is connected to a phase pin PHASE of the PWM signal controller U via the capacitor C 2 . The phase pin PHASE of the PWM signal controller U is connected to the voltage output terminal P1V5_DDR3 via the inductor L 1 , and connected to a first terminal of the resistor R 3 . A second terminal of the resistor R 3 is grounded via the capacitor C 1 . A high-pass driving pin UGATE of the PWM signal controller U is connected to a gate of the FET Q 3 via the resistor R 4 . A drain of the FET Q 3 is connected to the power supply Vcc via the inductor L 2 . The capacitor C 7 is connected between the drain of the FET Q 3 and ground. The capacitor C 8 is connected between the drain of the FET Q 3 and ground.

A source of the FET Q 3 is connected to a drain of the FET Q 4 and the phase pin PHASE of the PWM signal controller U. The gate of the FET Q 3 is also connected to the drain of the FET Q 4 via the resistor R 5 . A low-pass driving pin LGATE/OC of the PWM signal controller U is connected to a gate of the FET Q 4 . A source of the FET Q 4 is grounded. The low-pass driving pin LGATE/OC of the PWM signal controller U is also grounded via the resistor R 13 . A ground pin GND and a data pin EPAD of the PWM signal controller U are both grounded.

In use, when the enable control signal receiving terminal SLP_S4_N receives a low voltage level signal, such as 0V voltage, that means the motherboard is in an S4 status (in S4 status, memories and hard disk drives of the motherboard are not powered). The transistor Q 1 is turned off, and the transistor Q 2 is turned on. The enable pin COM/EN of the PWM signal controller U is at a low voltage status, therefore the PWM signal controller U is inactive.

When the enable control signal receiving terminal SLP_S4_N receives a high voltage level signal, such as 5V voltage, that means the motherboard is not in the S4 status. The transistor Q 1 is turned on, and the transistor Q 2 is turned off. The enable pin COM/EN of the PWM signal controller U is at a high voltage status, therefore the PWM signal controller U becomes activated. The high-pass driving pin UGATE of the PWM signal controller U outputs a high level voltage signal and a low level voltage signal in an alternating order to control the FET Q 3 to turn on and turn off repeatedly. Furthermore the low-pass driving pin LGATE of the PWM signal controller U alternately outputs a low level voltage signal and a high level voltage signal to alternately control the FET Q 4 to be turned off and turned on. As a result, the FET Q 3 and the FET Q 4 are at different states at any given time. At the same time, the phase pin PHASE of the PWM signal controller U outputs a PWM signal to a first terminal of the inductor L 1 and the power supply Vcc outputs a 5 V voltage to the first terminal of the inductor L 1 via the capacitor C 2 , the resistor R 6 , and the diode device D 1 , and then a second terminal of the inductor L 1 outputs the 1.5V voltage to the voltage output terminal P1V5_DDR3 to supply the 1.5V voltage to the memory 200 .

The 1.5V voltage is also fed back to the feedback pin FB of the PWM signal controller U via the resistors R 9 , R 8 , to adjust output signals from the high-pass driving pin UGATE, the low-pass driving pin LGATE, and the phase pin PHASH of the PWM signal controller U, to stabilize the 1.5V voltage.

It is to be understood, however, that even though numerous characteristics and advantages of the embodiments have been set forth in the foregoing description, together with details of the structure and function of the embodiments, the disclosure is illustrative only, and changes may be made in details, especially in matters of shape, size, and arrangement of parts within the principles of the embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.