Data transmitter and related semiconductor device

This application claims the benefit of Korean Patent Application No. 10-2009-0028533 filed on Apr. 2, 2009, the subject matter of which is hereby incorporated by reference.

The inventive concept relates to semiconductor devices. More particularly, the inventive concept relates to a data transmitter and a semiconductor device including the data transmitter.

Multilevel input/output (I/O) methods have been introduced in order to transmit and receive large quantities of data without necessarily increasing data transmission speed. Multilevel I/O methods may use a variety of digital modulation techniques including, for example, pulse amplitude modulation (PAM), pulse duration modulation (PDM), and pulse position modulation (PPM).

According to an aspect of the inventive concept, there is provided a semiconductor device transmitting data using a multilevel signal, the semiconductor device comprising; a parity bit control unit configured to generate a parity bit in accordance with a number of the data having a most significant bit (MSB) and a least significant bit (LSB) that are different, a data conversion unit configured to either inversely output one of the MSB and LSB, or output the data without a change in response to the parity bit, and a plurality of transmission units configured to transmit data output from the data conversion unit using the multilevel signal.

According to another aspect of the inventive concept, there is provided a transmitter transmitting data using a multilevel signal, the transmitter comprising; a first voltage control unit configured to disconnect a power voltage source and an output terminal of the transmitter when a first bit of the data is in a first logic state, a second voltage control unit configured to disconnect a ground voltage source and the output terminal of the transmitter when the first bit of the data is in a second logic state, a third voltage control unit configured to disconnect the power voltage source and the output terminal of the transmitter when the first bit and a second bit of the data are in the first logic state, a fourth voltage control unit configured to disconnect the ground voltage source and the output terminal of the transmitter when the first bit and the second bit are in the second logic state, a fifth voltage control unit configured to disconnect the power voltage source and the output terminal of the transmitter when the first bit and the second bit are in the second logic state, and a sixth voltage control unit disconnecting the ground voltage source and the output terminal of the transmitter when the first bit and the second bit are in the first logic state.

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the inventive concept;

FIG. 2A is a table listing the first through fourth data of FIG. 1 and corresponding parity bits to be transmitted;

FIG. 2B is a table listing the first through fourth data of FIG. 2B and corresponding parity bits as actually transmitted;

FIG. 3 is a circuit diagram of a transmitter according to an embodiment of the inventive concept; and

FIG. 4 is a table listing possible voltages apparent at the output terminal of the transmitter of FIG. 3 in accordance with various logic states for the data applied to the transmitter.

The attached drawings illustrate several embodiments of the inventive concept and may be referred to in order to gain a better understanding of the inventive concept, the merits thereof, and the objectives accomplished by the exemplary implementations of the inventive concept.

Hereinafter, the inventive concept will be described in some additional detail with reference to the attached drawings. Like reference numerals in the drawings denote like elements.

FIG. 1 is a block diagram of a semiconductor device 100 according to an embodiment of the inventive concept. Referring to FIG. 1 , the semiconductor device 100 comprises a parity bit control unit 110 , a data conversion unit 150 , and a plurality of transmission units TX. As illustrated in FIG. 1 , the semiconductor device 100 transmits first data D 0 < 1 > and D 0 < 0 >, second data D 1 < 1 > and D 1 < 0 >, third data D 2 < 1 > and D 2 < 0 >, and fourth data D 3 < 1 > and D 3 < 0 >. However, the inventive concept is not limited to only this number and arrangement of data. Indeed, any reasonable number and arrangement of transmitted data bits is contemplated by embodiments of the inventive concept. In the following description, however, only a case wherein the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > are transmitted will be described.

The parity bit control unit 110 is configured to change the logic state of a parity bit according to the number of data in which the most significant bits (MSBs) D 0 < 1 >, D 1 < 1 >, D 2 < 1 >, and D 3 < 1 > and the least significant bits (LSBs) D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are different, of the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > that are transmitted by the semiconductor device 100 . For example, of the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, when the number of data in which the MSBs and the LSBs are different is not greater than half of the total number of data, the parity bit control unit 110 may change the parity status to a first logic state. When the number of data in which the MSBs and the LSBs are different is greater than half of the total number of data, the parity bit control unit 110 changes the parity status to a second logic state. In the following description, the first logic state is assumed to be a logically “low” state, while the second logic state is assumed to be a logically “high” state. However, even if these state assumptions were reversed, the benefits of the inventive concept would be similarly obtained.

The parity bit control unit 110 in the illustrated embodiment of FIG. 1 comprises first through fourth XOR gates 121 , 122 , 123 , and 124 , a counter 130 , and a parity bit generation unit 140 . As will be understood by those skilled in the art the choice of four XOR gates is merely illustrative, and the inventive concept is not limited thereto. Indeed, a semiconductor device designed in accordance with the inventive concept may include any reasonable number of XOR gates configured to transmit a corresponding number of data bits.

Returning to FIG. 1 , the first XOR gate 121 determines whether the MSB D 0 < 1 > and the LSB D 0 < 0 > of the first data D 0 < 1 > and D 0 < 0 > have the same logic state by performing an exclusive XOR operation on the input MSB D 0 < 1 > and LSB D 0 < 0 > of the first data D 0 < 1 > and D 0 < 0 >. The second XOR gate 122 determines whether the MSB D 1 < 1 > and the LSB D 1 < 0 > of the second data D 1 < 1 > and D 1 < 0 > have the same logic state by performing an exclusive XOR operation on the input of the MSB D 1 < 1 > and the LSB D 1 < 0 > of the second data D 1 < 1 > and D 1 < 0 >. The third XOR gate 123 determines whether the MSB D 2 < 1 > and the LSB D 2 < 0 > of the third data D 2 < 1 > and D 2 < 0 > have the same logic state by performing an exclusive XOR operation on the input of the MSB D 2 < 1 > and the LSB D 2 < 0 > of the third data D 2 < 1 > and D 2 < 0 >, and the fourth XOR gate 124 similarly determines whether the MSB D 3 < 1 > and the LSB D 3 < 0 > of the fourth data D 3 < 1 > and D 3 < 0 > have the same logic state by performing an exclusive XOR operation on the input of the MSB D 3 < 1 > and the LSB D 3 < 0 > of the fourth data D 3 < 1 > and D 3 < 0 >.

The counter 130 is configured to count (i.e., to generate a “count value” indicating) the number of incidences wherein the MSB and the LSB are different between the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > using output signals received from the first through fourth XOR gates 121 , 122 , 123 , and 124 .

The parity bit generation unit 140 is configured to generate a parity bit (PB) in the first logic state when the count value is less than or equal to half of the total number of data, and to generate the parity bit (PB) in the second logic state when the count value is greater than half of the total number of data. For example, in the illustrated embodiment of FIG. 1 , when the count value is less than or equal to 2, a first logic state PB is generated, but when the count value is greater than 2, a second logic state PB is generated.

The data conversion unit 150 , in response to the PB provided by the parity bit control unit 110 , is configured to inversely output one of the MSBs D 0 < 1 >, D 1 < 1 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > of the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, or output the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > without a change. For example, when the PB is in the first logic state, the data conversion unit 150 will output the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, without a change. However, when the PB is in the second logic state, the data conversion unit 150 will inversely output one of the MSBs D 0 < 1 >, D 1 < 1 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > of the first through fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >.

The transmission units TX are configured to transmit data provided by the data conversion unit 150 using a multilevel signalling technique. One possible embodiment of the transmission units TX will be described in some additional detail with reference to FIGS. 3 and 4 .

FIG. 2A is a table listing the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > and the PB of FIG. 1 to be transmitted.

FIG. 2B is a table listing the first to fourth transmission data D 0 ′< 1 >, D 0 ′< 0 >, D 1 ′< 1 >, D 1 ′< 0 >, D 2 ′< 1 >, D 2 ′< 0 >, D 3 ′< 1 >, and D 3 ′< 0 > and the PB of FIG. 1 as actually transmitted. The operation of the semiconductor device 100 will be described with reference to FIGS. 1 , 2 A, and 2 B.

First, when the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > as in the first row of the table of FIG. 2A are to be transmitted, the MSB D 0 < 1 > of the first data D 0 < 1 > and D 0 < 0 > is in a logic high state H and the LSB D 0 < 0 > of the first data D 0 < 1 > and D 0 < 0 > is in a logic low state L, which are different logic states. Also, for the second data D 1 < 1 > and D 1 < 0 > and the third data D 2 < 1 > and D 2 < 0 >, the logic states of the MSBs D 1 < 1 > and D 2 < 1 > and the LSBs D 1 < 0 > and D 2 < 0 > are different. However, the logic states of the MSB D 3 < 1 > and the LSB D 3 < 0 > of the fourth data D 3 < 1 > and D 3 < 0 > are the same. That is, of the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, there are three data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are different, and one data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are the same. Thus, the parity bit control unit 110 generates and outputs a PB in the logic high state H because the number of data in which the MSBs and the LSBs are different is greater than 2 (i.e., more than half of the total number of data).

The first row of the table of FIG. 2B shows the first to fourth transmission data D 0 ′< 1 >, D 0 ′< 0 >, D 1 ′< 1 >, D 1 ′< 0 >, D 2 ′< 1 >, D 2 ′< 0 >, D 3 ′< 1 >, and D 3 ′< 0 > that are actually transmitted by converting the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the first row of the table of FIG. 2A . That is, when the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the first row of the table of FIG. 2A are to be transmitted, since the PB is in the logic high state H, the data conversion unit 150 outputs the first to fourth transmission data D 0 ′< 1 >, D 0 ′< 0 >, D 1 ′< 1 >, D 1 ′< 0 >, D 2 ′< 1 >, D 2 ′< 0 >, D 3 ′< 1 >, and D 3 ′< 0 > that are obtained by changing the logic states of the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > of the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, to the transmission units TX. Although, the embodiment of the inventive concept illustrated in FIG. 2B describes a case where changing the LSBs when the PB is in the logic high state H is performed, the present inventive concept is not limited to only this approach. Indeed, the same effect may be obtained in embodiments of the inventive concept that change the MSBs instead of the LSBs.

When the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the second row of the table of FIG. 2A are to be transmitted, since there are three data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are different, and one data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are the same, the parity bit control unit 110 generates and outputs a PB in the logic high state H. Also, when the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the third row of the table of FIG. 2A are to be transmitted, since there are four data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are different, of the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, the parity bit control unit 110 generates and outputs a PB in the logic high state H.

When the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the second or third row of the table of FIG. 2A are to be transmitted, since the PB is in the logic high state H, the data conversion unit 150 outputs the first to fourth transmission data D 0 ′< 1 >, D 0 ′< 0 >, D 1 ′< 1 >, D 1 ′< 0 >, D 2 ′< 1 >, D 2 ′< 0 >, D 3 ′< 1 >, and D 3 ′< 0 > that are obtained by changing the logic states of the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > of the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, to the transmission units TX.

When the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the fourth or fifth row of the table of FIG. 2A are to be transmitted, since there are two data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are different, and two data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are the same, the parity bit control unit 110 generates and outputs a PB in the logic low state L. Also, when the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the six row of the table of FIG. 2A are to be transmitted, since there are four data in which the MSBs D 0 < 1 >, D 1 < 0 >, D 2 < 1 >, and D 3 < 1 > and the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > are different, of the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, the parity bit control unit 110 generates and outputs a PB in the logic low state L.

When the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 > in the fourth, fifth, or sixth row of the table of FIG. 2A are to be transmitted, since the PB is in the logic low state L, the data conversion unit 150 outputs the first to fourth transmission data D 0 ′< 1 >, D 0 ′< 0 >, D 1 ′< 1 >, D 1 ′< 0 >, D 2 ′< 1 >, D 2 ′< 0 >, D 3 ′< 1 >, and D 3 ′< 0 > that have the same logic states as the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, without changing the logic states of the LSBs D 0 < 0 >, D 1 < 0 >, D 2 < 0 >, and D 3 < 0 > of the first to fourth data D 0 < 1 >, D 0 < 0 >, D 1 < 1 >, D 1 < 0 >, D 2 < 1 >, D 2 < 0 >, D 3 < 1 >, and D 3 < 0 >, to the transmission units TX.

FIG. 3 is a circuit diagram of a transmitter according to an embodiment of the present inventive concept. In the following description, for convenience of explanation, the transmission unit TX transmitting the first transmission data D 0 ′< 1 > and D 0 ′< 0 > is the transmitter TX of FIG. 3 . The transmission units TX transmitting the second to fourth transmission data D 1 ′< 1 >, D 1 ′< 0 >, D 2 ′< 1 >, D 2 ′< 0 >, D 3 ′< 1 >, and D 3 ′< 0 > may use the transmitter TX of FIG. 3 . However, it is not necessary that the transmission units TX of FIG. 1 must be the transmitter TX of FIG. 3 . A transmitter of a different type capable of transmitting data using a multilevel signal may be used therefor. Also, it is not necessary that the transmitter TX of FIG. 3 must be used for the semiconductor device 100 of FIG. 1 . The transmitter may be used for other semiconductor devices transmitting data.

Referring to FIGS. 1-3 , the transmitter TX may include a first voltage control unit 310 , a second voltage control unit 320 , a third voltage control unit 330 , a fourth voltage control unit 340 , a fifth voltage control unit 350 , and a sixth voltage control unit 360 .

The first voltage control unit 310 may disconnect a power voltage source VDDQ and an output terminal OUT of the transmitter TX when the MSB D 0 ′< 1 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > is in the first logic state. The second voltage control unit 320 may disconnect a ground voltage source VSS and the output terminal OUT of the transmitter TX when the MSB D 0 ′< 1 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > is in the second logic state. The third voltage control unit 330 may disconnect the power voltage source VDDQ and the output terminal OUT of the transmitter TX when the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are in the first logic state. The fourth voltage control unit 340 may disconnect the ground voltage source VSS and the output terminal OUT of the transmitter TX when the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are in the second logic state. The fifth voltage control unit 350 may disconnect the power voltage source VDDQ and the output terminal OUT of the transmitter TX when the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are in the second logic state. The sixth voltage control unit 360 may disconnect the ground voltage source VSS and the output terminal OUT of the transmitter TX when the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are in the first logic state.

The transmitter TX may further include an inverter INV, a NOR gate (NOR), and a NAND gate (NAND). The inverter INV may inversely output the MSB D 0 ′< 1 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 >. The NOR gate NOR may perform a NOR operation on the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 >. The NAND gate NAND may perform a NAND operation on the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 >.

The first voltage control unit 310 may include a first transistor TR 1 and a first resistor R 1 . An output signal of the inverter INV is applied to a gate of the first transistor TR 1 and the power voltage source VDDQ may be connected to a first end of the first transistor TR 1 . The first resistor R 1 may be connected between a second end of the first transistor TR 1 and the output terminal OUT of the transmitter TX.

The second voltage control unit 320 may include a second transistor TR 2 and a second resistor R 2 . The output signal of the inverter INV is applied to a gate of the second transistor TR 2 and the ground voltage source VSS may be connected to a first end of the second transistor TR 2 . The second resistor R 2 may be connected between a second end of the second transistor TR 2 and the output terminal OUT of the transmitter TX.

The third voltage control unit 330 may include a third transistor TR 3 and a third resistor R 3 . An output signal of the NOR gate NOR is applied to a gate of the third transistor TR 3 and the power voltage source VDDQ may be connected to a first end of the third transistor TR 3 . The third resistor R 3 may be connected between a second end of the third transistor TR 3 and the output terminal OUT of the transmitter TX.

The fourth voltage control unit 340 may include a fourth transistor TR 4 and a fourth resistor R 4 . The output signal of the NOR gate NOR is applied to a gate of the fourth transistor TR 4 and the ground voltage source VSS may be connected to a first end of the fourth transistor TR 4 . The fourth resistor R 4 may be connected between a second end of the fourth transistor TR 4 and the output terminal OUT of the transmitter TX.

The fifth voltage control unit 350 may include a fifth transistor TR 5 and a fifth resistor R 5 . An output signal of the NAND gate NAND is applied to a gate of the fifth transistor TR 5 and the power voltage source VDDQ may be connected to a first end of the fifth transistor TR 5 . The fifth resistor R 5 may be connected between a second end of the fifth transistor TR 5 and the output terminal OUT of the transmitter TX.

The sixth voltage control unit 360 may include a sixth transistor TR 6 and a sixth resistor R 6 . The output signal of the NAND gate NAND is applied to a gate of the sixth transistor TR 6 and the ground voltage source VSS may be connected to a first end of the sixth transistor TR 6 . The sixth resistor R 6 may be connected between a second end of the sixth transistor TR 6 and the output terminal OUT of the transmitter TX.

In the above description, the first transistor TR 1 , the third transistor TR 3 , and the fifth transistor TR 5 may be PMOS transistors and the second transistor TR 2 , the fourth transistor TR 4 , and the sixth transistor TR 6 may be NMOS transistors. Also, the first to sixth resistors R 1 -R 6 may have the same resistance.

FIG. 4 is a table showing the voltages Vout at the output terminal OUT of the transmitter TX of FIG. 3 according to the logic states of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > applied to the transmitter TX. The operation of the transmitter TX and the voltage Vout of the output terminal OUT of the transmitter TX according to the logic states of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > will be described below with reference to FIGS. 3 and 4 . In the following description, the first to sixth resistors R 1 -R 6 are assumed to have the same resistance.

When the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are all in the logic high state H, the output signal of the inverter INV is in the logic low state so that the first transistor TR 1 is turned on and the second transistor TR 2 is turned off. Since the output signals of the NOR gate NOR and the NAND gate NAND are all in the logic low state, the third and fifth transistors TR 3 and TR 5 are turned on and the fourth and sixth transistors TR 4 and TR 6 are turned off. Thus, the voltage Vout of the output terminal OUT of the transmitter TX has the same voltage level as that of the power voltage source VDDQ. Also, since all transistors connected to the ground voltage source VSS are turned off, current does not flow between the power voltage source VDDQ and the ground voltage source VSS.

Next, when the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are, respectively, in the logic high state H and the logic low state L, the output signal of the inverter INV is in the logic low state so that the first transistor TR 1 is turned on and the second transistor TR 2 is turned off. Since the output signals of the NOR gate NOR and the NAND gate NAND are, respectively, in the logic low state and the logic high state, the third and fourth transistors TR 3 and TR 4 are turned on and the fifth and sixth transistors TR 5 and TR 6 are turned off. Thus, the voltage level of the voltage Vout of the output terminal OUT of the transmitter TX is ⅔ of that of the power voltage source VDDQ. Also, since the fourth transistor TR 4 connected to the ground voltage source VSS is turned on, current flows between the power voltage source VDDQ and the ground voltage source VSS.

Next, when the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are, respectively, in the logic low state L and the logic high state H, the output signal of the inverter INV is in the logic high state so that the first transistor TR 1 is turned off and the second transistor TR 2 is turned on. Since the output signals of the NOR gate NOR and the NAND gate NAND are, respectively, in the logic low state and the logic high state, the third and fourth transistors TR 3 and TR 4 are turned on and the fifth and sixth transistors TR 5 and TR 6 are turned off. Thus, the voltage level of the voltage Vout of the output terminal OUT of the transmitter TX is ⅓ of that of the power voltage source VDDQ. Also, since the second and fourth transistors TR 2 and TR 4 connected to the ground voltage source VSS are turned on, current flows between the power voltage source VDDQ and the ground voltage source VSS.

When the MSB D 0 ′< 1 > and the LSB D 0 ′< 0 > of the first transmission data D 0 ′< 1 > and D 0 ′< 0 > are all in the logic low state L, the output signal of the inverter INV is in the logic high state so that the first transistor TR 1 is turned off and the second transistor TR 2 is turned on. Since the output signals of the NOR gate NOR and the NAND gate NAND are all in the logic high state, the third and fifth transistors TR 3 and TR 5 are turned off and the fourth and sixth transistors TR 4 and TR 6 are turned on. Thus, the voltage Vout of the output terminal OUT of the transmitter TX has the same voltage level as that of the ground voltage source VSS. Also, since all transistors connected to the power voltage source VDDQ are turned off, current does not flow between the power voltage source VDDQ and the ground voltage source VSS.

As described above, when the data is transmitted using a multilevel signal, even when the logic states of the MSB and the LSB of the data are different, current flows in the transmission unit TX. Thus, according to the illustrated embodiments of the inventive concept, by minimizing a case in which the logic states of the MSB and the LSB of the data are different, the amount of current consumed by a transmitter TX may be reduced, as compared with conventional data transmission approaches.

As noted above, the structure and operation of transmitter(s) TX incorporated within certain embodiments of the invention may vary from application to application. However, FIG. 3 illustrates one example wherein 2 bits of data are transmitted using one of four voltage levels. The transmitter TX generates a multilevel signal using the MSB and the LSB. When a different bit number of data bits is to be transmitted, portions connected to the power voltage source VDDQ and portions connected to the ground voltage source VSS are, respectively, turned ON/OFF so that a multilevel signal having a plurality of voltage levels may be generated.

To turn ON/OFF the portion connected to the power voltage source VDDQ and the portions connected to the ground voltage source VSS, two of the first and second bits are selected from the bits of the data and then controlled. For example, when 3 bits data D< 2 >, D< 1 >, and D< 0 > are transmitted using one of eight voltage levels, the first and second bits may be (D< 2 >, D< 1 >), (D< 2 >, D< 0 >), (D< 1 >, D< 0 >), (D< 1 >, D< 2 >), (D< 0 >, D< 2 >), or (D< 0 >, D< 1 >).

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.