Trigger signal detection apparatus

A description will be given in more detail of the trigger signal detection apparatus shown in FIG. 1 with reference to a specific circuit diagram. A circuit shown in FIG. 2 is one example of the input circuit IN 1 , the clock gating circuit CG 1 , the trigger signal processing circuit TG 1 , and the count circuit CT 1 in the trigger signal detection apparatus shown in FIG. 1 .

The input circuit IN 1 has an input terminal AIl to which an analog signal AS is applied and a digital filter DF 1 to convert the analog signal AS received from the input terminal AI 1 into a digital signal trig and output it.

The clock gating circuit CG 1 comprises an OR circuit OR 1 , a latch circuit LT 1 , and an AND circuit AN 1 . The trigger signal processing circuit TG 1 has an OR circuit OR 2 , an NAND circuit NAND 1 , and a flip-flop FF 1 . Additionally, the count circuit CT 1 has an AND circuit AN 2 and a 10-bit counter C 1 .

FIG. 3 shows a timing chart of signals in the circuits shown in FIG. 2 , specifically, the reset signal RST_X, the system clock signal “sysclk”, the trigger signal “trig”, the enable signal “enable”, the internal clock signal “clkin”, the signal output, the 10-bit count value [9:0], and the one-shot pulse “AA”.

Next, a description will be given of operations of the circuits shown in FIG. 2 .

First, the low level reset signal RST_X is inputted from the input terminal RS 1 to the flip-flop FF 1 and, via the AND circuit AN 2 , to the 10-bit counter C 1 also. When supplied with the low level reset signal RST_X, the flip-flop FF 1 is reset. The 10-bit counter C 1 is also reset as it is supplied with the low level reset signal RST_X. Then, the reset signal RST_X turns high in level, thereby the trigger signal detection apparatus is activated.

Next, the trigger signal “trig” is inputted via the OR circuit OR 1 to the latch circuit LT 1 and, via the AND circuit AN 2 , to the 10-bit counter C 1 and further, via the NAND circuit NAND 1 , also to the flip-flop FF 1 as a signal “outd”.

Since the trigger signal “trig” is inputted to the 1-bit counter C 1 , during a period in which the trigger signal “trig” remains high in level, the 10-bit counter C 1 stays in the reset state continuously, thus abstaining from starting the counting of the internal clock signal “clkin”.

On the other hand, the latch circuit LT 1 detects the high level of the trigger signal “trig” at a trailing edge of the system clock signal “sysclk”, generates the high level enable signal “enable” and outputs it to the AND circuit AN 1 . When supplied with the high level enable signal “enable” and the system clock signal “sysclk”, the AND circuit AN 1 generates the internal clock signal “clkin” and outputs it to the 10-bit counter C 1 and the flip-flop FF 1 .

The flip-flop FF 1 latches the signal “outd” received from the NAND circuit NAND 1 at a leading edge of the internal clock signal “clkin” applied from the AND circuit AN 1 and then outputs it as the high level signal output to the OR circuits OR 1 and OR 2 and the output terminal OUT 1 .

It is to be noted that when the trigger signal “trig” is changed from the high level to the low level, the AND circuit AN 2 provides a high level output, whose negative logic level is in turn input to the 10-bit counter C 1 , thereby releasing the 10-bit counter C 1 from the reset state.

On the other hand, since the OR circuit OR 1 is supplied with the output signal “output”, the output signal “output” remains at the high level, so the AND circuit AN 1 still continues to output the internal clock signal “clkin”. Therefore, after released from the reset state, the 10-bit counter C 1 starts counting the internal clock signal “clkin” with the internal clock signal “clkin”, and outputs count values “count” of its 0'th bit to 9'th bit to the time set-up circuit TS 1 . When the count value “count” inputted to the time set-up circuit TS 1 reaches a predetermined value (“250” in the present example), the time set-up circuit TS 1 generates the one-shot pulse “AA” and outputs the one-shot pulse “AA” to the OR circuit OR 2 and the output terminal OUT 2 .

As the one-shot pulse “AA” is inputted to the OR circuit OR 2 , the level of the signal “outd” being provided from the

NAND circuit NAND 1 is inverted from the high level to the low level. When supplied with the low level signal “outd”, the flip-flop FF 1 latches the low level of the signal “outd” at the leading edge of the internal clock signal “clkin” and outputs the low level signal output to the OR circuits OR 1 and OR 2 and the output terminal OUT 1 .

In such a manner, the trigger signal detection apparatus according to the present example provides the high level signal output when supplied with the high level trigger signal “trig” and continues to do so until the arbitrarily set-up time elapses even after the level of the trigger signal “trig” is changed from the high level to the low level.

When the level of the signal output is changed to the low level after this set-up time has elapsed, the output of the OR circuit OR 1 is also changed to the low level, so the enable signal “enable” is also changed to the low level as latched by the latch circuit LT 1 at the trailing edge of the system clock signal “sysclk”. As the result, the internal clock signal “clkin” is blocked by the AND circuit AN 1 , and also blocked the output to the 10-bit counter C 1 .

It is to be noted that when the high level trigger signal “trig” is inputted again from the input circuit IN 1 before the one-shot pulse “AA” is outputted from the time set-up circuit TS 1 before the count value “count” has reached the predetermined value (250 in the present example), the trigger signal “trig” is inputted via the AND circuit AN 2 to the 10-bit counter C 1 , and the 10-bit counter C 1 is rest. The 10-bit counter C 1 abstains from starting count up although the 10-bit counter C 1 is supplied with the high level internal clock signal “clkin” from the latch circuit LT 1 . Then, when the level of the trigger signal “trig” is changed from the high level to the low level, the 10-bit counter C 1 restarts count up and outputs the count value “count” to the time set-up circuit TS 1 . This series of operations will be repeated when the high level trigger signal “trig” is inputted again from the input circuit IN 1 to the 10-bit counter C 1 before the count value “count” reaches the predetermined value (250 in the present example). That is, when the count value “count” reaches the predetermined value (250 in the present example), the level of the signal “output” provided from the flip-flop FF 1 is changed to the low level, and the one-shot pulse “AA” is outputted from the time set-up circuit TS 1 . FIG. 4 shows a timing chart of the trigger signal “trig”, the 10-bit count value [9:0], the signal “output”, and the one-shot pulse “AA” in these cases.

In such a manner, according to the present example 1, the internal clock signal “clkin” is inputted to the trigger signal processing circuit TG 1 and the count circuit CT 1 , so the operating time of the trigger signal processing circuit TG 1 , the count circuit CT 1 , and the time set-up circuit TS 1 will be limited to the time within which the enable signal “enable” is high in level. More specifically, the trigger signal processing circuit TG 1 , the count circuit CT 1 , and the time set-up circuit TS 1 will operate only in a limited period from the point of time when the trigger signal “trig” is detected by the latch circuit LT 1 as the input signal, and changes the level of the output signal “output” of the flip-flop FF 1 to the high level, up to when the one-shot pulse “AA” is outputted from the time set-up circuit TS 1 . Thus, the dissipation power is reduced. The count circuit CT 1 and the time set-up circuit TS 1 tend to increase in circuit scale as the time set up by the time set-up circuit TS 1 becomes longer, thus the dissipation power reducing effects are further increasing.

Moreover, the enable signal “enable” required in control of the gating of the internal clock signal “clkin” to the trigger signal processing circuit TG 1 and the count circuit CT 1 is generated inside the trigger signal detection apparatus, so the enable signal “enable” is not need to be taken in from the other outside apparatus. This eliminates the necessity of mounting an enable signal generation circuit outside the apparatus, thus enabling a decrease in the circuit scale just by that much.

(2) Second Embodiment

In the aforesaid first embodiment, the counter C 1 starts count up when a change in level of the trigger signal “trig”, for example, from the high level to the low level, is detected (hereinafter, referred to as “level detection system”). However, there is another desired case of starting the count up by the counter C 1 when an edge, for example, a leading edge of the trigger signal “trig” is detected (hereinafter referred to as “edge detection system”). A description will be given below of an embodiment that can accommodate both of the level detection system and the edge detection system.

FIG. 5 is a block diagram showing an outlined constitution of a trigger signal detection apparatus according to a second embodiment of the present invention. As may be clear from comparison to FIG. 1 , the trigger signal detection apparatus shown in FIG. 5 includes a count circuit CT 11 instead of the count circuit CT 1 shown in FIG. 1 , an input terminal SEL and an edge detection/level detection switchover circuit ELS 11 that switches between the level detection system and the edge detection system at the time of starting count up by the count circuit CT 11 . A counter reset signal rst_x is supplied to the count circuit CT 11 . A select signal sel is supplied to the input terminal SEL.

On the other hand, the trigger signal detection apparatus shown in FIG. 5 has only the output terminal OUT 1 , not the output terminal OUT 2 , as its output terminals. Thus, the one-shot pulse “AA” generated by the time set-up circuit TS 1 is outputted to only the trigger signal processing circuit TG 1 . The other components of the trigger signal detection apparatus shown in FIG. 5 are essentially the same as those of the trigger signal detection apparatus shown in FIG. 1 . Therefore, in the following, a description will be given of the trigger signal detection apparatus of the present embodiment mainly about the operations of the edge detection/level detection switchover circuit ELS 11 .

First, when the high level select signal sel is inputted from the input terminal SEL, the level detection system is selected. The edge detection/level detection switchover circuit ELS 11 supplies the count circuit CT 11 with the reset signal RST_X received from the input terminal RS 1 . In this case, the trigger signal detection apparatus of the present embodiment operates essentially in the same way as the aforesaid trigger signal detection apparatus of the first embodiment, and repetitive description on their operations will not be repeated.

On the other hand, when the low level select signal sel is inputted from the input terminal SEL, the edge detection system is selected.

First, the reset signal RST_X inputted from the input terminal RS 1 is applied to the trigger signal processing circuit TG 1 and also to the count circuit CT 11 via the edge detection/level detection switchover circuit ELS 11 . Thus, the trigger signal processing circuit TG 1 and the count circuit CT 11 are reset to their initial states.

When the high level trigger signal “trig” is inputted from the input circuit IN 1 and applied to the clock gating circuit CG 1 , the clock gating circuit CG 1 detects the high level of the trigger signal “trig” and outputs the internal clock signal “cikin” to the trigger signal processing circuit TG 1 , the count circuit CT 11 , and the edge detection/level detection switchover circuit ELS 11 .

When the trigger signal “trig” is inputted to the trigger signal processing circuit TG 1 , the trigger signal processing circuit TG 1 detects the leading edge of the trigger signal “trig” in synchronization with the internal clock signal “clkin” and provides the signal output to the trigger signal processing circuit TG 1 , the clock gating circuit CG 1 , and the output terminal OUT 1 . In the present embodiment, the signal output corresponds to, for example, the first signal.

When the edge detection/level detection switchover circuit ELS 11 receives the high level trigger signal “trig” from the input circuit IN 1 and receives the internal clock “cikin” from the clock gating circuit CG 1 , the edge detection/level detection switchover circuit ELS 11 supplies the count circuit CT 11 with the counter reset signal rst_x which corresponds to half a pulse of the internal clock signal “cikin”, by synchronizing the high level trigger signal “trig” with the internal clock “clkin”. Thus, the count circuit CT 11 is reset in a synchronous manner, starts count up and outputs the count value “count” to the time set-up circuit TS 1 . In the present embodiment, the counter reset signal rst_x corresponds to, for example, a third signal. The time set-up circuit TS 1 generates the one-shot pulse “AA” when the received count value “count” has become equal to a preset value (count value), and outputs this pulse to the trigger signal processing circuit TG 1 . The one-shot pulse “AA” corresponds to, for example, the second signal in the present embodiment.

When the one-shot pulse “AA” is supplied to the trigger signal processing circuit TG 1 , the trigger signal processing circuit TG 1 provides the low level signal output to the trigger signal processing circuit TG 1 , the clock gating circuit CG 1 , and the output terminal OUT 1 . When the low level signal output is supplied to the clock gating circuit CG 1 , the clock gating circuit CG 1 stops outputting the internal clock signal “clkin”. Thus, the output of the internal clock signal “clkin” is stopped to the count circuit CT 11 , the trigger signal processing circuit TG 1 , and the edge detection/level detection switchover circuit ELS 11 .

In such a manner, according to the present embodiment, by outputting the internal clock signal “clkin” to the trigger signal processing circuit TG 1 , the edge detection/level detection switchover circuit LES 11 , and the count circuit CT 11 only in a necessary case, it is possible to operate those circuits only in a necessary time. Therefore, dissipation power of the trigger signal detection apparatus can be reduced. The effects of reducing the dissipation power will increase as the set-up time increases.

Furthermore, in gating of clock signal outputs to the count circuit CT 11 , control is conducted in such a manner that the clock signal outputs may start when the clock gating circuit CG 1 has detected an input of the trigger signal “trig”. Thus, there is no need to input the clock enable signal from outside of the apparatus. This eliminates the necessity of adding a circuit for, for example, generating the enable signal. Accordingly, an increase in scale of the apparatus can be prevented.

A description will be given in more detail of the trigger signal detection apparatus shown in FIG. 5 with reference to a specific circuit diagram. A circuit shown in FIG. 6 is one example of the input circuit IN 1 , the clock gating circuit CG 1 , the count circuit CT 11 , the trigger signal processing circuit TG 1 , and the edge detection/level detection switchover circuit ELS 11 in the trigger signal detection apparatus shown in FIG. 5 take shapes.

Of these circuits shown in FIG. 6 , the input circuit IN 1 , the clock gating circuit CG 1 , and the trigger signal processing circuit TG 1 have the same specific constitutions as those of the circuits shown in FIG. 2 . The count circuit CT 11 is different from the count circuit CT 1 of FIG. 2 in that the count circuit CT 11 includes a 10-bit counter C 11 having an rst_x input terminal to which the counter reset signal rst_x is to be inputted, instead of the 10-bit counter C 1 shown in FIG. 2 .

The edge detection/level detection switchover circuit ELS 11 has an AND circuits AN 12 and AN 13 , flip-flop circuits FF 12 and FF 13 , and an NAND circuit NAND 12 .

FIG. 7 shows a timing chart of the signals in the circuits shown in FIG. 6 , specifically, the reset signal RST_X, the system clock signal “sysclk”, the trigger signal “trig”, the enable signal “enable”, the internal clock signal “clkin”, the signal output, the counter reset signal rst_x, the 10-bit count value [9:0], and the one-shot pulse “AA”.

Next, a description will be given of operations of the trigger signal detection apparatus shown in FIG. 6 .

The description is based on the assumption that the trigger signal “trig” should be high in level for a time that is not less than one clock pulse of the system clock signal “sysclk” and not longer than a time preset in the time set-up circuit TS 1 .

First, the low level reset signal RST_X is inputted to the flip-flop FF 1 and is also inputted, via the AND circuit AN 2 , to the 10-bit counter C 11 . Thus, the flip-flop circuit FF 1 and the 10-bit counter C 11 are reset. Then, the reset signal RST_X turns high in level, thereby the trigger signal detection apparatus is activated.

When the high level select signal sel is applied from the input terminal SEL, the level detection system is selected. The trigger signal detection apparatus of the present example operates in the same way as that of Example 1 described above.

When the low level select signal sel is applied from the input terminal SEL, the edge detection system is selected. When the level of the reset signal RST_X supplied from the input terminal RS 1 turns high after the negative logic level of the select signal sel is inputted to the AND circuit AN 13 , the high level signal is inputted to the flip-flops FF 12 and FF 13 . Thus, those flip-flops are reset.

The trigger signal “trig” is inputted via the OR circuit OR 1 to the latch circuit LT 1 and inputted, via the NAND circuit NAND 1 , to the flip-flop FF 1 as the signal “outd” and also inputted to the flip-flop FF 12 and further to the AND circuit AN 12 . The latch circuit LT 1 detects the high level of the trigger signal “trig” at a trailing edge of the system clock signal “sysclk” and then outputs the enable signal “enable” to the AND circuit AN 1 . Thus, the internal clock signal “clkin” is outputted from the AND circuit AN 1 to the flip-flop FF 1 in the trigger signal processing circuit TG 1 , the flip-flops FF 12 and FF 13 in the edge detection/level detection switchover circuit ELS 11 , and the 10-bit counter C 11 .

Furthermore, when the flip-flop FF 1 is supplied with the internal clock signal “clkin” from the AND circuit AN 1 , the flip-flop FF 1 latches the signal “outd” at the leading edge of the internal clock signal “clkin” and then outputs the latched signal as the output signal “output” to the OR circuits OR 1 and OR 2 and the output terminal OUT 1 .

On the other hand, the flip-flop FF 12 latches the trigger signal “trig” at the leading edge of the first pulse of the internal clock signal “clkin”, and the low level counter reset signal rst_x is then outputted to the 10-bit counter C 11 via the flip-flop FF 13 and the NAND circuit 12 by as much as half a pulse of the internal clock signal “clkin”. The 10-bit counter C 11 is synchronously reset at the trailing edge of the counter reset signal rst_x, and starts count up from 0. In such a manner, when the edge detection system is selected in the present example, in contrast to Example 1, no time lag occurs from the point of time when the AND circuit AN 1 is supplied with the enable signal “enable” and the internal clock signal “clkin” is outputted from the AND circuit AN 1 , to the point of time when the counter starts count up.

The 10-bit counter C 11 supplies the time set-up circuit TS 1 with the count value “count” of its 0'th bit to 9'th bit until this count value “count” reaches a predetermined value (“250” in the present example), whereupon the time set-up circuit TS 1 outputs the one-shot pulse “AA” to the OR circuit OR 2 . Thus, the signal “outd” provided from the AND circuit AN 2 is inverted from the high level to the low level. In the result, the low level of the signal “outd” is latched by the flip-flop FF 1 at the leading edge of the internal clock signal “clkin”. Thus, the low level signal output is outputted from the flip-flop FF 1 to the OR circuits OR 1 and OR 2 and the output terminal OUT 1 .

In such a manner, the trigger signal detection apparatus according to the present example provides the high level signal output when supplied with the high level trigger signal “trig” and continues to do so until the arbitrarily set-up time elapses even after the level of the trigger signal “trig” is changed from the high level to the low level. When the level of the signal output is changed to the low level, the output of the OR circuit OR 1 is also changed to the low level. Thus, the enable signal “enable” is also changed to the low level as it is latched at the trailing edge of the system clock signal “sysclk”. In the result, the internal clock signal “clkin” is blocked by the AND circuit AN 1 , and the output to the 10-bit counter C 11 is stopped.

It is to be noted that if the trigger signal “trig” is inputted again from the digital filter DF 1 before the count value “count” has reached the predetermined value (250 in the present example) and the one-shot pulse “AA” is outputted from the time set-up circuit TS 1 , the high level enable signal “enable” is generated by the latch circuit LT 1 and the counter C 11 is supplied with the low level counter reset signal rst_x from the NAND circuit 12 , and thus the count value “count” is cleared, which operation is immediately followed by the 10-bit counter C 11 restarting count up. These operations are repeated when the trigger signal “trig” is inputted again before the count value “count” reaches the predetermined value (250 in the present example). When the count value “count” reaches the predetermined value (250 in the present example), the one-shot pulse “AA” is outputted from the time set-up circuit TS 1 , thus the level of the signal output to the low level is changed. FIG. 8 shows a timing chart of the reset signal RST_X, the trigger signal “trig”, the 10-bit count value [9:0], the signal output, and the one-shot pulse “AA” in these cases.

In such a manner, according to the present example 2, the internal clock signal “clkin” is inputted to the trigger signal processing circuit TG 1 , the edge detection/level detection switchover circuit ELS 11 , and the count circuit CT 11 , the operation time of the trigger signal processing circuit TG 1 , the count circuit CT 11 , the time set-up circuit TS 1 , and the edge detection/level detection switchover circuit ELS 11 is limited to a time period within which the enable signal “enable” is high in level. More specifically, the trigger signal processing circuit TG 1 , the count circuit CT 11 , the time set-up circuit TS 1 , and the edge detection/level detection switchover circuit ELS 11 will operate only in a limited period from the point of time when the incoming trigger signal “trig” is detected by the latch circuit LT 1 and the level of the output signal “output” of the flip-flop FF 1 is changed to the high level, up to the point of time when the one-shot pulse “AA” is outputted from the time set-up circuit TS 1 . Thus, the dissipation power is reduced. Since the count circuit CT 11 and the time set-up circuit TS 1 tend to increase in circuit scale as the time set up by the time set-up circuit TS 1 becomes longer, the dissipation power reducing effects according to the present example is further increased.

Moreover, the enable signal “enable” required in control of the gating of the internal clock signal “clkin” to the trigger signal processing circuit TG 1 and the count circuit CT 11 is generated inside the trigger signal detection apparatus and thus need not be taken in from the outside of the apparatus. This eliminates the necessity of mounting an enable signal generation circuit outside the apparatus. Accordingly, a decrease in the circuit scale is accomplished by just that much.

Although the present invention has been described with reference to its embodiments, it is to be understood that the present invention is not limited to these embodiments whatsoever and, of course, various modification can be implemented within the scope thereof.

For example, although the above embodiments have been arranged to generate and output the one-shot pulse “AA” when the count value “count” has reached the predetermined value in the time set-up circuits TS 1 , the present invention is not limited to it; the high level signal may be generated instead.

Example 2 has been arranged to apply the counter reset signal rst_x corresponding to half a pulse of the internal clock signal “clkin” to the rst_x input terminal of the count circuit CT 11 , the present invention is not limited to it; the counter reset signal may be outputted by as much as one pulse of the internal clock signal “clkin”. In this case, the internal clock signal “clkin” may be inputted to the flip-flop FF 13 as it is, not in a condition where it is inverted.