Temperature independent reference current generator using positive and negative temperature coefficient currents

The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0132840 (filed on Dec. 24, 2008) which is hereby incorporated by reference in its entirety.

Embodiments relate to an electronic circuit and methods thereof. Some embodiments relate to a temperature independent type reference current generating device.

A reference current generator and/or a reference current source may supply a reference current that may not be influenced by power and/or temperature. A generated reference current may be radiated and/or supplied to a bias voltage of each circuit. Example FIG. 1 and FIG. 2 are diagrams illustrating circuits of a current source. Referring to FIG. 1 , a current source may generate reference current I REF1 using base/emitter voltage V BE and resistance R 1 . A current source may generate a current, for example I 1 =V BE1 /R 1 , with substantially no influence of supplied power V DD . However, V BE1 may be influenced by temperature and thus a value of reference current I REF1 generated from a current may vary according temperature.

Referring to FIG. 2 , a current source may use a reference voltage with substantially no influence of temperature. A current source may generate reference current I REF2 ([V bg −V BE1 ]/R′) using reference voltage V bg , bipolar transistor Q′ and resistance R′. However, V BE1 may be influenced by temperature, and thus a temperature compensation part 5 may be provided to compensate for an influenced value. A current source may generate reference current I REF2 with no influence of power and/or temperature. However, a reference voltage source circuit generating reference voltage V bg may be additionally provided in a current source to generate reference current I REF2 . Therefore, a current source may be influenced by a temperature change and/or may require a reference voltage source circuit to generate a reference voltage.

Accordingly, there is a need of a temperature independent type reference current generating device, and a method of manufacturing a temperature independent type reference current generating device, which may be able to generate a reference current substantially without influence of a temperature and/or a supply voltage, substantially independent from a reference voltage.

Embodiments relate to a temperature independent type reference current generating device, and a method of manufacturing a temperature independent type reference current generating device. According to embodiments, a temperature independent type reference current generating device may be provided. In embodiments, a temperature independent type reference current generating device may be able to generate a reference current substantially without influence of a temperature and/or a supply voltage, substantially independent from a reference voltage.

According to embodiments, a temperature independent type reference current generating device may include a first reference current generator generating a first reference current having a first element using a first bipolar transistor and/or a first load. In embodiments, a temperature independent type reference current generating device may include a first element decreasing according to a temperature. In embodiments, a temperature independent type reference current generating device may include a second reference current generator generating a second reference current having a second element increasing according to a temperature, which may mirror and/or output a second reference current.

According to embodiments, a temperature independent type reference current generating device may include a first current mirror mirroring a first reference current and/or outputting a mirrored first reference current. In embodiments, a temperature independent type reference current generating device may include a second current mirror adding a mirrored first reference current and a mirrored second reference current, and/or mirroring a result of an addition to output a mirrored result as an output reference current.

According to embodiments, a reference current may be generated using a bipolar transistor and/or a load. In embodiments, a reference current may be generated, substantially without influence of changes of temperature and/or supply power, and/or substantially independent from a reference voltage.

Example FIG. 3 is a circuit view illustrating a temperature independent type reference current generating device in accordance with embodiments.

Embodiments relate to a temperature independent type reference current generating device and methods thereof. Referring to example FIG. 3 , a circuit illustrates a temperature independent type reference current generating device in accordance with embodiments. According to embodiments, a reference current generating device may include first reference current generator 10 and/or second reference current generator 20 . In embodiments, a reference current generating device may include first current mirror 30 and/or second current mirror 40 .

According to embodiments, first reference current generator 10 may generate first reference current I 1 using first bipolar transistor Q 1 and/or a first load. In embodiments, first reference current I 1 may include a first element that may be variable according to temperature. In embodiments, first reference current generator 10 may include first to fourth PMOS transistors MP 1 , MP 2 , MP 3 and/or MP 4 , respectively. In embodiments, first reference current generator 10 may include first to fourth NMOS transistors MN 1 , MN 2 , MN 3 and/or MN 4 , respectively. In embodiments, first bipolar transistor Q 1 and resistance R 1 may be employed as a first load.

According to embodiments, first PMOS transistor MP 1 may have a source connected to supply voltage V DD . In embodiments, second PMOS transistor MP 2 may have a source connected to supply voltage V DD , and/or a gate/drain connected to a gate of first PMOS transistor MP 1 . In embodiments, third PMOS transistor MP 3 may have a source connected to a drain of first PMOS transistor MP 1 . In embodiments, fourth PMOS transistor MP 4 may have a source connected to a drain of second PMOS transistor MP 2 and a gate/drain connected to each other.

According to embodiments, first NMOS transistor MN 1 may have a source/gate connected to a drain of third PMOS transistor MP 3 . In embodiments, second NMOS transistor MN 2 may have a source connected to a drain of fourth PMOS transistor MP 4 and/or a gate connected to a gate of first NMOS transistor MN 1 . In embodiments, third NMOS transistor MN 3 may have a source/gate connected to a drain of first NMOS transistor MN 1 . In embodiments, fourth NMOS transistor MN 4 may have a source connected to a drain of second NMOS transistor MN 2 and/or a gate connected to a gate of third NMOS transistor MN 3 .

According to embodiments, first bipolar transistor Q 1 may have a base/collector connected to a drain of third NMOS transistor MN 3 and/or an emitter connected to a ground. In embodiments, resistance R 1 which may be a first load may be connected between a drain of fourth NMOS transistor MN 4 and a ground, and/or first reference current I 1 may flow along resistance R 1 . In embodiments, first reference current generator 10 may include the above-described configuration. In embodiments, first reference current I 1 may be generated as illustrated by Equation 1. In embodiments, V BE1 may be a first element decreasing according to temperature as base/emitter voltage of first bipolar transistor Q 1 .

According to embodiments, second reference current generator 20 may generate second reference current I 2 having a second element increasing according to temperature, which may mirror second reference current I 2 to output mirrored second reference current I 2 ′. In embodiments, the term mirror may reference a current which may be radiated in a current mirror. In embodiments, second reference current generator 20 may include fifth PMOS transistor MP 9 , sixth PMOS transistor MP 11 , second bipolar transistor Q 2 and/or resistance R 2 corresponding to a second load.

According to embodiments, fifth PMOS transistor MP 9 may have a source connected to the supply voltage V DD . In embodiments, second bipolar transistor Q 2 may have a collector connected to a gate/drain of fifth PMOS transistor MP 9 and/or a base connected to a base of first bipolar transistor Q 1 . In embodiments, resistance R 2 which may be a second load may be connected between an emitter of second bipolar transistor Q 2 and a ground. In embodiments, sixth PMOS transistor MP 11 may have a source connected to supply voltage V DD , a gate connected to a gate/drain of fifth PMOS transistor MP 9 and/or a drain connected to second current mirror 40 . In embodiments, second reference current generator 20 may have the above-described configuration, and/or second reference current I 2 may be generated as illustrated by Equation 2.

According to embodiments, V BE2 may be a base/emitter voltage of second bipolar transistor Q 2 and/or second reference current I 2 ′ mirrored by a drain of sixth PMOS transistor MP 11 . In embodiments, mirrored second reference current I 2 ′ may be a proportional to absolute temperature (PTAT) current. In embodiments, a second element increasing according to temperature in second reference current I 2 may be V BE1 −V BE2 .

According to embodiments, first current mirror 30 may mirror first reference current I 1 and/or output mirrored first reference current I 1 ′ to second current mirror 40 . In embodiments, first current mirror 30 may include seventh PMOS transistor MP 10 and/or eighth PMOS transistor MP 12 . In embodiments, seventh PMOS transistor MP 10 may have a gate connected to a drain of second PMOS transistor MP 2 and/or a source connected to supply voltage V DD . In embodiments, eighth PMOS transistor MP 12 may have a source connected to a drain of seventh PMOS MP 10 , a gate connected to a drain of fourth PMOS transistor MP 4 and/or a drain connected to second current mirror 40 . In embodiments, mirror first reference current I 1 ′ may flow via a drain of eighth PMOS transistor MP 12 .

According to embodiments, second current mirror 40 may add mirrored first reference current I 1 ′ and mirrored second reference current I 2 ′, and/or mirror a result of addition to generate output reference current I REF . In embodiments, second current mirror 40 may include fifth NMOS transistor MN 7 and/or sixth NMOS transistor MN 8 . In embodiments, fifth NMOS transistor MN 7 may have a source/gate connected to a result of addition of mirrored first reference current I 1 ′ and mirrored second reference current I′ 2 , and/or a drain connected to a ground. In embodiments, sixth NMOS transistor MN 8 may have a gate connected to a gate of fifth NMOS transistor MN 7 , a source having an output reference current I REF flowing therein and/or a drain connected to a ground. In embodiments, an output reference current flowing via sixth NMOS transistor MN 8 may be generated as illustrated by Equation.

According to embodiments, Equation 3 may be presentable in Equation 4.

According to embodiments, I REF may include I PTAT presentable in Equation 5.

According to embodiments, as illustrated in Equation 4, a level of second element V BE1 −V BE2 may be adjustable by R 2 /R 1 to offset second element V BE1 −V BE2 of mirrored second reference current I 2 ′ and/or first element V BE1 of mirrored first reference current I 1 ′. In embodiments, a value of second load R 2 may be adjusted to offset the first element and/or the second element to each other. In embodiments, in contrast to a reference current generating device illustrated in FIG. 2 , a temperature independent type reference current generating device in accordance with embodiments may generate reference current I REF substantially independent from reference voltage V bg . In embodiments, in contrast to a reference current generating device illustrated in FIG. 1 , embodiments may offset second element V BE1 −V BE2 of current I PTAT generated using second reference current generator 20 and first element V BE1 of first reference current I 1 generated using both first bipolar transistor Q 1 and resistance R 1 each other, which may compensate for an influence of temperature applied to V BE1 .

It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.