USPatent applicationPatented

Image processing device and deinterlacing method thereof

Granted 24 Jul 2012 · 1 office action

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Abstract

An image processing device and a deinterlacing process thereof are provided. The deinterlacing process reads a memory to retrieve ten pixels of an image field that are temporarily stored in the memory, wherein the ten pixels are located on a first column, a second column, a third column, a fourth column and a fifth column of a first row and a second row of the image filed. Then, the deinterlacing process estimates the data of an interpolated pixel according to the data of the ten pixels. The interpolated pixel is inserted between the first and second rows of the image field on the third column to form a deinterlaced image frame.

Description

6 parts
›CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 98126332, filed on Aug. 5, 2009, the entirety of which is incorporated by reference herein.

›BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a deinterlacing process of an image processing fields, and more particularly, a deinterlacing process of an image processing field that converts a video from fields to frames.

2. Description of the Related Art

Interlacing is a technique for improving video quality without consuming extra data bandwidth. An interlacing process divides an image frame into two fields: an image field consisting of even lines of the image frame; and an image field consisting of odd lines of the image frame. The two image fields are conveyed in the system at different time. Thus, an image system with low-bandwidth can cope with the high quality image.

However, some image display systems do not support interlaced videos. For example, LCD panels, plasma TVs and so on mostly only support progressive videos and displays images frame by frame. Thus, deinterlacing techniques are called for to convert an interlaced video to a progressive video.

›BRIEF SUMMARY OF THE INVENTION

The invention discloses image processing devices and deinterlacing methods thereof.

An exemplary embodiment of the image processing device comprises a memory, a data bus, a line buffer and a deinterlacing module. The memory in which an image field is temporarily stored is coupled to the data bus and the line buffer. The data bus and the line buffer are used in conveying and buffering data of ten pixels of the image field. The ten pixels are located on a first column, a second column, a third column, a fourth column and a fifth column of a first row and a second row of the image field. The deinterlacing module, coupled to the line buffer, estimates data for an interpolated pixel according to the data of the ten pixels. To form an image frame, the interpolcated pixel is inserted between the first and the second rows of the image field on the third column.

The invention further discloses a deinterlacing method. An exemplary embodiment of the deinterlacing method comprises: reading a memory to obtain data of ten pixels of an image field, wherein the ten pixels are located on a first column, a second column, a third column, a fourth column and a fifth column of a first row and a second row of the image field; and estimating data of an interpolated pixel according to the data of the ten pixels to form a deinterlaced image frame, wherein the interpolated pixel is inserted between the first and second rows of the image field on the third column.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

›BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 depicts an exemplary embodiment of image processing device in accordance with the invention;

FIG. 2 shows ten pixels of an image field;

FIG. 3 shows a flowchart depicting the data estimation for the interpolated pixel V(x, y) in accordance with the invention;

FIG. 4 depicts an example showing benefits from the deinterlacing process of the invention;

FIG. 5 shows other information which may be considered in the deinterlacing process;

FIG. 6 is a flowchart depicting another deinterlacing process in accordance with the invention; and

FIG. 7 shows other information which may be considered in the deinterlacing process.

›DETAILED DESCRIPTION OF THE INVENTION · 1 of 2

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 depicts an exemplary embodiment of image processing device in accordance with the invention. As shown, the image processing device comprises a memory 102 , a data bus 104 at least one line buffer 106 and a deinterlacing module 108 . An image field is temporarily stored in the memory 102 . The data bus 104 and the line buffer 106 are coupled to the memory 102 to convey and buffer data of ten pixels of the image field. The ten pixels are located on a first column, a second column, a third column, a fourth column and a fifth column of a first row and a second row of the image field. As the embodiment shows, a DMA (direct memory access) technique may be applied to access the memory 102 . The deinterlacing module 108 is coupled to the line buffer 106 and, based on the data of the ten pixels, the deinterlacing module 108 estimates data of an interpolated pixel. To convert the image field to an image frame, the interpolated pixel is inserted between the first and second rows of the image field on the third column.

FIG. 2 shows ten pixels of an image field. The ten pixels are located on a first column (X=x−2), a second column (X=x−1), a third column (X=x), a fourth column (X=x+1) and a fifth column (X=x+2) of a first row (Y=y−1) and a second row (Y=y+1) of the image field, where x and y are integers. As shown, the pixels on the first, second, third, fourth and fifth columns of the first row are labeled V(x−2, y−1), V(x−1, y−1), V(x, y−1), V(x+1, y−1) and V(x+2, y−1), and the pixels on the first, second, third, fourth and fifth columns of the second row are labeled V(x−2, y+1), V(x−1, y+1), V(x, y+1), V(x+1, y+1) and V(x+2, y+1). V(x, y) shows the interpolated pixel and is inserted between the first and the second rows of the image field at the third column.

In FIG. 2 , a label d 11 represents a data difference between pixels V(x−2, y−1) and V(x, y+1), a label d 12 represents a data difference between pixels V(x−1, y−1) and V(x+1, y+1), a label d 13 represents a data difference between pixels V(x, y−1) and V(x+2, y+1), a label d 21 represents a data difference between pixels V(x−1, y−1) and V(x−1, y+1), a label d 22 represents a data difference between pixels V(x, y−1) and V(x, y+1), a label d 23 represents a data difference between pixels V(x+1, y−1) and V(x+1, y+1), a label d 31 represents a data difference between pixels V(x, y−1) and V(x−2, y+1), a label d 32 represents a data difference between pixels V(x+1, y−1) and V(x−1, y+1), and a label d 33 represents a data difference between pixels V(x+2, y−1) and V(x, y+1). The deinterlacing technique of the invention estimates the data of the interpolated pixel V(x, y) based on the data difference.

FIG. 3 shows a flowchart depicting the estimation for the data of the interpolated pixel V(x, y) in accordance with the invention. The process shown in the flowchart can be implemented by the deinterlacing module 108 shown in FIG. 1 or by the firmware of an electronic device, or by other techniques know by those skilled in the art. In step S 302 , the data difference d 11 . . . d 13 , d 21 . . . d 23 , d 31 . . . d 33 are calculated. A sum value S 1 is obtained by summing the data difference d 11 , d 12 and d 13 , a sum value S 2 is obtained by summing the data difference d 21 , d 22 and d 23 , and a sum value S 3 is obtained by summing the data difference d 31 , d 32 and d 3 . In step S 304 , the three sum values S 1 , S 2 and S 3 are compared with each other. When the minimum is S 1 , step S 306 is performed to estimate the data of the interpolated pixel V(x, y) according to the data of the pixels V(x−1, y−1) and V(x+1, y+1). When the minimum is S 2 , step S 308 is performed to estimate the data for the interpolated V(x, y) based on the data of the pixels V(x, y−1) and V(x, y+1). When the minimum is S 3 , step S 310 is performed to estimate the data for the interpolated pixel V(x, y) based on the pixels V(x+1, y−1) and V(x−1, y+1). The estimation realized in steps S 306 , S 308 and S 310 may be performed in various ways. For example, in step S 306 , the data for the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x−1, y−1) and V(x+1, y+1). In step S 308 , the data for the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x, y−1) and V(x, y+1). In step S 310 , the data for the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x+1, y−1) and V(x−1, y+1).

FIG. 4 depicts an example showing benefits from the deinterlacing process in accordance with the invention. FIG. 4 shows ten pixels of an image field, wherein a line is shown on the third column (X=x) of the image field. As shown, the pixels V(x−2, y−1), V(x−1, y−1), V(x+1, y−1), V(x+2, y−1), V(x−2, y+1), V(x−1, y+1), V(x+1, y+1) and V(x+2, y+1) are all blank and only pixels V(x, y−1) and V(x, y+1) are darkened. With the deinterlacing process of FIG. 3 , it is easy to determine that the sum value S 2 (sum of the data difference d 21 , d 22 and d 23 ) is the minimum one of S 1 , S 2 and S 3 , so that step S 308 may be performed and the data for the interpolated pixel V(x, y) may be estimated based on the data of the pixels V(x, y−1) and V(x, y+1). For example, the data for the interpolated pixel V(x, y) may be the average of the data of pixels V(x, y−1) and V(x, y+1). Thus, the interpolated pixel V(x, y) is not blank and the deinterlaced image frame fully shows the line on the third column (X=x).

The performance of the deinterlacing process may be further improved. Referring to FIG. 5 , data difference d 41 between the pixels V(x−1, y−1) and V(x, y+1) and data difference d 42 between the pixels V(x, y−1) and V(x+1, y+1), data difference d 51 between the pixels V(x, y−1) and V(x−1, y+1) and data difference d 52 between the pixels V(x+1, y−1) and V(x, y+1) are further considered in the deinterlacing process.

›DETAILED DESCRIPTION OF THE INVENTION · 2 of 2

FIG. 6 is a flowchart depicting a deinterlacing process in accordance with the invention, and may be implemented by the deinterlacing module 108 of FIG. 1 or by a firmware of an electronic device or by other techniques, such as a software and hardware co-design. Compared to step S 302 of FIG. 3 , step S 602 further calculates data difference d 41 , d 42 , d 51 and d 52 and obtains a sum value S 4 by summing the data difference d 41 and d 42 and a sum value S 5 by summing the data difference d 51 and d 52 . Because the sampling rule of the sum values S 4 and S 5 are different from that of the sum values S 1 . . . S 3 , in step S 602 , the sum values S 1 . . . S 5 are further provided with weighted factors to convert the sum value S 1 . . . S 5 to the weighted sum value D 1 . . . D 5 , wherein D i =w i . S i , i=1 . . . 5 and w i represent the weighted factors. In step S 604 , the weighted sum values D 1 . . . D 5 are compared with each other. When the minimum is D 1 , the process performs step S 606 to estimate the data of the interpolated pixel V(x, y) based on the data of the pixels V(x−1, y−1) and V(x+1, y+1). When the minimum of the D 2 , the process performs step S 608 to estimate the data of the interpolated pixel V(x, y) according to the data of the pixels V(x, y−1) and V(x, y+1). When the minimum is D 3 , the process performs of S 610 to estimate the data of the interpolated pixel V(x, y) according to the data of the pixels V(x+1, y−1) and V(x−1, y+1). When the minimum is D 4 , the process performs step S 612 to estimate the data of the interpolated pixel V(x, y) based on the data of the pixels V(x−1, y−1), V(x, y−1), V(x, y+1) and V(x+1, y+1). When the minimum is D 5 , the process performs step S 614 to estimate the data of the interpolated pixel V(x, y) based on the data of the pixels V(x, y−1), V(x+1, y−1), V(x−1, y+1) and V(x, y+1). The data estimations shown in steps S 606 . . . S 614 may be realized by several methods. In step S 606 , the data of the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x−1, y−1) and V(x+1, y+1). In steps S 608 , the data of the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x, y−1) and V(x, y+1). In step S 610 , the data of the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x+1, y−1) and V(x−1, y+1). In step S 612 , the data of the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x−1, y−1), V(x, y−1), V(x, y+1) and V(x+1, y+1). In step S 614 , the data of the interpolated pixel V(x, y) may be estimated by averaging the data of the pixels V(x, y−1), V(x+1, y−1), V(x−1, y+1) and V(x, y+1).

The deinterlacing process introduced in FIGS. 5 and 6 can perfectly deinterlace the image of stripes (such as the image of railings). The stripes of the railings can be completely shown in the deinterlaced image frame.

FIG. 7 further depicts another deinterlacing technique in accordance with the invention, the estimation for the data of the interpolated pixel V(x, y) may further consider data difference d 43 between the data of the pixels V(x−2, y−1) and V(x−1, y+1), data difference d 44 between the data of the pixels V(x+1, y−1) and V(x+2, y+1), data difference d 53 between the data of the pixels V(x−1, y−1) and V(x−2, y+1) and data difference d 54 between the data of the pixels V(x+2, y−1) and V(x+1, y+1). The calculation of the sum values S 4 and S 5 , the weighted factors for calculating the weighted sum values D 1 . . . D 5 , and the steps S 612 and S 614 are adjusted accordingly.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

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Classifications

2 codes
IPC · International Patent Classification
Section H — Electricity
  • H04N7/01
USPC · US Patent Classification
348/448

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Paulos Natnael
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