Current mode control type switching regulator

The present invention relates to a current mode control type switching regulator, in particular to a switching regulator capable of stable operation even when there is a large difference between an input voltage and an output voltage.

FIG. 5 is a diagram depicting an example of a slope voltage generating circuit in a conventional current mode control type switching regulator (for example, see Patent Document 1). In the current mode control type switching regulator, an inductor current iL flowing through an inductor when a switching transistor is on is the same as a drain current of the switching transistor. When on-resistance of the switching transistor is known, the inductor current iL can be detected by detecting a voltage drop caused by the switching transistor.

In view of this, an inductor current detecting circuit 110 a detects a voltage drop caused when the switching transistor is on. When the switching transistor is on, a gate signal S 101 supplied to the switching transistor is at a low level. At this time, a PMOS transistor M 113 is turned on at the same time as a PMOS transistor M 112 is turned off. Therefore, a voltage VLx of a node Lx between the switching transistor and the inductor is inputted to a non-inverting input terminal of an operational amplifier circuit 111 .

The operational amplifier circuit 111 controls a gate voltage of a PMOS transistor M 111 so that a source voltage of the PMOS transistor M 111 becomes the same voltage level as the voltage VLx. Therefore, a drain current of the PMOS transistor M 111 is proportional to the inductor current iL. The drain current is converted into a voltage VA by a resistor R 112 . The voltage VA is outputted through a resistor R 113 . When the resistors R 111 and R 112 have the same resistance values, the source voltage VA of the PMOS transistor M 111 is expressed by a formula (a) below.

VA=V in− VLx   (a)

Further, when the switching transistor is off, the gate signal S 101 is at a high level. In this case, the PMOS transistor M 113 is turned off at the same time as the PMOS transistor M 112 is turned on. Therefore, an input voltage Vin is inputted to the non-inverting input terminal of the operational amplifier circuit 111 . Since the operational amplifier circuit 111 turns off the PMOS transistor M 111 , the source voltage VA of the PMOS transistor becomes 0 V. An NMOS transistor M 114 of a ramp voltage generating circuit 110 b is on and conductive during a period when the gate signal S 101 is at a high level. Therefore, a current i 113 outputted from the constant current circuit 113 is bypassed to the NMOS transistor M 114 . As a result, a terminal voltage VB of a ramp capacitor C 111 is 0 V.

Subsequently, when the gate signal S 101 is at a low level, the NMOS transistor M 114 is turned off and nonconductive. Therefore, the ramp capacitor C 111 is charged by the output current i 113 of the constant current circuit 113 . A terminal voltage VB of the ramp capacitor C 111 is linearly increased to generate a ramp voltage. The ramp voltage VB is outputted through a resistor R 114 . Output voltages of the inductor current detecting circuit 110 a and the ramp voltage generating circuit 110 b are added by the resistors R 113 and R 114 and outputted from a node between the resistors R 113 and R 114 . The resistors R 113 and R 114 have the same resistance values. When a voltage of the node between the resistors R 113 and R 114 is VC, the voltage VC is expressed by a formula (b) below.

VC =( VA+VB )/2=( V in− VLx+VB )/2  (b)

The voltage VC in the above formula (b) is inputted to a non-inverting input terminal of an operational amplifier circuit 114 in an offset voltage generating circuit 110 c . The operational amplifier circuit 114 controls a gate voltage of an NMOS transistor M 116 so that a source voltage of the NMOS transistor M 116 becomes the same voltage level as the voltage VC. As a result, a drain current of the NMOS transistor M 116 is proportional to the voltage VC. The drain current is supplied to a resistor R 117 through a current mirror circuit formed of PMOS transistors M 117 and M 118 . The drain current is converted into a voltage by the resistor R 117 to be an output voltage Vslp of the slope voltage generating circuit 110 .

However, the resistor R 117 also receives a current supply from a constant current circuit 115 in addition to the output current of the current mirror circuit. Therefore, an offset voltage (r 117 ×i 115 ) corresponding to a voltage obtained by multiplying an output current i 115 of the constant current circuit 115 with a resistance value r 117 of the resistor R 117 is added to the output voltage Vslp of the slope voltage generating circuit 110 . In the case where the resistors R 116 and R 117 have the same resistance values and the resistance value of the resistor R 117 is r 117 , the output voltage Vslp of the slope voltage generating circuit 110 is expressed by a formula (c) below.

Note that (r 117 ×i 115 ) in the formula (c) indicates the offset voltage.

Patent Document 1: Japanese Laid-Open Patent Application No. 2006-246626

However, poor linearity in a rising part of the slope voltage Vslp has been a problem in the slope voltage generating circuit 110 shown in FIG. 5 . FIG. 6 is a diagram showing a waveform example of the slope voltage Vslp generated by the slope voltage generating circuit 110 . As shown in FIG. 6 , the slope voltage Vslp rises gently right after the gate signal S 101 becomes a low level, and the inclination gradually approaches a proper inclination over time. When a time Tdel passes after the gate signal S 101 becomes a low level, the slope voltage Vslp rises with the proper inclination.

The slope voltage Vslp rises gently due to a delay time caused when the voltage VC is converted into a current by a voltage-current converter circuit of the operational amplifier circuit 114 and a delay time caused by the current mirror circuit formed of the PMOS transistors M 117 and M 118 . When the slope voltage Vslp rises gently, the operation of the switching regulator becomes unstable in such cases where there is a large difference between the input voltage Vin and an output voltage Vo of the switching regulator, in which case an on-time of the switching transistor becomes shorter than the time Tdel. As a result, a defect may be caused in that the output voltage Vo becomes unstable, and the like.

It is an object of at least one embodiment of the present invention to provide a current mode control type switching regulator capable of generating a slope voltage having favorable linearity and of stable operation, that substantially obviate one or more of the above-described problems.

According to one aspect of the present invention, a current mode control type switching regulator for converting an input voltage into an output voltage that is a predetermined constant voltage is provided. The current mode control type switching regulator includes a switching element; an inductor energized by the input voltage in response to switching of the switching element; a rectifier element for discharging the inductor; and a slope voltage generating circuit unit configured to generate and output a slope voltage having an inclination responsive to a current flowing through the inductor. The current mode control type switching regulator is configured to amplify a voltage difference between a predetermined reference voltage and a divided voltage obtained by dividing the output voltage; compare the amplified voltage and the slope voltage to generate a pulsed signal having a duty cycle determined by the comparison; and control switching of the switching element in response to the pulsed signal. The slope voltage generating circuit unit includes an inductor current detecting circuit for detecting a current flowing through the inductor when the switching element is on to energize the inductor and converting the detected current into a voltage; and a ramp voltage generating circuit for generating and outputting a ramp voltage having a predetermined inclination. The slope voltage generating circuit unit is configured to add the voltage obtained by the inductor current detecting circuit and the ramp voltage to generate the slope voltage. The ramp voltage generating circuit includes a constant current circuit for generating and outputting a predetermined constant current; an offset voltage generating resistor through which the constant current outputted by the constant current circuit flows; and a ramp capacitor charged by the constant current outputted by the constant current circuit through the offset voltage generating resistor, said ramp voltage generating circuit being configured to add a voltage drop caused by the offset voltage generating resistor to a terminal voltage of the ramp capacitor to generate and output the ramp voltage.

FIG. 1 is a diagram showing a circuit example of a current mode control type switching regulator of a first embodiment of the present invention.

FIG. 2 is a timing chart showing a waveform example of each signal in the switching regulator 1 shown in FIG. 1 .

FIG. 3 is a diagram showing a circuit example of a slope voltage generating circuit 4 of FIG. 4 .

FIG. 4 is a diagram showing an enlarged waveform of a slope voltage Vslp of FIG. 2 .

FIG. 5 is a diagram showing a circuit example of a slope voltage generating circuit in a conventional current mode control type switching regulator.

FIG. 6 is a diagram showing a waveform example of a slope voltage Vslp generated in a slope voltage generating circuit 110 of FIG. 5 .

The present invention is described in detail based on an embodiment of the present invention with reference to the drawings.

First Embodiment

FIG. 1 is a diagram showing a circuit example of a current mode control type switching regulator of a first embodiment of the present invention. In FIG. 1 , the current mode control type switching regulator (hereinafter called a switching regulator) 1 serves as a synchronous rectification step-down switching regulator, which steps down an input voltage Vin inputted to an input terminal IN to a predetermined constant voltage to output the constant voltage as an output voltage Vout from an output terminal OUT to a load 20 .

The switching regulator 1 includes a switching transistor M 1 formed of a PMOS transistor that controls an output of a current supplied from the input terminal IN; a synchronous rectifier transistor M 2 formed of an NMOS transistor; an inductor L 1 , a smoothing capacitor C 1 ; and resistors R 1 and R 2 for detecting an output voltage, that divide the output voltage Vout to generate and output a divided voltage Vfb. Further, the switching regulator 1 includes a reference voltage generating circuit 2 that generates and outputs a predetermined reference voltage Vref; an error amplifier circuit 3 that compares the divided voltage Vfb and the reference voltage Vref and amplifies a voltage difference to generate and output an error voltage Ve; and a slope voltage generating circuit 4 that generates and outputs a slope voltage Vslp.

Moreover, the switching regulator 1 includes a PWM comparator 5 that compares the error voltage Ve outputted by the error amplifier circuit 3 and the slope voltage Vslp to generate and output a pulsed signal Spw for performing PWM (Pulse Width Modulation) control. The pulsed signal Spw has a pulse width that corresponds to the error voltage Ve. The switching regulator 1 further includes an oscillation circuit 6 that generates and outputs a predetermined clock signal CLK; an RS flip-flop circuit 7 having a set input terminal S receiving the clock signal CLK outputted by the oscillation circuit 6 and a reset input terminal R receiving the pulsed signal Spw outputted by the PWM comparator 5 ; and an inverter 8 that generates a control signal S 1 for controlling switching of the switching transistor M 1 and the synchronous rectifier transistor M 2 in response to an output signal Sq outputted by the RS flip-flop circuit 7 to drive the switching transistor M 1 and the synchronous rectifier transistor M 2 .

Note that the switching transistor M 1 serves as a switching element; the synchronous rectifier transistor M 2 serves as a rectifier element; and the slope voltage generating circuit 4 serves as a slope voltage generating circuit unit. Further, in the switching regulator 1 shown in FIG. 1 , circuits other than the inductor L 1 and the smoothing capacitor C 1 may be integrated into one IC.

The switching transistor M 1 is connected between the input voltage Vin and a drain of the synchronous rectifier transistor M 2 . A source of the synchronous rectifier transistor M 2 is connected to a ground voltage GND. The inductor L 1 is connected between a drain of the switching transistor M 1 and the output terminal OUT. The capacitor C 1 and a serial circuit of the resistors R 1 and R 2 are connected in parallel between the output terminal OUT and the ground voltage GND. The divided voltage Vfb, being a voltage at a node between the resistors R 1 and R 2 , is inputted to an inverting input terminal of the error amplifier circuit 3 . The reference voltage Vref is inputted to a non-inverting input terminal of the error amplifier circuit 3 .

Further, the PWM comparator 5 has an inverting input terminal that receives the error voltage Ve outputted by the error amplifier circuit 3 , and a non-inverting input terminal that receives the slope voltage Vslp. The output signal Sq of the RS flip-flop circuit 7 is inverted in level by the inverter 8 and inputted to each gate of the switching transistor M 1 and the synchronous rectifier transistor M 2 , and also to the slope voltage generating circuit 4 . A voltage VLx of a node Lx between the switching transistor M 1 and the synchronous rectifier transistor M 2 is inputted to the slope voltage generating circuit 4 .

Next, an operation of the switching regulator 1 is described. FIG. 2 is a timing chart showing a waveform example of each signal in the switching regulator 1 shown in FIG. 1 . Note that iout denotes an output current outputted from the output terminal OUT to the load 20 . The clock signal CLK which becomes a high level on a predetermined cycle is inputted from the oscillation circuit 6 to the set input terminal S of the RS flip-flop circuit 7 . When the clock signal CLK becomes a high level, the output signal Sq of the RS flip-flop circuit 7 becomes a high level. Therefore, the control signal S 1 at a low level is inputted to each gate of the switching transistor M 1 and the synchronous rectifier transistor M 2 . As a result, the switching transistor M 1 is turned on to be conductive while the synchronous rectifier transistor M 2 is turned off to be nonconductive. In this case, the input voltage Vin is applied to a serial circuit formed of the inductor L 1 and the smoothing capacitor C 1 . An inductor current iL flowing through the inductor L 1 increases linearly over time. When the inductor current iL becomes larger than the output current iout, the smoothing capacitor C 1 is charged and the output voltage Vout rises.

The slope voltage generating circuit 4 detects the inductor current iL and converts the inductor current iL into a voltage, and at the same time generates a compensation voltage to prevent subharmonic oscillation. Moreover, the slope voltage generating circuit 4 adds the compensation voltage to the voltage obtained by converting the inductor current iL to generate and output the slope voltage Vslp. The slope voltage Vslp linearly rises during a period when the switching transistor M 1 is on. The error amplifier circuit 3 , on the other hand, amplifies a voltage difference between the divided voltage Vfb and the reference voltage Vref to generate and output the error voltage Ve. The PWM comparator 5 compares the error voltage Ve and the slope voltage Vslp. The PWM comparator 5 outputs a signal Spw at a high level when the slope voltage Vslp becomes higher than the error voltage Ve to reset the RS flip-flop circuit 7 . As a result, the output signal Sq of the RS flip-flop circuit 7 becomes a low level and the control signal S 1 becomes a high level. Therefore, the switching transistor M 1 is turned off to be nonconductive. At the same time, the synchronous rectifier transistor M 2 is turned on to be conductive.

When the switching transistor M 1 is turned off and the synchronous rectifier transistor M 2 is turned on, the electric energy in the inductor L 1 is discharged. When the inductor is energized, electric energy is accumulated in the inductor. In response to this discharging operation, the inductor current iL linearly decreases over time. When the inductor current iL becomes smaller than the output current iout, a power is supplied from the smoothing capacitor C 1 to the load 20 , which decreases the output voltage Vout. After one cycle of the clock signal CLK outputted by the oscillation circuit 6 , the clock signal CLK becomes a high level again. As a result, the switching transistor M 1 is turned on and the synchronous rectifier transistor M 2 is turned off. Consequently, the inductor current iL flows and the output voltage Vout rises.

Here, when the output current iout is increased at a time T 0 , the output voltage Vout is decreased and the error voltage Ve outputted by the error amplifier circuit 3 rises. Therefore, it takes longer for the slope voltage Vslp to be higher than the voltage level of the error voltage Ve. As a result, an on-time of the switching transistor M 1 becomes longer, which makes a time to supply the power to the inductor L 1 longer. Thus, the output voltage Vout rises. When the output voltage Vout rises, on the other hand, the on-time of the switching transistor M 1 becomes shorter to decrease the output voltage Vout. In this manner, by controlling the time to turn on/off the switching transistor M 1 and the synchronous rectifier transistor M 2 in a complimentary manner in response to a change of the output voltage Vout, the output voltage Vout is stabilized.

Next, FIG. 3 is a diagram showing a circuit example of the slope voltage generating circuit 4 shown in FIG. 1 . In FIG. 3 , the slope voltage generating circuit 4 is formed of an inductor current detecting circuit 11 and a ramp voltage generating circuit 12 . The inductor current detecting circuit 11 is formed of an operational amplifier circuit 21 , PMOS transistors M 21 to M 23 , an inverter 22 , and resistors R 21 to R 23 . The ramp voltage generating circuit 12 is formed of an operational amplifier circuit 23 , NMOS transistors M 24 and M 25 , a constant current circuit 24 , a ramp capacitor C 21 , and resistors R 24 and R 25 . Note that the resistor R 25 serves as an offset voltage generating resistor. The operational amplifier circuit 23 , the NMOS transistor M 25 , and the resistor R 24 serve as an impedance converter circuit.

In the inductor current detecting circuit 11 , the PMOS transistor M 22 has a source connected to an input voltage Vin and a drain connected to a non-inverting input terminal of the operational amplifier circuit 21 . Further, the PMOS transistor M 22 has a gate connected to an output terminal of the inverter 22 . An input terminal of the inverter 22 receives the control signal S 1 . The PMOS transistor M 23 has a source connected to the non-inverting input terminal of the operational amplifier circuit 21 , a drain connected to the node Lx, and a gate receiving the control signal S 1 .

The resistor R 21 is connected between the input voltage Vin and the source of the PMOS transistor M 21 . An inverting input terminal of the operational amplifier circuit 21 is connected to a source of the PMOS transistor M 21 . Further, an output terminal of the operational amplifier circuit 21 is connected to a gate of the PMOS transistor M 21 . The resistor R 22 is connected between a drain of the PMOS transistor M 21 and a ground voltage GND. One terminal of the resistor R 23 is connected to a node between the PMOS transistor M 21 and the resistor R 22 . The other terminal of the resistor R 23 serves as an output terminal of the inductor current detecting circuit 11 .

In the ramp voltage generating circuit 12 , the constant current circuit 24 is connected between the input voltage Vin and the non-inverting input terminal of the operational amplifier circuit 23 . The resistor R 25 and the ramp capacitor C 21 are connected in serial between the non-inverting input terminal of the operational amplifier circuit 23 and the ground voltage GND. The NMOS transistor M 24 is connected in parallel to the ramp capacitor C 21 . A gate of the NMOS transistor M 24 receives the control signal S 1 . Further, the NMOS transistor M 25 is connected between the input voltage Vin and the inverting input terminal of the operational amplifier circuit 23 . A gate of the NMOS transistor M 25 is connected to an output terminal of the operational amplifier circuit 23 . One terminal of the resistor R 24 is connected to an inverting input terminal of the operational amplifier circuit 23 . The other terminal of the resistor R 24 serves as an output terminal of the ramp voltage generating circuit 12 . The other terminal of the resistor R 23 , serving as the output terminal of the inductor current detecting circuit 11 , and the other terminal of the resistor R 24 , serving as the output terminal of the ramp voltage generating circuit 12 , are connected to each other. A node between the resistors R 23 and R 24 serves as an output terminal of the slope voltage generating circuit 4 , which outputs the slope voltage Vslp.

Here, the inductor current iL which flows through the inductor L 1 when the switching transistor M 1 is on equals to a drain current of the switching transistor M 1 . Therefore, when on-resistance of the switching transistor M 1 is known, the inductor current iL can be detected by detecting a voltage drop caused by the switching transistor M 1 . The inductor current detecting circuit 11 detects a voltage drop caused by the switching transistor M 1 when the switching transistor M 1 is on. When the switching transistor M 1 is on, the control signal S 1 is at a low level. In this case, the PMOS transistor M 22 is off and nonconductive while the PMOS transistor M 23 is on and conductive. Therefore, the voltage VLx of the node Lx is inputted to the non-inverting input terminal of the operational amplifier circuit 21 .

The operational amplifier circuit 21 controls a gate voltage of the PMOS transistor M 21 so that a source voltage of the PMOS transistor M 21 becomes the same voltage level as the voltage VLx. Therefore, a drain current of the PMOS transistor M 21 becomes proportional to the inductor current iL. The drain current of the PMOS transistor M 21 is supplied to the resistor R 22 and converted into a voltage by the resistor R 22 . The converted voltage is outputted through the resistor R 23 . If the resistors R 21 and R 22 have the same resistance values, a drain voltage Va of the PMOS transistor M 21 is expressed by a formula (1) below.

Va=V in− VLx   (1)

When the switching transistor M 1 is off, the control signal S 1 is at a high level. At this time, the PMOS transistor M 22 is on while the PMOS transistor M 23 is off. As a result, the same voltage as the input voltage Vin is inputted to the non-inverting input terminal of the operational amplifier circuit 21 . Since the operational amplifier circuit 21 controls the PMOS transistor M 21 to be turned off, the voltage Va as the drain voltage of the PMOS transistor M 21 becomes 0 V.

Next, an operation of the slope voltage generating circuit 12 is described. In the slope voltage generating circuit 12 , the NMOS transistor M 24 is on during a period when the control signal S 1 is at a high level. Therefore, a constant current i 24 outputted by the constant current circuit 24 is bypassed by the NMOS transistor M 24 . The terminal voltage Vb of the ramp capacitor C 21 is 0 V. However, since the resistor R 25 causes a voltage drop, a voltage Vd of the non-inverting input terminal of the operational amplifier circuit 23 at this time is expressed by a formula (2) below when the resistor R 25 has a resistance value of r 25 .

Vd=r 25 ×i 24  (2)

When the control signal S 1 is at a low level, the NMOS transistor M 24 is turned off to be nonconductive. The ramp capacitor C 21 is charged by an output current i 24 of the constant current circuit 24 . As a result, a terminal voltage Vb of the ramp capacitor C 21 linearly rises to generate a ramp voltage. In this case, the voltage Vd of the non-inverting input terminal of the operational amplifier circuit 23 is expressed by a formula (3) below.

Vd=Vb +( r 25 ×i 24)  (3)

Since a source voltage of the NMOS transistor M 25 equals to the voltage Vd, the slope voltage Vslp can be expressed by a formula (4) below when the resistors R 23 and R 24 have the same resistance values and the resistance value is sufficiently larger than output impedance of the voltages Va and Vd.

Vslp =( Va+Vd )/2  (4)

The voltage Va is (Vin−VLx) as in the formula (1). The voltage Vd is {Vb+(r 25 ×i 24 )} as in the formula (3). Therefore, the formula (4) is expressed by a formula (5) below.

A second term of a right hand side in the formula (5), which is (r 25 ×i 24 )/2, indicates an offset voltage Vof. That is, by setting the resistance value of the resistor R 25 so that the second terms of the right hand sides of the formula (5) and the formula (c) become equal to each other, the slope voltage Vslp can be set the same as the slope voltage Vslp in the conventional circuit shown in FIG. 5 .

In this manner, in the current mode control type switching regulator of the first embodiment, a voltage-current converter circuit and a current mirror circuit that cause a delay in rising of the slope voltage Vslp are not necessary. Since the circuit configuration can be simplified, cost can be reduced. Further, as shown in FIG. 4 , the slope voltage Vslp with favorable linearity can be generated right after the control signal S 1 becomes a low level. Consequently, a stable operation can be performed even when an on-time of the switching transistor M 1 is short.

Note that although the synchronous rectification step-down type switching regulator has been taken as an example in the first embodiment, the present invention is not limited to this. The present invention can be applied to a non-synchronous rectification step-down type switching regulator, and to synchronous rectification or non-synchronous rectification step-up type switching regulators as well. The present invention is applied to a current mode control type switching regulator having a slope voltage generating circuit.

According to one embodiment, an impedance converter circuit configured to perform impedance conversion on a ramp voltage and output the ramp voltage is provided in the ramp voltage generating circuit.

According to a current mode control type switching regulator of one embodiment of the present invention, a voltage-current converter circuit and a current mirror circuit that cause a delay in rising of a slope voltage can be omitted, and a slope voltage with favorable linearity can be generated right after a switching element is turned on to start energizing an inductor. As a result, a stable operation can be performed even when an on-time of the switching element is short.

The present application is based on Japanese Priority Application No. 2008-057414 filed on Mar. 7, 2008, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.