Amplifier circuit

This invention relates to an improved amplifier, and in particular to a CMOS push-pull amplifier.

A known CMOS push-pull amplifier will now be described with reference to FIG. 1 . The known CMOS push-pull amplifier 10 comprises a PMOS transistor MP 1 and an NMOS transistor MN 1 that are connected between the voltage supply terminals V DD and GND. The input signal to the amplifier 10 is provided by the voltage source VRF and the source resistance Rsource, and the output signal from the amplifier 10 is fed into the load resistance Rload. A resistor Rfb provides biasing, input matching and control over the gain. The capacitor Csup realizes a low impedance between the voltage supply terminals V DD and GND at high-frequencies, attenuating any RF signals that may be present between V DD and GND.

The drain current of a MOS transistor approximately depends on the geometrical properties of the transistor as shown in equation (1):

I D = k ⁢ W L ⁢ ( V GS - V TH ) 2 ( 1 )

Wherein I D is the drain current, k is a constant that depends on the technology used, W is the width of the transistor and L is the length of the transistor, V GS is the voltage applied between the gate and the source terminals of the transistor, and V TH is the threshold voltage of the transistor.

The transistors MP 1 and MN 1 both have a voltage threshold (V TH ) of around 300 mV. If a MOS transistor pair is realized with matched transistors, then the output (and input) DC voltage is typically half of the supply voltage. When no input signal VRF is supplied, the circuit is in equilibrium, with both transistors MP 1 and MN 1 being turned on and with V GS =V DD /2. At equilibrium, a bias current I BIAS flows through the transistors MP 1 and MN 1 depending on the threshold values V TH of the PMOS and NMOS transistor respectively.

Such CMOS push-pull analogue amplifiers can find applications as low-noise, wideband amplifiers for amplifying Radio Frequency (RF) signals.

One of the problems with circuits comprising two transistors connected in series between positive and negative voltage supply terminals, is that small voltage variations in the supply voltage level can lead to large variations in the bias current I BIAS that flows through the two transistors. Referring to the circuit of FIG. 1 and to the equation (1) above, the drain (bias) current flowing through each transistor MN 1 and MN 2 is proportional to the square of (V GS −V TH ). For example, if V DD is 1.2 V, and the V TH of both transistors MP 1 and MN 1 is 0.3 V, then an increase of V DD to 1.3V (a factor of 1.083) causes the V GS voltage of both MP 1 and MN 1 to rise by 0.05V, which causes the DC bias current to increase with a factor:

Hence, an increase in the supply voltage by a factor of 1.083 results in an increase in the bias current by the much larger factor of 1.36. Therefore, even small variations in the supply voltage level can make overall power consumption difficult to predict, and furthermore can result in variations in the input and output impedances, the gain, and the noise characteristics of the amplifier.

These variations complicate the design of circuits based around two series connected transistors, and make consistent operation of the circuits difficult to achieve.

It is therefore an object of the invention to improve on the known art.

According to a first aspect of the invention, there is provided a circuit comprising two transistors connected in series between positive and negative voltage supply terminals, the circuit further comprising a control circuit adapted to:

measure a current or voltage parameter of the circuit that is indicative of a bias current conducted through the two transistors; and alter the bulk voltage of at least one of the transistors in response to the measured parameter so as to maintain the bias current at a target level.

Hence, there is provided a circuit that can modify the bulk voltage of at least one of its transistors so as to maintain a steady level of bias current. The modification of the at least one transistors bulk voltage is used to control the at least one transistors threshold voltage, and the at least one transistors threshold voltage has a direct effect on the level of the bias current. This is because a reduction in the threshold voltage results in an increase in the bias current when all other factors are unchanged.

The bulk voltage that is required to maintain the bias current at a target level can be determined by measuring a current or voltage parameter of the circuit that is indicative of the present level of the bias current. For example, if the present level is measured as being slightly above or below the target level, then the bulk voltage can altered to bring the present level closer to the target level.

The maintenance of a steady level of bias current makes the power consumption of the circuit simpler to predict, and improves the consistency of the input and output impedances, the gain, and the noise characteristics of the circuit. Furthermore, maintaining a steady level of bias current helps prevent variations in the power supply voltage from entering the signal path, thereby improving the Power Supply Rejection.

Advantageously, the two transistors may be an NMOS transistor and a PMOS transistor. Using a suitable IC manufacturing process, these transistors can be placed in an isolating well, and the bulk voltages of the transistors can be easily controlled. Furthermore, the two transistors can together form a push-pull class AB amplifier suitable for use in analogue amplifier applications, as will be apparent to those skilled in the art. These amplifier circuits may be cascaded together to form a multiple-stage amplifier to achieve higher levels of gain compared to a single-stage amplifier.

The measured parameter that is indicative of the level of the bias current is a parameter whose value changes along with changes in the level of the bias current. This is irrespective of whether the parameter causes the change in the bias current, whether the bias current causes the change in the parameter, or whether another factor acts to cause changes in both the bias current and the parameter together.

Advantageously, the measured parameter may be the supply voltage level, the supply voltage level being the voltage difference between the positive supply voltage level and the negative supply voltage level. The supply voltage level is indicative of the bias current level, because an increased supply voltage level results in an increased bias current level when all other factors are unchanged. Hence, if the measured level of the supply voltage increases, then the threshold voltage of the at least one transistor may be increased by altering the bulk voltage of the at least one transistor, thereby counteracting the effect of the increased supply voltage on the level of the bias current.

If the measured level of the supply voltage decreases, then the threshold voltage of the at least one transistor may be decreased by altering the bulk voltage of the at least one transistor, thereby counteracting the effects of the decreased supply voltage on the level of the bias current.

Advantageously, the control circuit may comprise at least one replica transistor for determining the bulk voltage level that should be applied to the at least one transistor of the two transistors. Each replica transistor may be connected to a respective constant current source in series between the positive and negative voltage supply terminals, and the bulk voltage level of the replica transistor may be altered so as to maintain a steady voltage at the connection between the replica transistor and the respective constant current source.

The bulk voltage levels of the at least one replica transistors are then used to alter the bulk voltage levels of at least one of the two transistors. The term replica is used to denote that a replica transistor effectively replicates a one of the two transistors, so that the correct bulk voltages for a given supply voltage level can be accurately determined.

Alternatively, the parameter that is measured may be the level of the bias current itself. If the measured level of the bias current flowing through the two transistors is above a target level, then the threshold voltages of the at least one transistor of the two transistors may be increased by altering the bulk voltages of the at least one transistors, thereby decreasing the level of the bias current to the target level.

If the measured level of the bias current is below a target level, then the threshold voltages of the at least one transistors may be decreased by altering the bulk voltages of the at least one transistors, thereby increasing the level of the bias current up to the target level.

According to a second aspect of the invention, there is provided a method for maintaining a bias current of a circuit at a target level, the circuit comprising two transistors connected in series between positive and negative voltage supply terminals, the circuit further comprising a control circuit and the method comprising:

measuring, using the control circuit, a current or voltage parameter of the circuit that is indicative of a bias current conducted through the two transistors; and altering, using the control circuit, the bulk voltage of at least one of the transistors in response to the measured parameter, so as to maintain the bias current at a target level.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

FIG. 1 shows a circuit diagram of a CMOS amplifier circuit as known in the prior art and as discussed above;

FIG. 2 shows a circuit diagram of a CMOS amplifier circuit according to an embodiment of the invention;

FIG. 3 shows a circuit diagram of a control circuit for use in the FIG. 2 embodiment;

FIGS. 4 a and 4 b show circuit diagrams of different parts of an alternate control circuit for use in the FIG. 2 embodiment;

FIG. 5 shows a circuit diagram of an alternate implementation of the circuit of FIG. 4 b ; and

FIG. 6 shows a circuit diagram of a circuit according to a further embodiment of the invention.

Same or similar reference signs denote same or similar features.

The CMOS amplifier circuit 24 that is shown in FIG. 2 comprises an NMOS transistor MN 2 and a PMOS transistor MP 2 . The drain terminals of the two transistors MN 2 and MP 2 are connected together in series and form the output of the circuit. The gate terminals of the two transistors MN 2 and MP 2 are connected together and form the input Vin to the circuit. The source terminal of the NMOS transistor MN 2 is connected to the negative power supply terminal GND, and the source terminal of the PMOS transistor MP 2 is connected to the positive power supply terminal V DD . A control circuit 25 applies voltage signals V B1 and V B2 to the bulk terminals of the transistors MN 2 and MP 2 respectively.

A bias current I BIAS1 flows from the positive V DD to the negative GND power supply terminal through the two series connected transistors. The bias current I BIAS1 biases the DC operating point of the amplifier. The DC operating point is the voltage point that the connection between the two transistors will return to at equilibrium (i.e. when no input signals are applied to the amplifier), as will be understood by those skilled in the art.

In use, the control circuit 25 effectively measures the supply voltage level V DD , and then sets the transistor bulk voltages V B1 and V B2 according to the supply voltage measurement. The supply voltage level V DD is indicative of the bias current I BIAS1 flowing through the transistors MN 2 and MP 2 , because an increase in the level of V DD causes an increase in the level of the bias current when all other factors are unchanged.

A change in the bulk voltage level of a transistor results in a change in the threshold voltage level of the transistor, due to the Body Effect (or ‘back gate effect’), as is known to those skilled in the art. For example, for an enhancement mode NMOS MOSFET, the threshold voltage may be calculated according to the following equation:

V TH =V TO +χ(√{square root over (2φ F −V BS )}−√{square root over (2φ F )})

wherein V TO is the zero bias threshold voltage, χ is the body effect parameter, V BS is the bulk-source voltage, and 2φ F is the absolute value of the surface voltage.

Hence, for the enhancement mode NMOS MOSFET, an increase in the bulk-source voltage results in a decrease in the threshold voltage. For a PMOS MOSFET, an increase in the bulk-source voltage results in an increase in the threshold voltage.

Therefore, when the control circuit 25 detects an increase in the level of the voltage supply V DD (which is expected to result in an increase in the bias current I BIAS1 ), the control circuit decreases the bulk voltage V B1 and increases the bulk voltage V B2 , thereby increasing the threshold voltages of both the transistors MN and MP, and keeping the bias current I BIAS1 down at a target level.

Although the FIG. 2 embodiment describes the case where the bulk voltages of both of the two transistors are controlled, those skilled in the art will appreciate that in other embodiments the control circuit 25 may only control the bulk voltage of one of the two transistors, for example MN 2 . Then, the bulk voltage of the transistor MN 2 may be altered to change the threshold voltage of transistor MN 2 by an amount sufficient to maintain the bias current at a target level. The threshold voltage of transistor MN 2 will clearly have to be altered further than if the threshold voltages of both transistors MN 2 and MP 2 were altered together.

It should be noted that the voltage source VRF, the resistors Rsource, Rfb, and Rload, and all of the capacitors are specific to this particular CMOS amplifier embodiment, and as such are not essential to the invention as defined in the appended claims. Many other circuit configurations comprising the two series connected transistors and the control circuitry 25 can benefit from the invention, and could easily be conceived by those skilled in the art.

FIG. 3 shows a circuit diagram of one possible implementation of the control circuit 25 of FIG. 2 . The control circuit comprises a series network connected between the positive and negative power supply voltages V DD and GND. The series network is formed by a resistor and a capacitor connected in parallel, a current source 26 that drives a current I DC dependent on the power supply voltage, and a further resistor and capacitor connected in parallel.

In use, a voltage level develops across the resistors according to the level of current I DC that is driven by the current source 26 . The voltage levels are applied to the bulk terminals of the transistors MN 2 and MP 2 . The level of the current I DC is set at K*(1.3−V DD ) mA, wherein K is a constant. For the circuit of FIG. 3 when implemented as the control circuit 25 of FIG. 2 , the bias current I BIAS1 is kept approximately constant over a supply voltage range of V DD =1.1-1.3 V when K=0.0025.

Hence, the control circuit effectively measures the level of the voltage parameter V DD , and in response applies voltage levels to the bulk terminals of transistors MN 2 and MP 2 .

The capacitors that are in parallel with the resistors reduce any RF signals that may be present at the bulk terminals of the transistors, including any noise generated by the resistors. Hence, the capacitors are optional and not essential to the circuit.

As an alternative to the FIG. 3 embodiment, in the case where the bulk voltage of only one of the two transistors (for example MN 2 ) is to be controlled, those skilled in the art will appreciate that a circuit comprising only the current source I DC and a single resistor through which the current I DC is driven will be sufficient to develop the voltage V B1 .

FIGS. 4 a and 4 b show circuit diagrams of different parts of an alternate control circuit 25 for use in the FIG. 2 embodiment. The circuit of FIG. 4 a is used to generate the voltage V B1 , and the circuit of FIG. 4 b is used to generate the voltage V B2 from the voltage V B1 .

Referring to FIG. 4 a , the control circuit comprises a voltage divider formed of two resistors Ra and Rb, a constant current source I REF1 , an NMOS transistor MN 5 , and an amplifier AMP 1 . The output of the voltage divider is connected to the inverting input (−) of the amplifier AMP 1 , and to the gate terminal of the transistor MN 5 . The output of the current source I REF1 is connected to the drain terminal of the transistor MN 5 , and to the non-inverting input (+) of the amplifier AMP 1 . The output of the amplifier AMP 1 is connected to the bulk terminal of the transistor MN 5 , and provides the output voltage signal V B1 .

In use, the voltage divider generates a reference voltage level V DD /2, the current source drives a current I REF1 , and the amplifier AMP 1 sets the bulk voltage V B1 of the transistor MN 5 , thereby altering the threshold voltage of the transistor MN 5 so as to make the drain terminal voltage of the transistor MN 5 (and the non-inverting input of the amplifier AMP 1 ) equal to the reference voltage level V DD /2. The transistor MN 5 serves as a replica of the transistor MN 2 , and so the circuit enables the bulk voltage of the transistor MN 2 to be set using the bulk voltage V B1 of the replica transistor MN 5 . This enables accurate control of the bias current through the two transistors MN 2 and MP 2 , without any need to directly measure the bias current of MN 2 and MP 2 . Hence, the design of the two transistor circuit portion is not constrained by a directly connected parameter measurement circuit.

The mirroring circuit 55 of FIG. 4 b generates the voltage signal V B2 by mirroring the voltage signal V B1 about a voltage level that is half of the supply voltage level, such that V B2 =V DD −(V B1 −GND). For example, if V DD =1.2V and V B1 =0.8V, then V B2 =0.4V. Hence, V B1 is mirrored about 0.6V (V DD /2) to give V B2 , as will be apparent to those skilled in the art.

When the circuits of FIGS. 4 a and 4 b are used to form the control circuit 25 of FIG. 2 , the operation of the FIG. 2 circuit is as follows. If the voltage level of the power supply V DD increases, then the bias current I BIAS1 through transistors MN 2 and MP 2 begins to increase above the target level, and the voltage level V DD /2 that is applied to the inverting terminal of the amplifier AMP 1 is increased. Then, the amplifier AMP 1 reduces the voltage V B1 , thereby increasing the threshold voltage of the transistor MN 5 leading to reduction of MN 5 drain current causing the voltage at the non-inverting input of the amplifier AMP 1 to go up to V DD /2. The mirroring circuit of FIG. 4 b causes a corresponding increase in the voltage V B2 , since V B2 =V DD −(GND−V B1 ).

The reduction in the voltage V B1 results in a increase in the threshold voltage of the transistor MN 2 , and the increase in the voltage V B2 results in an increase in the threshold voltage of the transistor MP 2 , thereby reducing the level of the bias current I BIAS1 back to the target level. Hence, the transistor MN 5 is used as a ‘replica’ of the transistor MN 2 , to determine the change in the bulk voltage that is required in order to maintain a steady bias current I BIAS1 in response to a change in the supply voltage V DD .

One possible modification to the circuit of FIG. 4 a , is to replace the resistor Ra with another constant current source. Then, the gate-source voltage of the transistor MN 5 is fixed by the voltage developed across the resistor Rb, and the output of the amplifier AMP 1 sets the bulk voltage V B1 so as to maintain both the fixed gate-source voltage and the drain-source current I REF1 of transistor MN 5 .

FIG. 5 shows an alternate circuit to FIG. 4 b for generating the bulk voltage signal V B2 that is applied to the PMOS transistor MP 2 of the amplifier of FIG. 2 . The circuit of FIG. 5 works in a very similar fashion to the circuit of FIG. 4 a , as will be apparent to those skilled in the art. In this embodiment, the same voltage divider formed of resistors Ra and Rb is used to generate the reference voltage for application to the inverting input (−) of both the circuits of FIG. 4 a and the circuit of FIG. 5 . Alternatively, the reference voltages for the circuits of FIG. 4 a and FIG. 5 may be generated separately, for example using two voltage dividers or using two series networks, each comprising a series connected resistor and constant current source.

The mirroring circuit of FIG. 4 b requires less circuit components than the circuit of FIG. 5 , however the mirroring circuit of FIG. 4 b assumes that the characteristics of the NMOS and PMOS transistors are identical, which may not always be the case. Hence, the circuit of FIG. 5 may be used in place of the circuit of FIG. 4 b , in order to give more accurate control over the bulk voltage signal V B2 .

A further embodiment of the invention, wherein the bias current through the two transistors is measured directly, will now be described with reference to FIG. 6 . The circuit 50 shown in FIG. 6 comprises a PMOS transistor MP 3 and NMOS transistor MN 3 that are connected in series between positive and negative supply voltages V DD and GND. Furthermore, a sense resistor R SENSE is connected in series between the transistor MN 3 and the negative supply voltage GND.

The circuit 50 further comprises an amplifier AMP 3 that has one inverting input (−) connected to the sense resistor R SENSE , and one non-inverting input (+) connected to a constant current source I REF3 and a resistor R REF . The output V B3 of the amplifier AMP 3 is connected to the bulk terminal of the transistor MN 3 , and to the input of a mirroring circuit 40 . The output V B4 of the mirroring circuit 40 is connected to the bulk voltage terminal of the transistor MP 3 .

The control circuit of this embodiment is clearly formed of the resistor R SENSE , the amplifier AMP 3 , the mirroring circuit 40 , the resistor R REF , and the constant current source I REF3 .

In use, a bias current I BIAS2 flows through the two transistors MN 3 and MP 3 , and the sense resistor R SENSE . A voltage is developed across the resistor R SENSE in proportion to the level of the bias current I BIAS2 , and this voltage is input to the inverting terminal of the amplifier AMP 3 . The non-inverting terminal of the amplifier AMP 3 is connected to a voltage reference signal that is set according to the level of the constant current source and the value of the resistor R REF , as will be apparent to those skilled in the art. The output V B3 of the amplifier AMP 3 is connected to the input of the mirroring circuit 40 , which mirrors the value of V B3 about V DD /2, to output the signal V B4 =V DD −(V B3 −GND). The mirroring circuit 40 is implemented as shown in FIG. 4 b , except that V B1 is replaced by V B3 , and V B2 is replaced by V B4 .

The output of the amplifier AMP 3 acts to alter the bulk voltages V B3 and V B4 of the transistors MN 3 and MP 3 , so as to alter the transistor's threshold voltages to make the bias current I BIAS2 develop the same voltage across the resistor R SENSE as is developed across the resistor R REF . Hence, the bias current I BIAS2 is maintained at a target level.

For example, if the level of the bias current I BIAS2 begins to increase (e.g. due to an increase in the supply voltage level V DD ), then the voltage developed across the resistor R SENSE will increase. Consequently, the amplifier AMP 3 will decrease its output voltage V B3 , and the mirroring circuit will increase its output voltage V B4 . The decrease in V B3 and the increase in V B4 results in an increase in the threshold voltages of both MN 3 and MP 3 , thereby reducing the bias current I BIAS2 back to the target level.

In this embodiment, the value of the resistor R SENSE is 5 ohm, and the value of the resistor R REF is also 5 ohm.

Therefore, the amplifier AMP 3 controls the transistor bulk voltages V B3 and V B4 to make the level of bias current I BIAS2 the same as the level of current supplied by the constant current source I REF3 . Hence, the target level for the current I BIAS2 may be set by setting the level of the constant current source I REF3 .

The values of the resistors R REF and R SENSE may be individually varied, although the value of the resistor R SENSE is preferable small so that the voltage developed across it does not consume an excessive portion (for example more than 10%) of the supply voltage range, and significantly reduce the output voltage range of the amplifier.

One of the advantages of this embodiment is that it provides a simple control circuit wherein the level of the bias current I BIAS2 can be easily set by setting the value of the constant current source I REF3 .

In summary, there is provided a method and circuit for maintaining a bias current that flows through two transistors at a target level. The two transistors are both connected to form a series network between positive and negative voltage supply terminals. The bias current flows through the two transistors when the circuit is in equilibrium, and the threshold voltage of the transistors is controlled by controlling the voltage that is applied to the transistors bulk terminals. In addition to the two transistors, there is provided a control circuit that measures a circuit parameter that is indicative of the level of the bias current flowing through the two transistors. In response to the measured parameter, the control circuit adjusts the bulk voltage levels of the two transistors so as to alter the transistors threshold voltages and maintain the level of bias current at a target level.

From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of amplifier design, and which may be used instead of, or in addition to, features already described herein. In particular, there are a wide range of alternative control circuits that may be readily devised by those skilled in the art, and which perform the claimed function of measuring a circuit parameter that is indicative of a bias current flowing through two transistors, and altering the transistor bulk voltages so as to maintain the bias current at a target level.

The circuits described in the embodiments all use the ground voltage level for the negative supply voltage, however other voltage levels that are below the supply voltage level V DD may also be used.

Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination.

The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.