Negative lock loop and control method for a flyback voltage converter

The present invention is related generally to a flyback voltage converter and, more particularly, to a negative lock loop and control method for a flyback voltage converter.

FIG. 1 is a circuit diagram of a conventional flyback voltage converter 10 , in which a bridge rectifier 12 rectifies an AC input voltage VAC to produce a DC input voltage VIN, a transformer 16 has a primary winding Lp, a secondary winding Ls and an auxiliary winding La, a power switch SW is serially connected to the primary winding Lp, and a controller 14 switches the power switch SW to convert the DC input voltage VIN into an output voltage VOUT. FIG. 2 is a waveform diagram of the current Is in the secondary winding Ls and the voltage Vds across the secondary winding Ls. FIG. 3 is a waveform diagram of the peak value Is_pk of the current Is and the current conduction time Toff during which the current Is in the secondary winding Ls is greater than zero. Referring to FIGS. 1 and 2 , during the power switch SW is on, for example, from time t 1 to time t 2 in FIG. 2 , a current Ip is generated in the primary winding Lp, the voltage Vds across the secondary winding Ls has a negative value, and there is no current in the secondary winding Ls. At time t 2 , the power switch SW is turned off so that the voltage Vds across the secondary winding Ls changes to be positive and in consequence, the current Is is induced in the secondary winding Ls. Then, as shown by waveform 20 , the current Is decreases slowly until it reaches zero at time t 3 . Assuming that the power switch SW has a switching cycle Ts, the current Is in the secondary winding Ls will have the average value

Io= 0.5 ×Is — pk×T off/ Ts,   [Eq-1]

where Is_pk is the peak value of the current Is. From the equation Eq-1, it is obtained the peak value

Is — pk= 2 ×Io×Ts/T off.  [Eq-2]

Ideally, the output voltage VOUT of the flyback voltage converter 10 is constant, which requires the average current Io be constant and the switching cycle Ts of the power switch SW also be constant. Therefore, it can be known from the equation Eq-2 that the product of the peak value Is_pk and current conduction time Toff of the current Is in the secondary winding Ls is constant, or the peak value Is_pk is in inverse proportion to the current conduction time Toff. As shown in FIG. 3 , the peak value Is_pk decreases as the current conduction time Toff increases.

Therefore, it is desired an approach for rendering the peak value Is_pk being in inverse proportion to the current conduction time Toff.

An object of the present invention is to provide a negative lock loop for a flyback voltage converter.

An object of the present invention is to provide a control method for a flyback voltage converter for controlling the peak value of the current in a secondary winding of the flyback voltage converter being in inverse proportion to a current conduction time of the current in the secondary winding.

According to the present invention, a negative lock loop and control method for a flyback voltage converter adjust the peak value of the current in a secondary winding of the flyback voltage converter according to the current conduction time of the current in the secondary winding, during which the current in the secondary winding is greater than a current threshold, such that the peak value will be in inverse proportion to the current conduction time. The negative lock loop includes a current source, a capacitor, a first switch connected between the current source and capacitor, a second switch parallel connected with the capacitor, a comparator connected to the capacitor, and a logic circuit coupled to the comparator. A first clock switches the first switch such that the current source provides a charging current to charge the capacitor, and a second clock switches the second switch to reset the capacitor. During the current conduction time, the first clock turns on the first switch to charge the capacitor. The comparator compares the voltage of the capacitor with a voltage threshold to generate a comparison signal. The logic circuit adjusts the charging current according to the comparison signal and the first and second clocks such that the charging current is in inverse proportion to the on-time of the first clock. The peak value of the current in the secondary winding is adjusted according to the charging current such that the peak value of the current in the secondary winding is in inverse proportion to the current conduction time.

These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a conventional flyback voltage converter;

FIG. 2 is a waveform diagram of the current in the secondary winding and the voltage across the secondary winding shown in FIG. 1 ;

FIG. 3 is a waveform diagram of the peak value of the current in the secondary winding and the current conduction time during which the current in the secondary winding is greater than zero;

FIG. 4 is a circuit diagram of a negative lock loop according to the present invention for application to the flyback voltage converter shown in FIG. 1 ;

FIG. 5 is a circuit diagram of an embodiment for the charge/discharge logic circuit shown in FIG. 4 ;

FIG. 6 is a timing diagram of a charging process with the charge/discharge control circuit shown in FIG. 4 ;

FIG. 7 is a timing diagram of a discharging process with the charge/discharge control circuit shown in FIG. 4 ;

FIG. 8 is a circuit diagram of another embodiment for the charge/discharge control circuit shown in FIG. 4 ; and

FIG. 9 is a waveform diagram of the charge/discharge control circuit shown in FIG. 8 .

FIG. 4 is a circuit diagram of a negative lock loop 40 according to the present invention for application to the flyback voltage converter 10 shown in FIG. 1 . A charge/discharge control circuit 42 , which includes serially connected current sources 4202 and 4208 and switches 4204 and 4206 , controls the charging and discharging of a capacitor CN 1 according to a charging signal Sc and a discharging signal Sdc, to thereby generate a voltage Vw 1 by the capacitor CN 1 . The current source 4202 and switch 4204 are connected in series between a power source and the capacitor CN 1 , the switch 4206 and current source 4208 are connected in series between the capacitor CN 1 and a ground terminal, and the charging signal Sc and discharging signal Sdc control the switches 4204 and 4206 , respectively. A current source 46 , which includes a voltage-to-current converter 4602 and a current mirror 4604 , generates a charging current ix according to the voltage Vw 1 . The voltage-to-current converter 4602 converts the voltage Vw 1 into a reference current ic, and the current mirror 4604 mirrors the reference current ic to generate the charging current ix. A switch M 4 is connected between the current source 46 and a capacitor CN 2 , and a clock Soff switches the switch M 4 to charge the capacitor CN 2 by the charging current ix. The clock Soff is generated by detecting the current Is in the secondary winding Ls of the flyback voltage converter 10 . When the current Is is greater than zero, as during the current conduction time Toff shown in FIG. 2 , the clock Soff is high and the switch M 4 is turned on accordingly, thereby charging the capacitor CN 2 . A switch M 5 is parallel connected with the capacitor CN 2 , and a clock Son switches the switch M 5 to reset the capacitor CN 2 . When the power switch SW shown in FIG. 1 is on, the clock Son is high and the switch M 5 is turned on accordingly, thereby resetting the capacitor CN 2 . A comparator 48 compares the voltage Vx 1 of the capacitor CN 2 with a voltage threshold VTH to generate a comparison signal CPout. A charge/discharge logic circuit 44 generates the charging signal Sc and discharging signal Sdc according to the comparison signal CPout and the clocks Son and Soff so as to adjust the voltage Vw 1 and thereby the charging current ix, such that the charging current ix will be in inverse proportion to the on-time of the clock Soff. The charging current ix is used to adjust the peak value Is_pk of the current Is in the secondary winding Ls such that the peak value Is_pk is in inverse proportion to the current conduction time Toff.

FIG. 5 is a circuit diagram of an embodiment for the charge/discharge logic circuit 44 , in which an inverter 4402 generates a signal Soff′ according to the clock Soff, an inverter 4404 generates a signal CPout′ according to the comparison signal CPout, an inverter 4406 generates a signal Son′ according to the clock Son, a NAND gate 4408 generates a signal Sna 1 according to the signals Son′, CPout′ and Soff, a NAND gate 4410 generates a signal Sna 2 according to the signals Son′, Soff′ and CPout, and inverters 4412 and 4414 generate the charging signal Sc and discharging signal Sdc according to the signals Sna 2 and Sna 1 , respectively, resulting in the charging signal

Sc=S on′× S off′× CP out,  [Eq-3]

and discharging signal

Sdc=S on′× S off× CP out′.  [Eq-4]

FIG. 6 is a timing diagram of a charging process with the charge/discharge control circuit 42 , in which waveform 50 represents the clock Son, waveform 52 represents the clock Soff, waveform 54 represents the voltage Vx 1 , waveform 56 represents the comparison signal CPout, waveform 58 represents the discharging signal Sdc, and waveform 60 represents the charging signal Sc. Referring to FIGS. 4 and 6 , the clock Son turns to high at time t 4 so that the capacitor CN 2 is reset and in consequence, the voltage Vx 1 becomes zero. At time t 5 , the clock Son turns to low and the clock Soff turns to high, so that the charging current ix begins to charge the capacitor CN 2 , thereby raising the voltage Vx 1 . When the clock Soff turns to low at time t 6 , the charging signal Sc will turn to high if the voltage Vx 1 is below the voltage threshold VTH, thus allowing the current source 4202 to charge the capacitor CN 1 and consequently, the voltage Vw 1 increases and the charging current ix increases accordingly. When the clock Soff turns to low, the voltage Vx 1 will be equal to the voltage threshold VTH. In this embodiment, when the clock Soff turns to low, a latch circuit (not shown in the figure) allows the capacitor CN 2 to continue being charged.

FIG. 7 is a timing diagram of a discharging process with the charge/discharge control circuit 42 , in which waveform 62 represents the clock Son, waveform 64 represents the clock Soff, waveform 66 represents the voltage Vx 1 , waveform 68 represents the comparison signal CPout, waveform 70 represents the discharging signal Sdc, and waveform 72 represents the charging signal Sc. Referring to FIG. 4 and FIG. 7 , the clock Son turns to high at time t 7 so that the capacitor CN 2 is reset, and the voltage Vx 1 becomes zero accordingly. At time t 8 , the clock Son turns to low and the clock Soff turns to high and consequently, the charging current ix begins to charge the capacitor CN 2 and the voltage Vx 1 starts to increase accordingly. When the voltage Vx 1 reaches the voltage threshold VTH, the comparison signal CPout turns to low if the clock Soff has not turned to low, as shown at time t 9 , and thus the discharging signal Sdc turns to high to allow the current source 4208 to discharge the capacitor CN 1 . In consequence, the voltage Vw 1 decreases and the charging current ix is lowered accordingly. The capacitor CN 1 is discharged until the clock Soff turns to low, and when the clock Soff turns to low, the voltage Vx 1 will be equal to the voltage threshold VTH.

FIG. 8 is a circuit diagram of another embodiment for the charge/discharge control circuit 42 . In addition to the serially connected current sources 4202 and 4208 and switches 4204 and 4206 , an OR gate 4226 has a first input receiving the charging signal Sc and a second input receiving the clock Son through a switch 4224 to thereby determine its output to switch the switch 4204 , and a forcing circuit 4210 asserts a signal Sfc when the current conduction time Toff exceeds a time threshold, to turn on the switch 4224 to allow the clock Son passing through the OR gate 4226 to turn on the switch 4204 for a while, thereby preventing a latch condition which might otherwise occur when the capacitor CN 1 is charged for too short a time. In the forcing circuit 4210 , a NOR gate 4212 generates a signal Xnor according to the clocks Son and Soff, a current source 4214 and a switch 4216 are connected in series between a power source and a capacitor CN 3 , a current source 4220 and a switch 4218 are connected in series between the capacitor CN 3 and a ground terminal, the signal Xnor switches the switch 4216 to charge the capacitor CN 3 , the signal Son switches the switch 4218 to discharge the capacitor CN 3 by the current source 4220 , and a comparator 4222 compares the voltage Vy 1 of the capacitor CN 3 with a voltage threshold VTH 2 to generate the signal Sfc.

FIG. 9 is a waveform diagram of the charge/discharge control circuit 42 shown in FIG. 8 , in which waveform 80 represents the clock Soff, waveform 82 represents the clock Son, and waveform 84 represents the signal Xnor. Referring to FIGS. 8 and 9 , as the on-time Toff of the clock Soff is longer, the on-time of the signal Xnor becomes shorter. If the on-time of the signal Xnor is shorter than the on-time of the clock Son, the voltage Vy 1 of the capacitor CN 3 will decrease. When the voltage Vy 1 is below the voltage threshold VTH 2 , the comparator 4222 triggers the signal Sfc to turn on the switch 4224 .

While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.