Magnetic storage device having a buffer track and storage tracks, and method of operating the same

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0022181, filed on Mar. 16, 2009, in the Korean Intellectual Property Office, the entire contents of which is incorporated herein by reference.

1. Field

The general inventive concept relates to information storage devices and methods of operating the same.

2. Description of the Related Art

Non-volatile information storage devices retain recorded information even when power is cut off. Examples of non-volatile information storage devices include hard disk drives (HDDs), non-volatile random access memories (RAMs), etc.

In general, conventional HDDs may wear down and experience operational failure due to a rotating mechanical device included in the HDD. As a result, conventional HDDs have relatively low reliability.

A representative example of a conventional non-volatile RAM is flash memory. Although conventional flash memories do not use a rotating mechanical device, conventional flash memories do have relatively low reading and writing speeds, relatively short lifetimes, and smaller storage capacities relative to conventional HDDs. Also, conventional flash memories have relatively high manufacturing costs.

Another type of information storage device uses movement of a magnetic domain wall of a magnetic material. A magnetic domain is a minute magnetic region formed of a ferromagnetic material, in which magnetic moments are arranged in a given direction. A magnetic domain wall is a border region between magnetic domains having different magnetization directions. The magnetic domain and the magnetic domain wall may be moved by supplying current to the magnetic material. By using the movement of the magnetic domain and the magnetic domain wall, an information storage device having a relatively large storage capacity without the need to use a rotating mechanical device may be realized.

One or more example embodiments provide information storage devices using movement of magnetic domains and magnetic domain walls and methods of operating the same.

One or more example embodiments provide an information storage device including a magnetic structure and a write/read unit. The magnetic structure includes a buffer track and a plurality of storage tracks connected to the buffer track. Each of the buffer track and the plurality of storage tracks include a plurality of magnetic domains and magnetic domain walls between adjacent magnetic domains. The write/read unit is disposed on the magnetic structure. The information storage device according to at least this example embodiment further includes a plurality of switching devices and a circuit. The plurality of switching devices are connected to the buffer track, the storage tracks, and a first end of the write/read unit, respectively. The circuit is configured to control the switching devices and supply current to at least one of the magnetic structure and the write/read unit.

According to at least some example embodiments, the storage tracks may be connected in parallel to an end of the buffer track. The write/read unit may be disposed at an end of the buffer track or a region adjacent to the end of the buffer track. The magnetic structure may include a first magnetic track and at least one second magnetic track connected to the first magnetic track. A first portion of the first magnetic track may correspond to the buffer track. A second portion of the first magnetic track and the at least one second magnetic track may correspond to the plurality of storage tracks. The length of the at least one second magnetic track may be similar to or the same as the length of the first magnetic track. In this example, a central region or a region adjacent to the central region of the at least one second magnetic track may be connected to a central region or a region adjacent to the central region of the first magnetic track. Each of the at least one second magnetic tracks may correspond to two of the plurality of storage tracks.

According to at least some example embodiments, the length of the at least one second magnetic track may be similar to or the same as the length of the buffer track. In this example, an end of the at least one second magnetic track may be connected to a central region or a region adjacent to the central region of the first magnetic track. Each of the at least one second magnetic track may correspond to one of the plurality of storage tracks. The plurality of switching devices may be transistors.

Among the plurality of switching devices, switching devices connected to the buffer track and the plurality of storage tracks may also be connected to a first word line. A switching device connected to the write/read unit may also be connected to a second word line. A plurality of bit lines may intersect the first and second word lines, and may be respectively connected to the plurality of switching devices and a second end of the write/read unit.

According to at least some example embodiments, the circuit may include a first circuit unit connected to the first and second word lines, and a second circuit unit connected to the plurality of bit lines. The second circuit unit may include first through fourth signal generators. The first signal generator may be configured to supply a signal to a bit line connected to a switching device, which is further connected to the buffer track. The second signal generator may be configured to supply a signal to a bit line connected to a switching device, which is further connected to the first end of the write/read unit. The third signal generator may be configured to supply a signal to a bit line connected to the second end of the write/read unit. The fourth signal generator may be configured to supply a signal to bit lines connected to ones of the plurality of switching devices, which are further connected to the plurality of storage tracks.

The second circuit unit may include a selection circuit. The selection circuit may be configured to select a bit line to which a signal is supplied from the fourth signal generator from among the bit lines connected to the plurality of switching devices, which are further connected to the plurality of storage tracks.

The first and second signal generators may be configured to control a read operation performed on a first region of the magnetic structure on which the write/read unit is disposed. The second and third signal generators may be configured to control a write operation performed on the first region. The first and fourth signal generators may be configured to control movement of magnetic domain walls in the magnetic structure.

The first circuit unit may be configured to activate the first and second word lines for the read operation, configured to activate the second word line for the write operation, and configured to activate the first word line for moving the magnetic domain walls.

The first signal generator may include a first interconnecting wire, a first transistor, a second and a third transistor. The first interconnecting wire may be connected to the bit line corresponding to the switching device, which is further connected to the buffer track. The first moving-current source may be connected to the first interconnecting wire. The first transistor may be connected between the first moving-current source and the first interconnecting wire. The second and third transistors may be connected in parallel between the first interconnecting wire and ground. The first signal generator may further include first and second logic gates, and a first inverter. The first logic gate (e.g., an AND gate) may have an output terminal connected to the second transistor, and first and second input terminals. The second logic gate (e.g., an AND gate) may have an output terminal connected to the first transistor, and first and second input terminals. The first and second input terminals are respectively connected to the first and second input terminals of the first logic gate. The first inverter may be connected between the second input terminals of the first and second logic gates. Moving signals for moving the magnetic domain walls may be supplied to the first and second input terminals of the first logic gate, and a read signal may be supplied to a gate terminal of the third transistor.

The second signal generator may include a second interconnecting wire, a read current source, a first write current source, and fourth through sixth transistors. The second interconnecting wire may be connected to the bit line corresponding to the switching device, which is further connected to the write/read unit. The read current source and a first write current source may be connected in parallel to the second interconnecting wire. The fourth transistor may be connected between the read current source and the second interconnecting wire. The fifth transistor may be connected between the first write current source and the second interconnecting wire. The sixth transistor may be connected between the second interconnecting wire and ground. The second signal generator may further include a third and fourth logic gate, and a second inverter. The third logic gate (e.g., an AND gate) may have an output terminal connected to the sixth transistor, and first and second input terminals. The fourth logic gate (e.g., an AND gate) may have an output terminal connected to the fifth transistor, and first and second input terminals respectively connected to the first and second input terminals of the third logic gate. The second inverter may be connected between the second input terminals of the third and fourth logic gates. Write signals may be supplied to the first and second input terminals of the third logic gate, and a read signal may be supplied to a gate terminal of the fourth transistor.

The third signal generator may include a third interconnecting wire, a second write current source, and seventh and eighth transistors. The third interconnecting wire may be connected to the bit line connected to the second end of the write/read unit. The second write current source may be connected to the third interconnecting wire. The seventh transistor may be connected between the second write current source and the third interconnecting wire. The eighth transistor may be connected between the third interconnecting wire and ground. The third signal generator may further include a fifth and sixth logic gates, and a third inverter. The fifth logic gate (e.g., an AND gate) may have an output terminal connected to the seventh transistor, and first and second input terminals. The sixth logic gate (e.g., an AND gate) may have an output terminal connected to the eighth transistor, and first and second input terminals respectively connected to the first and second input terminals of the fifth logic gate. The third inverter may be connected between the first input terminals of the fifth and sixth logic gates. Write signals may be supplied to the first and second input terminals of the fifth logic gate.

The fourth signal generator may include a fourth interconnecting wire, a second moving-current source, and a ninth and a tenth transistor. The fourth interconnecting wire may be connected to the others of the plurality of bit lines corresponding to the switching devices connected to the plurality of storage tracks. The second moving-current source may be connected to the fourth interconnecting wire. The ninth transistor may be connected between the second moving-current source and the fourth interconnecting wire. The tenth transistor may be connected between the fourth interconnecting wire and ground. The fourth signal generator may further include seventh and eighth logic gates and a fourth inverter. The seventh logic gate (e.g., an AND gate) may have an output terminal connected to the ninth transistor, and first and second input terminals. The eighth logic gate (e.g., an AND gate) may have an output terminal connected to the tenth transistor, and first and second input terminals respectively connected to the first and second input terminals of the seventh logic gate. The fourth inverter may be connected between the first input terminals of the seventh and eighth logic gates. Moving signals for moving the magnetic domain walls may be supplied to the first and second input terminals of the seventh logic gate.

The first circuit unit may include a first logic gate and a second logic gate (e.g., OR gates). An output terminal of the first logic gate may be connected to the first word line. An output terminal of the second logic gate may be connected to the second word line. A moving signal and a read signal may be respectively supplied to first and second input terminals of the first logic gate, and a write signal and the read signal may be respectively supplied to first and second input terminals of the second logic gate.

The magnetic structure, the first and second word lines, the plurality of bit lines and the plurality of switching devices may form a unit memory region. A plurality of unit memory regions may form a memory array.

A first decoder may be connected between the first circuit unit and the memory array. A second decoder may be connected between the second circuit unit and the memory array.

Among the plurality of switching devices, a switching device connected to the buffer track may be connected to a first word line, a switching device connected to the write/read unit may be connected to a second word line, and others of the plurality of switching devices, which are connected to the plurality of storage tracks, may be connected to a third word line.

One or more example embodiments provide a method of operating an information storage device. The information storage device includes a magnetic structure and a write/read unit. The magnetic structure includes a buffer track and a plurality of storage tracks connected to the buffer track. Each of the buffer track and the plurality of storage tracks include a plurality of magnetic domains and magnetic domain walls between adjacent magnetic domains. The write/read unit is disposed on the magnetic structure. The information storage device according to at least this example embodiment further includes a plurality of switching devices and a circuit. The plurality of switching devices are connected to the buffer track, the storage tracks, and a first end of the write/read unit, respectively. The circuit is configured to control the switching devices and supply current to at least one of the magnetic structure and the write/read unit.

According to at least this example embodiment, at least one of the plurality of switching devices is activated and current is supplied to at least one of the magnetic structure and the write/read unit. The supplied current may be read current, write current, or moving current for moving the magnetic domain walls of the magnetic structure. The moving current may be supplied between the buffer track and one of the plurality of storage tracks. The plurality of switching devices may be transistors.

Among the plurality of switching devices, switching devices connected to the buffer track and the plurality of storage tracks may be connected to a first word line. A switching device connected to the first end of the write/read unit may be connected to a second word line. A plurality of bit lines may be arranged to intersect the first and second word lines. The plurality of bit lines may be connected to the switching devices and a second end of the write/read unit, respectively.

The circuit may include a first circuit unit connected to the first and second word lines, and a second circuit unit connected to the plurality of bit lines. The second circuit unit may include first through fourth signal generators. The first signal generator may be configured to supply a signal to a bit line connected to the buffer track. The second signal generator may be configured to supply a signal to a bit line connected to a switching device, which is further connected to the first end of the write/read unit. The third signal generator may be configured to supply a signal to a bit line connected to the second end of the write/read unit. The fourth signal generator may be configured to supply a signal to a bit line selected from among the other bit lines connected to switching devices, which are connected to the plurality of storage tracks.

A read operation performed on a first region of the magnetic structure on which the write/read unit is disposed, may be controlled by the first and second signal generators. A write operation performed on the first region may be controlled by the second and third signal generators. Movement of magnetic domain walls of the magnetic structure may be controlled by the first and fourth signal generators.

The first circuit unit may activate the first and second word lines, and the second circuit unit may control a read current to be supplied to the first signal generator from the second signal generator via the write/read unit. The first circuit unit may activate the second word line, and the second circuit unit may control a write current to be supplied from one of the second and third signal generators to the other second or third signal generator via the write/read unit.

The first circuit unit may activate the first word line, the second circuit unit may control a moving current to be supplied from one of the first and fourth signal generators to the other first or fourth signal generator via the magnetic structure, and the moving current may be supplied between the buffer track and one of the storage tracks.

At least one other example embodiment provides an information storage device including a magnetic structure and a first unit. The magnetic structure includes a first magnetic track and at least one second magnetic track. The first magnetic track has a plurality of first magnetic domains and a first magnetic domain wall between each pair of adjacent first magnetic domains. The at least one second magnetic track has a plurality of second magnetic domains and a second magnetic domain wall between each pair of adjacent second magnetic domains. The at least one second magnetic track is arranged one of above or below the first magnetic track and connected to the first magnetic track. The first unit is configured to at least one of read and write information from and to the magnetic structure.

According to at least some example embodiments, the information storage device further includes a plurality switching devices. Each of the plurality of switching devices may be connected to a corresponding one of the first and at least one second magnetic tracks.

A first switching device may be connected between the first unit and a first bit line, and the plurality of switching devices may include second through fifth switching devices. The second switching device may be connected between a first end of the first magnetic track and a second bit line. The third switching device may be connected between a second end of the first magnetic track and a third bit line. The fourth switching device may be connected between a first end of the at least one second magnetic track and a fourth bit line. The fifth switching device may be connected between a second end of the at least one second magnetic track and a fifth bit line. A first word line may be connected to gates of each of the second through fifth switching devices, and a second word line may be connected to a gate of the first switching device.

According to at least some example embodiments, the first magnetic track may include a buffer track and a first storage track, and the at least one second magnetic track may include at least a second and a third storage track. The second and third storage tracks may be part of the same magnetic track. The second storage track may be arranged above the buffer track, and the third storage track may be arranged above the first storage track.

According to at least some example embodiments, the first magnetic track may include a buffer track and a first storage track, and the at least one second magnetic track may include at least a second and a third storage track. The second storage track may be arranged above the first storage track and the third storage track may be arranged below the first storage track.

At least one other example embodiment provides a memory device. The memory device includes a plurality of information storage devices and a control circuit. Each of the information storage devices includes a magnetic structure and a first unit. The magnetic structure includes a first magnetic track and at least one second magnetic track. The first magnetic track has a plurality of first magnetic domains and a first magnetic domain wall between each pair of adjacent first magnetic domains. The at least one second magnetic track has a plurality of second magnetic domains and a second magnetic domain wall between each pair of adjacent second magnetic domains. The at least one second magnetic track is arranged one of above or below the first magnetic track and connected to the first magnetic track. The first unit is configured to at least one of read and write information from and to the magnetic structure. The control circuit is configured to control the plurality of information storage devices.

According to at least some example embodiments, the control circuit may include a row decoder and a column decoder. The row and column decoder may be configured to select an information storage device among the plurality of information storage devices for operation. The control circuit may further include a first peripheral circuit connected to and configured to control the row decoder, and a second peripheral circuit connected to and configured to control the column decoder. The second peripheral circuit may include a plurality of signal generators connected to the column decoder via respective column wires.

According to at least some example embodiments, each of the plurality of information storage devices may further include a plurality switching devices, each of the plurality of switching devices may be connected to a corresponding one of the first and at least one second magnetic tracks.

The general inventive concept will become apparent and more readily appreciated from the following description of example embodiments, taken in conjunction with the accompanying drawings in which:

FIG. 1 is a circuit diagram of an example embodiment of an information storage device;

FIG. 2 is a circuit diagram of another example embodiment of an information storage device;

FIGS. 3A and 3B are cross-sectional views illustrating an example embodiment of a method of writing information by a first unit of an information storage device;

FIGS. 4 to 6 are circuit diagrams illustrating an example embodiment of a method of operating an information storage device;

FIG. 7 is a layout diagram of an example embodiment of an information storage device;

FIG. 8 is a cross-sectional view taken along the line I-I′ of FIG. 7 ;

FIG. 9 is a circuit diagram illustrating an example embodiment of an overall architecture of an information storage device;

FIGS. 10 to 13 are circuit diagrams respectively illustrating an example embodiment of first to fourth signal generators of FIG. 9 ;

FIGS. 14 to 18 are circuit diagrams illustrating another example embodiment of a method of operating an information storage device;

FIG. 19 is a timing diagram of various input signals that may be used when operating an example embodiment of an information storage device; and

FIGS. 20 and 21 are circuit diagrams of other example embodiments of an information storage device.

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown.

Detailed illustrative example embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only the example embodiments set forth herein.

Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or,” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being “formed on,” another element or layer, it can be directly or indirectly formed on the other element or layer. That is, for example, intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly formed on,” to another element, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between,” versus “directly between,” “adjacent,” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an,” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Hereinafter, various example embodiments of an information storage device and a method of operating the same will be described more fully with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals denote like elements throughout the drawings.

FIG. 1 is a circuit diagram of an example embodiment of an information storage device. In FIG. 1 , a first direction indicator ID 1 indicates directions of first and second word lines WL 1 and WL 2 and first through fourth bit lines BL 1 to BL 4 . A second direction indicator ID 2 indicates directions of a magnetic structure MS 1 and a first unit 200 .

Referring to the example embodiment shown in FIG. 1 , the magnetic structure MS 1 includes a plurality of magnetic tracks 100 and 120 connected to one another. As discussed herein, magnetic tracks 100 and 120 are referred to as first magnetic track 100 and second magnetic track 120 . Each of the first and second magnetic tracks 100 and 120 may include a plurality of magnetic domain regions D. A magnetic domain wall region DW is arranged between each pair of adjacent magnetic domain regions D.

The first and second magnetic tracks 100 and 120 may be formed of a ferromagnetic material including at least one of Co, Ni, Fe, or the like. The ferromagnetic material may further include a material other than Co, Ni, and Fe. The length of the first magnetic track 100 may be the same as or similar to that of the second magnetic track 120 . The first and second magnetic tracks 100 and 120 may be arranged in parallel.

In FIG. 1 , the second magnetic track 120 is disposed above the first magnetic track 100 , and a connection layer 110 is disposed between the first and second magnetic tracks 100 and 120 . The connection layer 110 may have the same or substantially the same width as each of the magnetic domain regions D. In the example embodiment shown in FIG. 1 , the connection layer 110 is disposed between center regions or near center regions of the first and second magnetic tracks 100 and 120 . The connection layer 110 may be formed of, but is not limited to, the same material as the first and/or second magnetic tracks 100 and/or 120 . Alternatively, the connection layer 110 may be formed of a material having a magnetic anisotropic energy lower than that of the first and/or second magnetic tracks 100 and/or 120 . Although not shown in FIG. 1 , according to at least some example embodiments, the magnetic structure MS 1 may have three or more magnetic tracks.

Still referring to the example embodiment shown in FIG. 1 , the first unit 200 is disposed on a selected region R 1 of the first magnetic track 100 . In FIG. 1 , the region R 1 is adjacent to the connection layer 110 . Hereinafter, the region R 1 is referred to as ‘first region R 1 ’. The first region R 1 may be one of the plurality of magnetic domain regions D or the leftmost magnetic domain region D of the connection layer 110 . The first region R 1 may be a center region of, or a region adjacent to the center region of, the first magnetic track 100 .

The first unit 200 may be a device for writing/reading information. For example, the first unit 200 may be a device using the tunnel magneto resistance (TMR) effect or the giant magneto resistance (GMR) effect.

In the example embodiment shown in FIG. 1 , the first unit 200 includes a first pinned layer 20 a formed on the bottom surface of the first region R 1 . Although the first pinned layer 20 a is formed on the bottom surface of the first region R 1 in FIG. 1 , the first pinned layer 20 a may be formed on either one of the top and bottom surfaces. The first unit 200 further includes a first separation layer 10 a between the first region R 1 and the first pinned layer 20 a.

Still referring to FIG. 1 , the first unit 200 also includes a second pinned layer 20 b on the top surface of the first region R 1 . Although the second pinned layer 20 b is formed on the top surface of the first region R 1 in FIG. 1 , the second pinned layer 20 b may be formed on either of the top and bottom surfaces of the first region R 1 . A second separation layer 10 b is arranged between the first region R 1 and the second pinned layer 20 b . Magnetization directions of the first pinned layer 20 a and the second pinned layer 20 b may be opposite to each other.

The first and second separation layers 10 a and 10 b may be insulating layers or conductive layers. If the first and second separation layers 10 a and 10 b are insulating layers, the first unit 200 is a TMR device. If the first and second separation layers 10 a and 10 b are conductive layers, the first unit 200 is a GMR device. If the first and second separation layers 10 a and 10 b are conductive layers, a resistive layer (not shown) may be formed between the first and second separation layers 10 a and 10 b and the first region R 1 . The resistive layer may have a higher electrical resistance than the first region R 1 .

Still referring to FIG. 1 , a first electrode 30 a is formed at a bottom surface of the first pinned layer 20 a , and a second electrode 30 b is formed at a top surface of the second pinned layer 20 b . In addition, a free layer (not shown) may also be formed between the first pinned layer 20 a and the first separation layer 10 a and/or between the second pinned layer 20 b and the second separation layer 10 b . In this case, an additional separation layer (not shown) may also be included between the free layer and the corresponding first and/or second pinned layers 20 a and/or 20 b . Although not expressly discussed herein, the first unit 200 may be constructed in various ways.

In the example embodiment shown in FIG. 1 , the region of the first magnetic track 100 located at the left side of the first unit 200 serves as a temporary storage region (e.g., a buffer region BUFFER). The other region (STORAGE 1 ) of the first magnetic track 100 located on the right side of the first unit 200 serves as an effective storage region. The entire second magnetic track 120 may serve as an effective storage region. Said another way, for example, the entire magnetic structure MS 1 , except for the buffer region BUFFER, may serve as an effective storage region. The buffer region BUFFER may occupy half or about half of the first magnetic track 100 . Hereinafter, in FIG. 1 the portion of the first magnetic track 100 located to the right of the first unit 200 is referred to as a ‘first storage region STORAGE 1 ’. Similarly, the right half and the left half of the second magnetic track 120 are referred to herein as a ‘second storage region STORAGE 2 ’ and a ‘third storage region STORAGE 3 ’, respectively. The lengths of the first through third storage regions STORAGE 1 to STORAGE 3 and the buffer region BUFFER may be the same or similar to one another.

According to at least some example embodiments, the magnetic structure MS 1 may have a structure in which the first through third storage regions STORAGE 1 to STORAGE 3 share the buffer region BUFFER. For example, in the magnetic structure MS 1 shown in FIG. 1 , the first through third storage regions STORAGE 1 to STORAGE 3 are connected in parallel to an end of the buffer region BUFFER. The first unit 200 is disposed on an end of or a region adjacent to an end of the buffer region BUFFER.

First through fifth switching devices T 1 to T 5 are connected to ends of the first and second magnetic tracks 100 and 120 , and one end of the first unit 200 . More specifically, in this example embodiment the first switching device T 1 is connected to the buffer region BUFFER, and the second to fourth switching devices T 2 to T 4 are connected to the first through third storage regions STORAGE 1 to STORAGE 3 , respectively. The fifth switching device T 5 is connected to a bottom surface of the first unit 200 . The first to fifth switching devices T 1 to T 5 may be transistors or similar switching devices.

In the example embodiment shown in FIG. 1 , a first word line WL 1 is commonly connected to gates of the first to fourth switching devices T 1 to T 4 . A second word line WL 2 is separated from the first word line WL 1 and connected to a gate of the fifth switching device T 5 . The first and second word lines WL 1 and WL 2 are arranged in parallel with the first and second magnetic tracks 100 and 120 . A plurality of bit lines BL 1 to BL 3 , BL 4 - 1 , BL 4 - 2 and BL 4 - 3 intersect the first and second word lines WL 1 and WL 2 , for example, in the vertical direction.

Still referring to FIG. 1 , the first bit line BL 1 is connected to the first switching device T 1 and the second bit line BL 2 is connected to the fifth switching device T 5 . The third bit line BL 3 is connected to a top surface of the first unit 200 . The fourth bit lines BL 4 - 1 , BL 4 - 2 and BL 4 - 3 are respectively connected to the second to fourth switching devices T 2 to T 4 . The first electrode 30 a of the first unit 200 and the fifth switching device T 5 are connected via a first conducting wire C 1 . The second electrode 30 b of the first unit 200 and the third bit line BL 3 are connected via a second conducting wire C 2 .

The first electrode 30 a may be considered part of the first unit 200 or part of the first conducting wire C 1 . Similarly, the second electrode 30 b may be considered part of the first unit 200 or part of the second conducting wire C 2 .

The positions of the first bit line BL 1 and the fourth bit line BL 4 - 3 may be switched with each other, and those of the fourth bit lines BL 4 - 1 and BL 4 - 2 may be switched with each other. The position of the fifth switching device T 5 may also be changed. For example, the fifth switching device T 5 may be connected to the second electrode 30 b (e.g., the top surface of the first unit 200 ) rather than the first electrode 30 a (e.g., the bottom surface of the first unit 200 ). In this case, the fifth switching device T 5 may be connected to the third bit line BL 3 rather than the second bit line L 2 . In some cases, the first to fifth switching devices T 1 to T 5 may be switching devices (e.g., diodes) other than transistors.

FIG. 2 is a circuit diagram of another example embodiment of an information storage device. The information storage device in FIG. 2 includes a first magnetic track and at least one additional magnetic track.

Referring to FIG. 2 , according to this example embodiment the magnetic structure MS 2 includes a first through third magnetic tracks 100 , 120 a and 120 b . The second and third magnetic tracks 120 a and 120 b are connected to the first magnetic track 100 . The lengths of the second and third magnetic tracks 120 a and 120 b may be less than (e.g., about half of) the length of the first magnetic track 100 .

As shown in FIG. 2 , the second and third magnetic tracks 120 a and 120 b are disposed in parallel with the first magnetic track 100 . For example, in FIG. 2 the second and third magnetic tracks 120 a and 120 b are respectively disposed above and below the first storage region STORAGE 1 . In this case, first ends of the second and third magnetic tracks 120 a and 120 b may be connected to a central region of, or a region adjacent to the central region of, the first magnetic track 100 .

A connection layer 110 a is disposed between the first end of the second magnetic track 120 a and the first magnetic track 100 . A connection layer 110 b is disposed between the first end of the third magnetic track 120 b and the first magnetic track 100 . The connection layers 110 a and 110 b may be the same or substantially the same as the connection layer 110 of FIG. 1 . In the magnetic structure MS 2 , the second and third magnetic tracks 120 a and 120 b are referred to and serve as second and third storage regions STORAGE 2 and STORAGE 3 , respectively.

The magnetic structure MS 2 of FIG. 2 may be differentiated from the magnetic structure MS 1 of FIG. 1 in terms of the position of the third storage region STORAGE 3 .

In an alternative example embodiment, the third storage region STORAGE 3 may be disposed above the second storage region STORAGE 2 . In this alternative embodiment, the third magnetic track 120 b is disposed above the second magnetic track 120 a . Also, the first magnetic track 100 may be connected to three or more magnetic tracks.

Still referring to FIG. 2 , a buffer region BUFFER is connected to a first switching device T 1 . And, the first to third storage regions STORAGE 1 to STORAGE 3 are connected to second to fourth switching devices T 2 to T 4 , respectively. A first unit 200 is connected to a fifth switching device T 5 . The first to fourth switching devices T 1 to T 4 are connected to a first word line WL 1 and the fifth switching device T 5 is connected to a second word line WL 2 .

A plurality of bit lines BL 1 , BL 2 , BL 3 , BL 4 - 1 , BL 4 - 2 , and BL 4 - 3 intersect the first and second word lines WL 1 and WL 2 . The first to fifth switching devices T 1 to T 5 are connected to the bit lines BL 1 , BL 2 , BL 3 , BL 4 - 1 , BL 4 - 2 , and BL 4 - 3 as described above with reference to FIG. 1 , except that the position of the fourth bit line BL 4 - 3 connected to the third storage region STORAGE 3 is changed because the position of the third storage region STORAGE 3 is different than that illustrated in FIG. 1 .

In the example embodiments illustrated in FIGS. 1 and 2 , the first unit 200 includes two pinned layers 20 a and 20 b . But, the first unit 200 may be modified to include a single pinned layer. In this case, one of the pinned layers 20 a and 20 b may be omitted. A separation layer 10 a or 10 b corresponding to the omitted pinned layer 20 a or 20 b may also be omitted. In addition, one of two electrodes 30 a and 30 b (e.g., the second electrode 30 b ) may be disposed on a first region R 1 . A resistive layer (not shown) may be formed between the second electrode 30 b and the first region R 1 . The resistive layer may have a higher electrical resistance than the first magnetic track 100 .

An example embodiment of a method of writing information using the first unit 200 of FIG. 1 will now be described in detail with reference to FIGS. 3A and 3B .

FIGS. 3A and 3B are partial cross-sectional views of the information storage device of FIG. 1 . In FIGS. 3A and 3B , the first and second pinned layers 20 a and 20 b and the first magnetic track 100 have vertical magnetic anisotropy, and the first and second pinned layers 20 a and 20 b are magnetized in a first direction M 1 and a second direction M 2 , respectively. Also, the first and second pinned layers 20 a and 20 b and the first magnetic track 100 have horizontal magnetic anisotropy.

Referring to FIG. 3A , electrons move from the first electrode 30 a to the second electrode 30 b in response to a first write current supplied from the second electrode 30 b to the first electrode 30 a . In so doing, electrons E 1 magnetized in the same direction as the first pinned layer 20 a (e.g., first direction M 1 ) move from the first electrode 30 a to the first region R 1 . The movement of the electrons E 1 allows the first region R 1 to be magnetized in the first direction M 1 . In the second pinned layer 20 b , electrons magnetized in the same direction as the second pinned layer 20 b (e.g., second direction M 2 ) are discharged to the second electrode 30 b via the second pinned layer 20 b . However, electrons E 2 magnetized in a direction opposite to the magnetization direction of the second pinned layer 20 b are not discharged to the second electrode 30 b via the second pinned layer 20 b . Instead, these electrons E 2 return back to, and are accumulated in, the first region R 1 . The movement of the electrons E 2 allows the first region R 1 to be magnetized in the first direction M 1 .

As described above, the first region R 1 may be magnetized in the first direction M 1 by spin transfer torque applied from the first pinned layer 20 a and the second pinned layer 20 b to the first region R 1 . If the first region R 1 is magnetized in the second direction M 2 before the first write current is applied, the magnetization direction of the first region R 1 may change from the second direction M 2 to the first direction M 1 by applying the first write current.

Referring to FIG. 3B , electrons move from the second electrode 30 b to the first electrode 30 a in response to a second write current supplied from the first electrode 30 a to the second electrode 30 b . In so doing, electrons E 3 magnetized in the same direction as the second pinned layer 20 b (e.g., second direction M 2 ) move from the second electrode 30 b to the first region R 1 . The movement of the electrons E 3 allows the first region R 1 to be magnetized in the second direction M 2 . In the first pinned layer 20 a , electrons magnetized in the same direction as the first pinned layer 20 a (e.g., first direction M 1 ) are discharged to the first electrode 30 a via the first pinned layer 20 a . But, electrons E 4 magnetized in a direction opposite to the magnetization direction (e.g., second direction M 2 ) of the first pinned layer 20 a are not discharged to the first electrode 30 a via the first pinned layer 20 a . Instead, the electrons E 4 return back to, and are accumulated in, the first region R 1 . The movement of the electrons E 4 allows the first region R 1 to be magnetized in the second direction M 2 .

If the first region R 1 is magnetized in the first direction M 1 before the second write current is applied, the magnetization direction of the first region R 1 may change from the first direction M 1 to the second direction M 2 by applying the second write current.

As described above, in the information storage device according to at least this example embodiment, the first pinned layer 20 a and the second pinned layer 20 b having opposite magnetization directions are respectively formed on bottom and top surfaces of the first magnetic track 100 . Thus, information may be written by spin transfer torque induced by both the first and second pinned layers 20 a and 20 b . If one of the first and second pinned layers 20 a and 20 b is omitted, information may be written by spin transfer torque applied from the remaining first or second pinned layer 20 a or 20 b to the first region R 1 .

Before, after or between the operations illustrated in FIGS. 3A and 3B , magnetic domains and magnetic domain walls may be moved by one bit within the first magnetic track 100 in a selected direction by applying a current to the first magnetic track 100 . A relatively large amount of information may be written to the first magnetic track 100 by magnetizing a magnetic domain located on the first region R 1 in a desired direction as described above with reference to FIG. 3A or 3 B while moving the magnetic domains and the magnetic domain walls within the first magnetic track 100 in the units of bits.

For example, it is possible to write selected information by moving the magnetic domains and magnetic domain walls in the first storage region STORAGE 1 of FIG. 1 to the buffer region BUFFER. After completing the writing, the information written to the buffer region BUFFER may be moved back to the first storage region STORAGE 1 . Alternatively, it is possible to write selected information by moving the magnetic domains and magnetic domain walls in the second or third storage region STORAGE 2 or STORAGE 3 of FIG. 1 to the buffer region BUFFER. Similarly, after completing the writing, the information written to the buffer region BUFFER may be moved back to the second or third storage region STORAGE 2 or STORAGE 3 ,

In addition to writing, reading may also be performed using the first unit 200 of FIG. 1 . Briefly, the type of information written to the first region R 1 may be determined by supplying a read current to the first unit 200 . In this example, the read current may be supplied between one of the first electrode 30 a and the second electrode 30 b and an end of the first magnetic track 100 . Alternatively, the read current may be supplied between one of the first electrode 30 a and the second electrode 30 b and an end of the second magnetic track 200 . The amount of the read current may vary according to the information written to the first region R 1 including the first unit 200 .

The read current may not be influenced (e.g., greatly influenced) by the state of magnetization of the other magnetic domain regions D except for the first region R 1 . For example, the magnetization state of the first region R 1 including the first unit 200 may be a dominant factor in determining the amount of the read current. Thus, the type of the information written to the first region R 1 may be determined by supplying the read current. A relatively large amount of information written to the magnetic structure MS 1 may be determined by reading the information from the first region R 1 while moving the magnetic domains and the magnetic domain walls by one bit (e.g., bit-by-bit). For example, information may be read from the magnetic domains in the first storage region STORAGE 1 while moving the magnetic domains and magnetic domain walls in the first storage region STORAGE 1 to the buffer region BUFFER. After reading, the information in the buffer region BUFFER may be moved back to the first storage region STORAGE 1 . Alternatively, information may be read from the magnetic domains in the second or third storage region STORAGE 2 or STORAGE 3 while moving the magnetic domains and magnetic domain walls in the second or third storage region STORAGE 2 or STORAGE 3 to the buffer region BUFFER. Similarly, after reading, the information in the buffer region BUFFER may be moved back to the second or third storage region STORAGE 2 or STORAGE 3 .

An example embodiment of a method of operating an information storage device, such as that shown in FIG. 1 , will now be described in greater detail with reference to FIGS. 4 to 6 .

Referring to FIG. 4 , while a fifth switching device T 5 is turned on by activating a second word line WL 2 (e.g., by applying a selected voltage V 2 to the second word line WL 2 ), a write current is supplied to a first unit 200 via a second bit line BL 2 and a third bit line BL 3 . The type of information that is to be written to the first region R 1 may be determined by a direction of the write current.

Referring to FIG. 5 , while first through fourth switching devices T 1 to T 4 are turned on by activating a first word line WL 1 (e.g., by applying a selected voltage V 1 to the first word line WL 1 ), a moving current (pulse current) is supplied to a magnetic structure MS 1 via the first bit line BL 1 and one of fourth bit lines BL 4 - 1 , BL 4 - 2 and BL 4 - 3 . For example, the moving current may be supplied between the fourth bit line BL 4 - 2 and the first bit line BL 1 . In this case, the moving current is supplied between a buffer region BUFFER and a second storage region STORAGE 2 , and magnetic domains and magnetic domain walls move from the second storage region STORAGE 2 to the buffer region BUFFER and vice versa. A direction in which the magnetic domains and magnetic domain walls move within the magnetic structure MS 1 may vary according to the direction of the current. Because current flows in a direction opposite to that in which electrons move, the magnetic domains and the magnetic domain walls move in a direction opposite to that in which the current flows.

By repeatedly and alternately performing the operations described above with reference to FIGS. 4 and 5 , selected information may be written to magnetic domain regions D in the second storage region STORAGE 2 while moving the magnetic domain regions D from the second storage region STORAGE 2 to the buffer region BUFFER. After completing the writing, the information in the buffer region BUFFER may be moved back to the second storage region STORAGE 2 .

Referring to FIG. 6 , to read stored information (or data), a read current is supplied between the first bit line BL 1 and the second bit line BL 2 while the first to fifth switching devices T 1 to T 5 are turned on in response to selected voltages V 1 and V 2 applied to the first and second word lines WL 1 and WL 2 . The read current may flow via a part of the first unit 200 (a lower portion of the first region R 1 ) and the first region R 1 , and the amount of the read current may be influenced (e.g., greatly influenced) by a direction of magnetization of the first region R 1 . For example, an electrical resistance between the first bit line BL 1 and the second bit line BL 2 may change relatively significantly according to the direction of magnetization of the first region R 1 . Thus, the type of information written to the first region R 1 may be determined by applying the read current. The magnitude of the read current is less than that of the above write current, and thus, may not change the direction of magnetization of the first region R 1 . Reading may be performed by supplying a read current between the second bit line BL 2 and one of the fourth bit lines BL 4 - 1 , BL 4 - 2 and BL 4 - 3 rather than by supplying the read current to the first bit line BL 1 and the second bit line BL 2 . Also, if the fifth switching device T 5 is connected to the third bit line BL 3 rather than the second bit line BL 2 , reading may be performed by supplying the read current between the first and third bit lines BL 1 and BL 3 or between the third bit line BL 3 and one of the fourth bit lines BL 4 - 1 , BL 4 - 2 and BL 4 - 3 .

According to at least one example embodiment, information may be read from the first region R 1 by supplying the read current between an end of the first unit 200 and an end of the first and second magnetic tracks 100 and 120 . As described above, in at least this example embodiment, the first unit 200 may be used as a device for reading information. Thus, the first unit 200 may be referred to as a writing/reading unit capable of performing both a write operation and a read operation. Alternatively, a writing unit and a reading unit may be separate units or devices.

The read operation of FIG. 6 and the moving operation of FIG. 5 may be repeatedly and/or alternately performed. In this way, it is possible to read information from magnetic domains located at one side of the first unit 200 while moving these magnetic domain regions D toward the other side of the first unit 200 . For example, information may be read from one of the first to third storage regions STORAGE 1 to STORAGE 3 while moving this information to the buffer region BUFFER. After completing the reading, the information moved to the buffer region BUFFER may be returned back to the original position (e.g., to one of the first to third storage regions STORAGE 1 to STORAGE 3 ).

A write operation and a read operation performed by the information storage device of FIG. 2 may be similar to those performed as described above with reference to FIGS. 4 to 6 . Thus, a detailed description is omitted.

FIG. 7 is a layout diagram of an information storage device according to another example embodiment.

Referring to the example embodiment shown in FIG. 7 , the information storage device includes first through fourth word lines WL 1 to WL 4 . The information storage device also includes a plurality of bit lines BL 1 , BL 2 , BL 3 , BL 4 - 1 , BL 4 - 2 and BL 4 - 3 intersecting the first through fourth word lines WL 1 to WL 4 . A magnetic structure MS 1 is disposed between the first and second word lines WL 1 and WL 2 . The magnetic structure MS 1 includes a first magnetic track 100 and a second magnetic track 120 , similar to the magnetic structure MS 1 illustrated in FIG. 1 .

A first switching device T 1 is disposed at or near a location where the first word line WL 1 intersects the first bit line BL 1 . The first switching device T 1 includes a first source S 1 and a first drain D 1 , which are disposed at respective sides of the first word line WL 1 . The first source S 1 and the first drain D 1 of the first switching device T 1 are respectively connected to the first bit line BL 1 and a first end of the first magnetic track 100 .

A second switching device T 2 is disposed at or near a location where the first word line WL 1 intersects the fourth bit line BL 4 - 1 . The second switching device T 2 includes a second source S 2 and a second drain D 2 , which are disposed at respective sides of the first word line WL 1 . The second source S 2 and the second drain D 2 of the second switching device T 2 are respectively connected to the fourth bit line BL 4 - 1 and a second end of the first magnetic track 100 .

Still referring to the example embodiment shown in FIG. 7 , a third switching device T 3 is disposed at or near a location where the first word line WL 1 intersects the fourth bit line BL 4 - 2 . The third switching device T 3 includes a third source S 3 and a third drain D 3 , which are disposed at respective sides of the first word line WL 1 . The third source S 3 and the third drain D 3 of the third switching device T 3 are respectively connected to the fourth bit line BL 4 - 2 and a first end of the second magnetic track 120 . In this case, the third drain D 3 and the second magnetic track 120 are connected via a third conducting wire C 3 .

A fourth switching device T 4 is disposed at or near a location where the first word line WL 1 intersects the fourth bit line BL 4 - 3 . The fourth switching device T 4 includes a fourth source S 4 and a fourth drain D 4 , which are disposed at respective sides of the first word line WL 1 . The fourth source S 4 and the fourth drain D 4 of the fourth switching device T 4 are respectively connected to the fourth bit line BL 4 - 3 and a second end of the second magnetic track 120 . The fourth drain D 4 and the second magnetic track 120 are connected via a fourth conducting wire C 4 .

Still referring to FIG. 7 , a first unit 200 may be disposed on a selected region (e.g., a central region or a region adjacent to the central region) of the first magnetic track 100 . The second bit line BL 2 is disposed above the first unit 200 and the third bit line BL 3 is spaced apart from the second bit line BL 2 by a given, desired or selected distance.

A fifth switching device T 5 is disposed at or near a location where the second word line WL 2 intersects the second bit line BL 2 . The fifth switching device T 5 has a fifth source S 5 and a fifth drain D 5 , which are disposed at respective sides of the second word line WL 2 . The fifth source S 5 is electrically connected to a bottom surface of the first unit 200 and the fifth drain D 5 is electrically connected to the second bit line BL 2 . A top surface of the first unit 200 is electrically connected to the third bit line BL 3 via a second conducting wire C 2 . The connection between the top surface of the first unit 200 and the third bit line BL 3 and the connection between the bottom surface of the first unit 200 and the fifth source S 5 will be described in more detail later with reference to FIG. 8 .

The functions of the first to fifth sources S 1 to S 5 of the first to fifth switching devices T 1 to T 5 may be respectively switched with those of the first to fifth drains D 1 to D 5 of the first to fifth switching devices T 1 to T 5 .

Each unit memory region MR 1 illustrated in FIG. 7 may correspond to the information storage device of FIG. 1 . Although FIG. 7 illustrates that a plurality of the unit memory regions MR 1 are arranged in the Y-axis direction, a plurality of the unit memory regions MR 1 may be arranged in a matrix in more than one axis direction (e.g., the X-axis and Y-axis directions).

FIG. 8 is a cross-sectional view taken along the line I-I′ of FIG. 7 .

Referring to FIG. 8 , the bottom surface of the first unit 200 is connected to the fifth source S 5 via the first conducting wire C 1 , and the top surface of the first unit 200 is connected to the third bit line BL 3 via the second conducting wire C 2 .

The structures of the information storage device illustrated in FIGS. 7 and 8 are merely illustrative examples. The layout of the information storage device of FIG. 7 may be changed in various ways, and the structure illustrated in FIG. 8 may also change accordingly.

FIG. 9 is a circuit diagram illustrating an overall architecture of an information storage device according to an example embodiment.

In the example embodiment shown in FIG. 9 , a plurality of unit memory regions MR are arranged in a matrix with n rows and m columns. Although FIG. 9 illustrates the unit memory regions MR in a simplified manner, the unit memory regions MR may be constructed as illustrated, for example, in FIG. 1 or 2 . In this example embodiment, reference numerals WL 1 i band WL 2 i respectively denote a first word line and a second word line that are commonly connected to a plurality of unit memory regions MR in an i th row (where i is a natural number, and 1≦i≦n). Reference numerals BL 1 j , BL 2 j , BL 3 j and BL 4 k j respectively denote first through fourth bit lines that are commonly connected to a plurality of unit memory regions MR in a j th column (where j is a natural number, and 1≦j≦m).

The first and second word lines WL i and WL 2 i may respectively correspond to the first and second word lines WL 1 and WL 2 shown in FIG. 1 or 2 . The first to third bit lines BL 1 j to BL 3 j may respectively correspond to the first to third bit lines BL 1 to BL 3 of FIGS. 1 and/or 2 . The fourth bit line BL 4 k j may correspond to the fourth bit lines BL 4 - 1 to BL 4 - 3 in FIG. 1 or 2 . More specifically, for example, the fourth bit line BL 4 k j may correspond to one of the fourth bit lines BL 4 - 1 to BL 4 - 3 .

Still referring to the example embodiment shown in FIG. 9 , a row decoder DCR 1 is commonly connected to the first and second word lines WL 1 1 to WL 1 n and WL 2 1 to WL 2 n . A column decoder DCR 2 is commonly connected to the first to fourth bit lines BL 1 1 to BL 1 m , BL 2 1 to BL 2 m , BL 3 1 to BL 3 m , and BL 4 k 1 to BL 4 k m . A unit memory region MR that is to operate may be selected from among the unit memory regions MR using the row decoder DCR 1 and the column decoder DCR 2 . It would be apparent to those of ordinary skill in the art that the row decoder DCR 1 and the column decoder DCR 2 may include a selection logic device having a multiplexer (MUX) or demultiplexer (DEMUX) structure. Thus, a detailed description of the row decoder DCR 1 and the column decoder DCR 2 will not be provided here.

A first peripheral circuit 1000 is arranged adjacent and connected to a side of the row decoder DCR 1 . The first peripheral circuit 1000 includes at least two logic units (e.g., first and second logic elements LC 1 and LC 2 ). In the example embodiment shown in FIG. 9 , the first and second logic elements LC 1 and LC 2 are OR gates. A first row wire W 1 is connected between the row decoder DCR 1 and an output terminal OUT 1 of the first logic element LC 1 . A second row wire W 2 is connected between the row decoder DCR 1 and an output terminal OUT 2 of the second logic element LC 2 . The first and second row wires W 1 and W 2 may be respectively connected to the first and second word lines WL 1 i and WL 2 i .

In FIG. 9 , IN 11 and IN 12 respectively denote first and second input terminals of the first logic element LC 1 , and IN 21 and IN 22 respectively denote first and second input terminals of the second logic element LC 2 . The first peripheral circuit 1000 further includes a row address circuit AD 1 connected to the row decoder DCR 1 . Although not shown in FIG. 9 , voltage sources may be respectively connected to the first and second logic elements LC 1 and LC 2 .

Still referring to the example embodiment shown in FIG. 9 , a second peripheral circuit 2000 is arranged adjacent and connected to a side of the column decoder DCR 2 .

As shown in FIG. 9 , the second peripheral circuit 2000 includes a plurality of signal generators (e.g., first through fourth signal generators SG 1 to SG 4 ) connected to the column decoder DCR 2 . The first through fourth signal generators SG 1 to SG 4 may be devices for supplying signals to the first through fourth bit lines BL 1 j to BL 4 j of the selected unit memory region MR. Example embodiments of the first through fourth signal generators SG 1 to SG 4 will be described in more detail later.

The first through fourth signal generator SG 1 to SG 4 are connected to the column decoder DCR 2 via first through fourth column wires B 1 to B 4 , respectively. The first through fourth column wires B 1 to B 4 are further respectively connected to the first through fourth bit lines BL 1 j to BL 4 k j . When the fourth bit line BL 4 k j includes three bit lines (e.g., the fourth bit lines BL 4 - 1 to BL 4 - 3 illustrated in FIG. 1 or 2 ), the fourth column wire B 4 may be connected to a bit line selected from among the fourth bit lines BL 4 - 1 to BL 4 - 3 .

A sense circuit or sense amplifier S/A is connected to the second signal generator SG 2 . The sense circuit S/A may be a sense amplifier configured to sense and amplify an information signal read by a selected unit memory region MR. Sense circuits or sense amplifiers such as the sense circuit S/A shown in FIG. 9 are well known in this art and thus a detailed description thereof will not be provided here. The second peripheral circuit 2000 further includes a column address circuit AD 2 and a storage branch address circuit AD 3 (hereinafter referred to as ‘branch address circuit’), which are also connected to the column decoder DCR 2 .

To select a unit memory region MR that is to operate from among the unit memory regions MR, logic operations of the row decoder DCR 1 and the column decoder DCR 2 may be controlled by the row address circuit AD 1 and the column address circuit AD 2 , respectively. After selecting the unit memory region MR, information may be written to or read from the selected unit memory region MR, or magnetic domain walls may be moved by using one of the first and second logic elements LC 1 and LC 2 and at least two signal generators from among the first through fourth signal generators SG 1 to SG 4 . In this case, the fourth bit line BLK 4 j (e.g., one of BL 4 - 1 to BL 4 - 3 in the case of FIG. 1 or 2 ) of the selected unit memory region MR may be selected by using the branch address circuit AD 3 if necessary, where a signal from the fourth column wire B 4 is supplied to the selected fourth bit line BLK 4 j (e.g., one of BL 4 - 1 to BL 4 - 3 in the case of FIG. 1 or 2 ).

Example structures of the first through fourth signal generators SG 1 to SG 4 of FIG. 9 and a method of operating the same will now be described in detail with reference to FIGS. 10 to 13 .

FIG. 10 is a circuit diagram of an example embodiment of the first signal generator SG 1 of FIG. 9 .

Referring to FIG. 10 , in this example embodiment a moving-current source MCS 1 is connected to a first column wire B 1 . A first transistor Tr 1 is connected between the first moving-current source MCS 1 and the first column wire B 1 . A second transistor Tr 2 is connected in series between a lower part of the first column wire B 1 and ground. The first signal generator SG 1 also includes first and second logic gates L 1 and L 2 . The first and second logic elements L 1 and L 2 may be AND gates. An output terminal Out 1 of the first logic element L 1 is connected to a gate of the second transistor Tr 2 , and an output terminal Out 2 of the second logic element L 2 is connected to a gate of the first transistor Tr 1 . A first input terminal In 21 and a second input terminal In 22 of the second logic element L 2 are respectively connected to a first input terminal In 11 and a second input terminal In 12 of the first logic element L 1 . A first inverter IVT 1 for inverting a signal is connected between the second input terminal In 22 of the second logic element L 2 and the second input terminal In 12 of the first logic element L 1 . First and second moving signals S M 1 and S M 2 are respectively supplied to the first and second input terminals In 11 and In 12 of the first logic element L 1 .

Still referring to FIG. 10 , one of the first and second transistors T 1 and T 2 may be turned on in response to the first and second moving signals S M 1 and S M 2 . If both the first and second moving signals S M 1 and S M 2 have a value of 1, the second transistor Tr 2 may be turned on because information ‘1’ is output from the first logic element L 1 , but the first transistor Tr 1 may not be turned on because information ‘0’ is output from the second logic element L 2 . In this case, moving current flows from a selected unit memory region to the first column wire B 1 , then to the second transistor Tr 2 , and finally to ground. If the first and second moving signals S M 1 and S M 2 have values of ‘1’ and ‘0’, respectively, the second transistor Tr 2 may not be turned on because information ‘0’ is output from the first logic element L 1 and the first transistor Tr 1 may be turned on because information ‘1’ is output from the second logic element L 2 . In this case, the moving current flows from the first moving-current source MCS 1 to the first transistor Tr 1 , then to the first column wire B 1 , and finally, to a selected unit memory region. The movement of magnetic domain walls may occur in association with an operation of a fourth signal generator SG 4 , which will later be described.

Still referring to FIG. 10 , the first signal generator SG 1 further includes a third transistor Tr 3 . The third transistor Tr 3 is connected to the first column wire B 1 in parallel with the second transistor Tr 2 such that the second transistor Tr 2 and the third transistor Tr 3 share a source and a drain.

In example operation, a read signal S R 1 is supplied to a gate terminal G 3 of the third transistor Tr 3 . A read operation related to the third transistor Tr 3 may be performed in association with an operation of the second signal generator SG 2 , which will be described in more detail below.

FIG. 11 is a circuit diagram of an example embodiment of the second signal generator SG 2 of FIG. 9 .

Referring to FIG. 11 , in this example embodiment a read current source RCS 1 is connected to a second column wire B 2 . A fourth transistor Tr 4 is connected between the read current source RCS 1 and the second column wire B 2 . A sense circuit S/A is connected to a wire connecting the read current source RCS 1 and the fourth transistor Tr 4 .

In example operation, a read signal S R 1 is supplied to a gate terminal G 4 of the fourth transistor Tr 4 . If the fourth transistor Tr 4 turns on in response to the read signal S R 1 , read current flows from the read current source RCS 1 to a selected unit memory region via the second column wire B 2 . An information signal read from the selected unit memory region is supplied to the sense circuit S/A. Such a read operation may be performed in association with the operation of the above-described first signal generator SG 1 . For example, the read signal S R 1 may be supplied to the gate terminal G 3 of the third transistor Tr 3 of FIG. 10 simultaneously when it is supplied to the gate terminal G 4 of the fourth transistor Tr 4 . In this way, the read current supplied to the selected unit memory region via the second column wire B 2 of FIG. 11 may flow to ground via the first column wire B 1 of FIG. 10 . Thus, a read operation may be performed on the selected unit memory region. During the read operation, a sixth transistor Tr 6 of FIG. 11 , which will be described in more detail later, may be turned off, and thus, the read current may not flow to ground.

Still referring to FIG. 11 , the second signal generator SG 2 further includes a first write current source WCS 1 , which is connected to the second column wire B 2 in parallel with the read current source RCS 1 . A fifth transistor Tr 5 is connected between the first write current source WCS 1 and the second column wire B 2 . A sixth transistor Tr 6 is connected in series between a lower part of the second column wire B 2 and ground. The second signal generator SG 2 further includes third and fourth logic elements L 3 and L 4 , which are connected to each other. The constructions and connections of the third and fourth logic elements L 3 and L 4 and the fifth and sixth transistors Tr 5 and Tr 6 may be similar to those of the first and second logic elements L 1 and L 2 and first and second transistors Tr 1 and Tr 2 of FIG. 10 . Reference numerals In 31 , In 32 and Out 3 respectively denote first and second input terminals and an output terminal of the third logic element L 3 . Reference numerals In 41 , In 42 and Out 4 respectively denote first and second input terminals and an output terminal of the fourth logic element L 4 . A reference numeral IVT 2 denotes a second inverter, which is connected between the second input terminal In 32 and the second input terminal In 42 .

First and second write signals S W 1 and S W 2 may be supplied to the first and second input terminals In 31 and In 32 of the third logic element L 3 . One of the fifth and sixth transistors Tr 5 and Tr 6 may be turned on in response to the first and second write signals S W 1 and S W 2 . If both the first and second write signals S W 1 and S W 2 have a value of 1, the sixth transistor Tr 6 turns on because information ‘1’ is output from the third logic element L 3 , but the fifth transistor Tr 5 is not turned on because information ‘0’ is output from the fourth logic element L 4 . In this case, write current flows from a selected unit memory region to the second column wire B 2 , then to the sixth transistor Tr 6 , and finally to ground. Thus, first information may be written to a first region R 1 , such as shown in FIG. 1 or 2 , of the selected unit memory region.

If the first and second write signals S W 1 and S W 2 respectively have values of 1 and 0, the sixth transistor Tr 6 is not turned on because information ‘0’ is output from the third logic element L 3 , but the fifth transistor Tr 5 is turned on because information ‘1’ is output from the fourth logic element L 4 . In this case, the write current flows from the first write current source WCS 1 to the fifth transistor Tr 5 , then to the second column wire B 2 , and finally to a selected unit memory region. Accordingly, second information may be written to the first region R 1 of the unit memory region. Such a write operation may be performed in association with an operation of the third signal generator SG 3 , which will be described in more detail below.

FIG. 12 is a circuit diagram of an example embodiment of the third signal generator SG 3 of FIG. 9 .

Referring to FIG. 12 , a second write current source WCS 2 is connected to a third column wire B 3 . A seventh transistor Tr 7 is connected between the second write current source WCS 2 and the third column wire B 3 . An eighth transistor Tr 8 is connected in series to a lower part of the third column wire B 3 . One end of the eighth transistor Tr 8 is connected to ground.

The third signal generator SG 3 further includes fifth and sixth logic elements L 5 and L 6 , which are connected to each other. In one example, the fifth and sixth logic elements L 5 and L 6 may be AND gates. An output terminal Out 5 of the fifth logic element L 5 is connected to a gate of the seventh transistor Tr 7 , and an output terminal Out 6 of the sixth logic element L 6 is connected to a gate of the eighth transistor Tr 8 . A first input terminal In 61 of the sixth logic element L 6 is connected to a first input terminal In 51 of the fifth logic element L 5 , and a second input terminal In 62 of the sixth logic element L 6 is connected to a second input terminal In 52 of the fifth logic element L 5 . A third inverter IVT 3 is connected between the first input terminal In 51 of the fifth logic element L 5 and the first input terminal In 61 of the sixth logic element L 6 . First and second write signals Sw 1 and Sw 2 may be respectively supplied to the second and first input terminals In 52 and In 51 of the fifth logic element L 5 .

Referring still to FIG. 12 , if both the first and second write signals S W 1 and S W 2 have a value of 1, the seventh transistor Tr 7 turns on, but the eighth transistor Tr 8 does not turn on. As a result, the write current flows from the second write current source WCS 2 to the seventh transistor Tr 7 , then the third column wire B 3 , and finally to a selected unit memory region. If the first write signal S W 1 has a value of 1 and the second write signal S W 2 has a value of 0, the seventh transistor Tr 7 is not turned on, but the eighth transistor Tr 8 turns on. As a result, the write current flows from the selected unit memory region to the third column wire B 3 , then to the eighth transistor Tr 8 , and finally to ground.

In FIG. 12 , the first and second write signals S W 1 and S W 2 may be respectively equivalent to the first and second write signals S W 1 and S W 2 of FIG. 11 . For example, during a write operation the first and second write signals S W 1 and S W 2 may be supplied to the third signal generator SG 3 of FIG. 12 simultaneously while being supplied to the second signal generator SG 2 of FIG. 11 . In this case, if both the first and second write signals S W 1 and S W 2 have a value of 1, the seventh transistor Tr 7 of FIG. 12 turns on, the sixth transistor Tr 6 of FIG. 11 turns on, and the write current sequentially flows from the second write current source WCS 2 to the seventh transistor Tr 7 , the third column wire B 3 , a selected unit memory region, the second column wire B 2 , the sixth transistor Tr 6 of FIG. 11 , and finally to ground. Thus, first information may be written to a first region R 1 , such as that of FIG. 1 or 2 , of the selected unit memory region.

If the first write signal S W 1 has a value of 1 and the second write signal S W 2 has a value of 0, the eighth transistor Tr 8 of FIG. 12 turns on, the fifth transistor Tr 5 of FIG. 11 turns on, and the write current flows from the first write current source WCS 1 of FIG. 11 to the fifth transistor Tr 5 , the second column wire B 2 , the selected unit memory region, the third column wire B 3 , the eighth transistor Tr 8 , and finally to ground. Accordingly, second information may be written to the first region R 1 of the selected unit memory region.

FIG. 13 is a circuit diagram of an example embodiment of the fourth signal generator SG 4 of FIG. 9 .

Referring to FIG. 13 , a second moving-current source MCS 2 is connected to a fourth column wire B 4 . A ninth transistor Tr 9 is connected between the second write current source WCS 2 and the fourth column wire B 4 . A tenth transistor Tr 10 is connected in series between a lower part of the fourth column wire B 4 and ground. The fourth signal generator SG 4 further includes seventh and eighth logic elements L 7 and L 8 , which are connected to each other. The constructions and connections of the seventh and eighth logic elements L 7 and L 8 and the ninth and tenth transistors Tr 9 and Tr 10 may be similar or substantially similar to those of the fifth and sixth logic elements L 5 and L 6 and seventh and eighth transistors Tr 7 and Tr 8 of FIG. 12 . Reference numerals In 71 , In 72 and Out 7 respectively denote first and second input terminals and an output terminal of the seventh logic element L 7 . Reference numerals In 81 , In 82 and Out 8 respectively denote first and second input terminals and an output terminal of the eighth logic element L 8 . A reference numeral IVT 4 denotes a fourth inverter, which is connected between the first input terminal In 71 and the first input terminal In 81 .

In example operation, first and second moving signals S M 1 and S M 2 may be respectively supplied to the second and first input terminals In 72 and In 71 of the seventh logic element L 7 . If both the first and second moving signals S M 1 and S M 2 have a value of 1, the ninth transistor Tr 9 turns on. As a result, moving current flows from the second moving-current source MCS 2 to the ninth transistor Tr 9 , then to the fourth column wire B 4 , and finally to a selected unit memory region.

If the first and second moving signals S M 1 and S M 2 respectively have values of 1 and 0, the tenth transistor Tr 10 turns on. As a result, the moving current flows from the selected unit memory region to the fourth column wire B 4 , then to the tenth transistor Tr 10 , and finally to ground.

During movement of magnetic domain walls, the fourth signal generator SG 4 of FIG. 13 may operate in association with the first signal generator SG 1 of FIG. 10 . When the ninth transistor Tr 9 is turned on, the third transistor Tr 3 of FIG. 10 is also turned on, and thus, the moving current flows from the second moving-current source MCS 2 to the fourth column wire B 4 , a selected unit memory region, the first column wire B 1 of FIG. 10 , the third transistor Tr 3 , and finally to ground.

Also, when the tenth transistor Tr 10 is turned on the first transistor Tr 1 of FIG. 10 is turned on, and thus, the moving current flows from the first moving-current source MCS 1 of FIG. 10 to the first column wire B 1 , the selected unit memory region, the fourth column wire B 4 , the tenth transistor Tr 10 , and finally to ground. As described above, the fourth column wire B 4 may be connected to one of a plurality of fourth bit lines (e.g., the fourth bit lines BL 4 - 1 to BL 4 - 3 of FIG. 1 or 2 ) of the selected unit memory region. Thus, magnetic domain walls may be moved from one of the first to third storage regions STORAGE 1 to STORAGE 3 of FIG. 1 or 2 to the buffer region BUFFER of FIG. 1 or 2 and vice versa.

After a desired unit memory region MR is selected using the row decoder DCR 1 and the column decoder DCR 2 of FIG. 9 , a write/read operation may be performed on the selected unit memory region MR or the magnetic domain walls may be moved using the first through fourth signal generators SG 1 to SG 4 . In this case, one of a plurality of fourth bit lines (e.g., the fourth bit lines BL 4 - 1 to BL 4 - 3 in the case of FIG. 1 or 2 ) of the selected unit memory region, to which a signal is to be supplied, may be selected using the branch address circuit AD 3 of FIG. 9 if necessary. The write/read operation or the movement of the magnetic domain walls may be performed in association with the operation of the first peripheral circuit 1000 of FIG. 9 . More specifically, during the write/read operation or the movement of the magnetic domain walls, the first moving signal S M 1 and the read signal S R 1 may be respectively supplied to the first and second input terminals IN 11 and IN 12 of the first logic element LC 1 of FIG. 9 , and the first write signal S W 1 and the read signal S R 1 may be respectively supplied to the first and second input terminals IN 21 and IN 22 of the second logic element LC 2 . If the first logic element LC 1 is an OR gate, when at least one of the first moving signal S M 1 and the read signal S R 1 supplied to the first logic element LC 1 has a value of 1, an operation signal may be supplied to the first word line WL 1 i connected to the selected unit memory region via the first row wire W 1 . Thus, the first and second switching devices T 1 and T 2 of FIG. 1 or 2 , which are connected to the first word line WL 1 i of the selected unit memory region, may be turned on.

Similarly, if the second logic element LC 2 is an OR gate, when at least one of the first write signal S W 1 and the read signal S R 1 supplied to the second logic element LC 2 have values of 1, an operation signal may be supplied to the second word line WL 2 i connected to the selected unit memory region via the second row wire W 2 . Thus, the fifth switching device T 5 of FIG. 1 or 2 , which is connected to the second word line WL 2 i of the selected unit memory region, may turn on. The fifth switching device T 5 needs to be turned on in order to write information (see FIG. 4 ). And, the first switching device T 1 and at least one of the second to fourth switching devices T 2 to T 4 need to be turned on in order to move the magnetic domain walls (see FIG. 5 ). The first and fifth switching devices T 1 and T 5 need to be turned on in order to read information (see FIG. 6 ).

The information storage device of FIG. 9 is constructed to satisfy the above operations. For example, when the first write signal S W 1 and the second write signal S W 2 respectively supplied to the second signal generator SG 2 and the third signal generator SG 3 both have a value of 1 to write first information, the first write signal S W 1 having a value of 1 is supplied to the first input terminal IN 21 of the second logic element LC 2 . Thus, the fifth switching device T 5 connected to the second word line WL 2 i connected to the selected unit memory region turns on via the second row wire W 2 .

When the first write signal S W 1 having a value of 1 and the second write signal S W 2 having a value of 0 are respectively supplied to the second signal generator SG 2 and the third signal generator SG 3 to write second information, the first write signal S W 1 having a value of 1 is supplied to the first input terminal IN 21 of the second logic element LC 2 . As a result, the fifth switching device T 5 connected to the second word line WL 2 i connected to the selected unit memory region turns on.

Also, if the read signal S R 1 having a value of 1 is supplied to the first and second signal generators SG 1 and SG 2 to read information, the read signal S R 1 having a value of 1 is supplied to the second input terminals IN 12 and IN 22 of the first and second logic elements LC 1 and LC 2 . Thus, the first to fifth switching devices T 1 to T 5 connected to the first and second word lines WL 1 i and WL 2 i connected to the selected unit memory region are turned on via the first and second row wires W 1 and W 2 . Also, to move the magnetic domain walls in a first direction, when the first moving signal S M 1 and the second moving signal S M 2 having a value of 1 are respectively supplied to the first signal generator SG 1 and the fourth signal generator SG 4 , the first moving signal S M 1 having a value of 1 is supplied to the first input terminal IN 11 of the first logic element LC 1 . Thus, the first to fourth switching devices T 1 to T 4 connected to the first word line WL 1 i connected to the selected unit memory region turns on via the first row wire W 1 . To move the magnetic domain walls in a second direction opposite to the first direction, when the first moving signal S M 1 having a value of 1 and the second moving signal S M 2 having a value of 0 are respectively supplied to the first signal generator SG 1 and the fourth signal generator SG 4 , the first moving signal S M 1 having a value of 1 is supplied to the first input terminal IN 11 of the first logic element LC 1 . Thus, the first to fourth switching devices T 1 to T 4 connected to the first word line WL 1 i connected to the selected unit memory region turn on.

As described above, a write/read operation may be performed on a selected unit memory region by the associated operations of the first and second peripheral circuits 1000 and 2000 .

The above example embodiments of write and read operations are as illustrated in FIGS. 14 through 18 .

FIGS. 14 and 15 illustrate example embodiments of a write operation. FIGS. 16 and 17 illustrate an example embodiment of movement of magnetic domain walls. FIG. 18 illustrates an example embodiment of a read operation. For convenience of explanation, only elements for performing the write and read operation and the movement of the magnetic domain walls are illustrated in FIGS. 14 through 18 .

Referring to FIG. 14 , first and second write signals S W 1 and S W 2 having values of 1 are respectively supplied to second and third signal generators SG 2 and SG 3 . In addition, the first write signal S W 1 having a value of 1 supplied to the first input terminal IN 21 of the second logic element LC 2 . In this case, a seventh transistor Tr 7 of the third signal generator SG 3 , a sixth transistor Tr 6 of the second signal generator SG 2 , and a fifth switching device T 5 of a selected unit memory region turns on. Thus, first write current flows from a second write current source WCS 2 to the seventh transistor Tr 7 , a third column wire B 3 , the selected unit memory region, the second column wire B 2 , the sixth transistor Tr 6 , and finally to ground. Thus, first information is written to a first region R 1 of the selected unit memory region. The principle of writing the first information may be performed as described above with reference to FIG. 3A .

Referring to FIG. 15 , a first write signal S W 1 having a value of 1 and a second write signal S W 2 having a value of 0 are respectively supplied to the second signal generator SG 2 and the third signal generator SG 3 . In addition, the first write signal S W 1 having a value of 1 is supplied to a first input terminal IN 21 of a second logic element LC 2 . In this case, a fifth transistor Tr 5 of the second signal generator SG 2 , an eighth transistor Tr 8 of the third signal generator SG 3 , and a third switching device T 3 of a selected unit memory region turns on. Thus, second write current flows from a first write current source WCS 1 to the fifth transistor Tr 5 , a second column wire B 2 , the selected unit memory region, a third column wire B 3 , the eighth transistor Tr 8 , and finally to ground. Thus, second information is written to a first region R 1 of the selected unit memory region. The principle of writing the second information may be performed as described above with reference to FIG. 3B .

Referring to FIG. 16 , first and second moving signals S M 1 and S M 2 having values of 1 are respectively supplied to first and fourth signal generators SG 1 and SG 4 . In addition, the first moving signal S M 1 having the value of 1 is supplied to the first input terminal IN 11 of the first logic element LC 1 . In this case, a ninth transistor Tr 9 of the fourth signal generator SG 4 , a second transistor Tr 2 of the first signal generator SG 1 , and first to fourth switching devices T 1 to T 4 of a selected unit memory region turn on. Also, one of a plurality of fourth bit lines BL 4 - 1 j to BL 4 - 3 j (e.g., the fourth bit line BL 4 - 2 j ) is selected, and a signal is received from a fourth column wire B 4 via the fourth bit line BL 4 - 2 j . Thus, first moving current flows from a second moving-current source MCS 2 to the ninth transistor Tr 9 , the fourth column wire B 4 , a second storage region STORAGE 2 and a buffer region BUFFER of the selected unit memory region, the first column wire B 1 , the second transistor Tr 2 , and finally to ground. Accordingly, magnetic domain walls of the selected unit memory region move from the buffer region BUFFER to the second storage region STORAGE 2 .

Referring to FIG. 17 , a first moving signal S M 1 having a value of 1 and a second moving signal S M 2 having a value of 0 are respectively supplied to a first signal generator SG 1 and a fourth signal generator SG 4 . In addition, the first moving signal S M 1 having the value of 1 is supplied to a first input terminal IN 11 of a first logic element LC 1 . In this case, a first transistor Tr 1 of the first signal generator SG 1 , a tenth transistor Tr 10 of the fourth signal generator SG 4 , and first to fourth switching devices T 1 to T 4 of a selected unit memory region turn on. Also, one of a plurality of fourth bit lines BL 4 - 1 j to BL 4 - 3 j (e.g., the fourth bit line BL 4 - 2 j ) is selected, and a signal is received from a fourth column wire B 4 via the fourth bit line BL 4 - 2 j . Thus, second moving current flows from a first moving-current source MCS 1 to the first transistor Tr 1 , a first column wire B 1 , a buffer region BUFFER and a second storage region Storage 2 of the selected unit memory region, the fourth column wire B 4 , the tenth transistor Tr 10 , and finally to ground. Accordingly, magnetic domain walls of the first magnetic track 100 move from the second storage region STORAGE 2 to the buffer region BUFFER.

Referring to FIG. 18 , a read signal S R 1 having a value of 1 is supplied to first and second signal generators SG 1 and SG 2 , and the read signal S R 1 having the value of 1 is supplied to first and second logic elements LC 1 and LC 2 . In this case, a fourth transistor Tr 4 of the second signal generator SG 2 , a third transistor Tr 3 of the first signal generator SG 1 , and first to fifth switching devices T 1 to T 5 of a selected unit memory region turn on. Thus, read current flows from a moving-current source RCS 1 to a second column wire B 2 , a first unit 200 of the selected unit memory region, a first column wire B 1 , the third transistor Tr 3 , and finally to ground.

FIG. 19 is a timing diagram of various input signals S R 1 , S W 1 , S W 2 , S M 1 , and S M 2 that may be used when operating information storage devices according to example embodiments. FIG. 19 is also a timing diagram of first through fourth current signals B 1 ′ to B 4 ′, which may flow through the first through fourth column wires B 1 to B 4 of FIG. 9 , respectively. In FIG. 19 , slanted patterns denote signals that may be neglected, and dot patterns denote floating-level signals. These signals of FIG. 19 will now be described with reference to FIGS. 14 through 18 .

Referring to FIG. 19 , in a first read operation, the read signal S R 1 having a value of 1 may be supplied to the information storage device. Thus, the current signal B 2 ′ corresponding to ‘1’ and the current signal B 1 ′ corresponding to ‘0’ may be respectively supplied to a second column wire B 2 and a first column wire B 1 . As a result, read current may flow from the second column wire B 2 to the first column wire B 1 as illustrated in FIG. 18 .

In first movement of magnetic domain walls, the first and second moving signals S M 1 and S M 2 having a value of 1 may be supplied to the information storage device, and thus, the current signal B 1 ′ corresponding to ‘0’ and the current signal B 4 ′ corresponding to ‘1’ may be respectively supplied to the first column wire B 1 and the fourth column wire B 4 . As a result, a first moving current may flow from the fourth column wire B 4 to the first column wire B 1 as illustrated in FIG. 16 .

In a first write operation, the first and second write signals S W 1 and S W 2 having a value of 1 may be supplied to the information storage device, and thus, the current signal B 2 ′ corresponding to ‘0’ and the current signal B 3 ′ corresponding to ‘1’ may be respectively supplied to the second column wire B 2 and the third column wire B 3 . As a result, a first write current may flow from the third column wire B 3 to the second column wire B 2 as illustrated in FIG. 14 .

A second read operation may be performed in a manner similar or substantially similar to the first read operation.

In a second movement of the magnetic domain walls, the first and second moving signals S M 1 and S M 2 respectively having a value of 1 and a value of 0 may be supplied to the information storage device. Thus, the current signal B 1 ′ corresponding to ‘1’ and the current signal B 4 ′ corresponding to ‘0’ may be respectively supplied to the first column wire B 1 and the fourth column wire B 4 . As a result, a second moving current may flow from the first column wire B 1 to the fourth column wire B 4 as illustrated in FIG. 17 .

In a second write operation, the first and second write signals S W 1 and S W 2 respectively having a value of 1 and a value of 0 may be supplied to the information storage device. Thus, the current signal B 2 ′ corresponding to ‘1’ and the current signal B 3 ′ corresponding to ‘0’ may be respectively supplied to the second column wire B 2 and the third column wire B 3 . As a result, a second write current may flow from the second column wire B 2 to the third column wire B 3 as illustrated in FIG. 15 . The signals of FIG. 19 are just illustrative examples and may be changed in various ways.

The above-described information storage devices may be constructed in various ways. For example, although FIGS. 1 and 2 illustrate that the first to fourth switching devices T 1 to T 4 are commonly connected to the first word line WL 1 , the first to fourth switching devices T 1 to T 4 may be divided and connected to at least two word lines in other example embodiments as illustrated in FIGS. 20 and 21 . The information storage devices illustrated in FIG. 20 and FIG. 21 are respectively modified examples of those illustrated in FIGS. 1 and 2 .

Referring to FIGS. 20 and 21 , a first switching device T 1 may be connected to a first word line WL 1 , a fifth switching device T 5 may be connected to a second word line WL 2 , and second to fourth switching devices T 2 to T 4 may be connected to a third word line WL 3 . As the construction of a unit memory region in FIGS. 20 and 21 is different than as illustrated in FIGS. 1 and 2 , those of the first and second peripheral circuits 1000 and 2000 illustrated in FIGS. 9 and 10 through 13 may also be changed and operate differently accordingly.

If at least one second magnetic track 120 , or 120 a and 120 b are connected to a first track 100 to share one buffer region BUFFER by a plurality of storage regions STORAGE 1 to STORAGE 3 as illustrated in FIGS. 1 , 2 , 20 and 21 , then a rate of the buffer region BUFFER that occupies in a magnetic structure MS 1 or MS 2 may be reduced, thereby increasing the storage capacity and/or integration of the information storage device. Also, when a magnetic structure is manufactured by stacking a plurality of magnetic tracks, integration of the information storage device may be increased more easily by increasing the total number of magnetic tracks to be stacked. For example, when the first to fourth switching devices T 1 to T 4 are commonly connected to the first word line WL 1 as illustrated in FIG. 1 or 2 , the integration of the information storage device may be improved (e.g., greatly improved).

It should be understood that the example embodiments described therein should be considered in a descriptive sense only and not for purposes of limitation. For example, it would be obvious to those of ordinary skill in the art that in FIGS. 1 , 2 , 20 and 21 , a plurality of magnetic tracks may be arranged to be apart from one another in a Y-axis rather than a Z-axis and may be connected in various ways. The structure and elements of the first unit 200 may be changed in various ways. Further, the constructions of the first and second peripheral circuits 1000 and 200 illustrated in FIGS. 9 and 13 may be constructed in various ways. Accordingly, the spirit and scope of this disclosure should be defined by the claims.