Apparatus and method for automatic level control

The invention is related to automatic level control, and in particular, to an apparatus and method for a low distortion automatic level control for an audio amplifier.

In audio applications, a power amplifier is usually incorporated to drive a speaker load. The speaker load value typically varies from 4 ohm to 32 ohm. Traditionally, class AB amplifiers have been used to drive the speaker load.

The main drawback of using class AB amplifiers is low efficiency. Low efficiency translates into more power dissipation inside the amplifier which in turn mandates using a (larger) heat sink to dissipate the heat and also lowers the battery life or necessitates a larger and more expensive power supply. This increases the cost and the area of the audio solution.

A class-D amplifier is attractive because of the higher power efficiency compared to a class AB amplifier, which realizes a longer battery life and eliminates the heat sink requirement. This allows design of compact and low cost multi-channel high-power systems. The class D amplifiers partially mitigate the concern of thermal runaway by using transistors as switches.

Class D amplifiers typically employ either pulse-width modulation, pulse density modulation, or sigma-delta modulation. The relatively high frequency carrier signal is modulated by the relatively low frequency audio input signal.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings, in which:

FIG. 1 illustrates a block diagram of a circuit;

FIG. 2 shows a block diagram of an embodiment of the circuit of FIG. 1 ;

FIG. 3 schematically illustrates an embodiment of the circuit of FIG. 2 ;

FIG. 4 shows a block diagram of a differential embodiment of the circuit of FIG. 2 ;

FIG. 5 schematically illustrates an embodiment of the circuit of FIG. 4 ;

FIG. 6 shows a block diagram of another embodiment of the circuit of FIG. 1 ;

FIG. 7 illustrates a functional block diagram of an embodiment of the circuit of FIG. 5 ;

FIG. 8 shows a block diagram of an embodiment of the circuit of FIG. 4 that includes an automatic level control circuit;

FIG. 9 illustrates a block diagram of an embodiment of the circuit of FIG. 8 ;

FIG. 10 shows a schematic diagram of an embodiment of the detection circuit of FIG. 9 ; and

FIG. 11 illustrates a block diagram of a portion of the circuit of FIG. 9 , arranged in accordance with aspects of the invention.

Various embodiments of the present invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. Similarly, the phrase “in some embodiments,” as used herein, when used multiple times, does not necessarily refer to the same embodiments, although it may. As used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based, in part, on”, “based, at least in part, on”, or “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. Where either a field effect transistor (FET) or a bipolar junction transistor (BJT) may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa.

Briefly stated, the invention is related to a circuit and method for automatic level control. The circuit includes an amplifier including a variable resistance circuit that is connected between a first node and a second node. The circuit also includes a first resistance circuit that is connected between a first input node and the first node, and a second resistance circuit that is connected between the first input node and a first op amp node. The first and second resistance circuits are at least approximately linear elements. The circuit also includes an op amp having at least a first input that is connected to the first op amp input node.

FIG. 1 illustrates a block diagram of an embodiment of circuit 100 . Circuit 100 includes amplifier 101 . Amplifier 101 is a variable gain amplifier in which the gain is controlled by control signal CTL. In some embodiment, control signal CTL is a voltage, and amplifier 101 is a voltage controlled amplifier (VCA). In other embodiments, signal CTL is a type of signal other than a voltage, such as a current.

Amplifier 101 includes resistance circuit 111 , resistance circuit 112 , variable resistance circuit 121 , and op amp 130 . As shown in FIG. 1 , variable resistance circuit 121 is coupled between node N 1 and node N 2 . A control input of variable resistance circuit 121 is coupled to node N 5 . First resistance circuit 111 is coupled between node N 1 and node N 3 . Second resistance circuit 112 is coupled between node N 1 and node N 4 . Op amp 130 has at least a first input that is coupled to node N 4 .

Variable resistance circuit 121 is arranged to provide a variable resistance between node N 1 and node N 2 , such that the resistance between nodes N 1 and N 2 varies based on signal CTL provided at node N 5 . In some embodiments, variable resistance circuit 121 is approximately a linear element. For example, in some embodiments, variable resistance circuit 121 consists of one or more MOSFETs biased to operate in the triode region of operation. In some embodiment, node N 2 is coupled to a fixed voltage, or the like.

First resistance circuit 111 is arranged to provide a first fixed equivalent resistance between nodes N 3 and N 1 . First resistance 111 may be a linear element, or approximately a linear element. In one embodiment, resistance circuit 111 consists of a single resistor connected between node N 1 and N 3 . The term “equivalent resistance” is understood to encompass the resistance of the resistor in this case, so that the “equivalent resistance” is the actual resistance in the case where the resistance circuit consists of exactly one resistor. In other embodiments, resistance circuit 111 may include one or more resistors coupled together in series and/or in parallel to provide an equivalent resistance. In other embodiments, resistance circuit 111 may be a transistor bias to operate substantially as a resistor with a fixed resistance.

Second resistance circuit 112 is arranged to provide a second equivalent resistance between nodes N 1 and N 4 . Like first resistance circuit 111 , second resistance circuit 112 may consist of one resistor, two or more resistors coupled together in series and/or in parallel, or the like.

FIG. 2 shows a block diagram of circuit 200 , which may be employed as an embodiment of circuit 100 of FIG. 1 . Amplifier 201 further includes resistance circuit 213 , which is coupled between nodes N 4 and N 6 . Op amp 230 includes a second input that is coupled to node N 2 , and an output that is coupled to node N 6 . Amplifier 200 is arranged to provide amplifier output signal Out, which is based at least in part on the output of op amp 230 . Node N 2 is coupled to a fixed voltage, such as ground or the like.

FIG. 3 schematically illustrates an embodiment of circuit 300 , which may be employed as an embodiment of circuit 200 of FIG. 2 . Op amp 330 has a non-inverting input coupled to node N 2 , an inverting input coupled to node N 4 , and an output coupled to node N 6 . Amplifier 301 is arranged to receive amplifier input voltage Vin at node N 3 , and to provide amplifier output signal Out at node N 6 . Variable resistance circuit 321 includes transistor M 1 , which is biased to operate in the triode region of operation. Resistance circuit 311 includes a resistor having a resistance R 1 . Resistance circuit 312 includes a resistor having a resistance R 2 . Resistance circuit 313 includes a resistor having a resistance A V *(R 1 +R 2 ), where A V is the unmodified voltage gain of amplifier 301 (i.e., the voltage gain when transistor M 1 is substantially an open circuit). Control voltage VC is an embodiment of control signal CTL.

In the embodiment shown, node N 2 is coupled to AC ground. However, in other embodiments, it may be some other DC potential. For example, in some embodiments, VSS=0V, and the voltage at node N 2 is VDD/2.

Amplifier 301 has a gain that varies based on control voltage VC. When equivalent resistance across variable resistance circuit 321 is large, so that it is approximately an open circuit, there is no attenuation, and the gain of amplifier 130 is A V . The lower the resistance across variable resistance circuit 321 , the greater than attenuation, and the smaller the total gain provided by amplifier 301 .

FIG. 4 shows a block diagram of an embodiment of circuit 400 , which may be employed as an embodiment of circuit 200 of FIG. 2 . Amplifier 401 is arranged to provide differential output signal Outd. Op amp 430 includes a first input that is coupled to node N 4 , a second input that is coupled to node N 9 , and first output that is coupled to node N 6 , and a second output that is coupled to node N 7 . Circuit 200 further includes resistance circuit 414 coupled between node N 7 and node N 9 , resistance circuit 415 coupled between node N 8 and node N 2 , and resistance circuit 416 coupled between node N 2 and node N 9 . As previously discussed, in some embodiments, control signal CTL is a control voltage, and amplifier 401 is a voltage controlled amplifier (VCA).

FIG. 5 schematically illustrates an embodiment of circuit 500 , which may be employed as an embodiment of circuit 400 of FIG. 4 . Amplifier 501 is arranged to receive amplifier differential input voltage Vin+/Vin− across nodes N 3 and N 8 , and to provide amplifier output voltage Voutd across nodes N 6 and N 7 . Amplifier output voltage Voutd is an embodiment of amplifier output signal Out. Amplifier output voltage Voutd is a differential voltage that includes voltage Voutp at node N 6 and Voutn at node N 7 . Variable resistance circuit 521 includes transistors M 1 and M 2 , which are each biased to operate in the triode region of operation. Resistance circuits 511 and 515 each include a resistor having a resistance R 1 . Resistance circuits 512 and 516 each include a resistor having a resistance R 2 . Resistance circuits 513 and 514 each include a resistor having a resistance A V *(R 1 +R 2 ), where A V is the unmodified voltage gain of amplifier 501 .

Variable resistance circuit 521 provides a variable resistance 2 *R M1 between nodes N 1 and N 2 , where the equivalent resistance across resistance of transistor M 1 =R M1 , and where the equivalent resistance across transistor M 2 is also substantially equal to R M1 . The variable resistance 2 *R M1 has an attenuating effect on the amplifier output Voutd. Current Iatt is directly proportional to Vin+, and inversely proportional to R M1 . Current Iatt shunts current from R 2 . As R M1 increases in value, Iatt approaches zero. As R M1 approaches infinity, Iatt approaches zero such that I 1 =I 2 (No attenuation). As R M1 decreases in value Iatt approaches I 1 . As R M1 approaches zero, I 2 approaches zero such that Iatt=I 1 (full attenuation). Voltage Voutp=A V I 2 (R 1 +R 2 ) and Voutn=−A V I 2 (R 1 +R 2 ). Current Iatt=Vin+/[R 1 +(R 1 +R 2 )*R M1 /R 2 ]. The total attenuation is 1/(1+[m/(m+1)]*[R 2 /R M1 ]), where m=R 1 /R 2 .

Transistors M 1 and M 2 are MOS transistors biased to operate in the triode region of operation. Accordingly, I PMOS(triode) =ρ p *[(V SG −|V thp |)*V SD −V SD 2 ]. V SD is preferably very small to ensure linearly is achieved (signal integrity). For audio applications, the smaller V SD , the lower the amount of distortion introduced by the transistor. If this approach is taken, then, I PMOS(triode) =β p *[(V SG −|V thp |)*V SD ]. According, R PMOS =V SD /I PMOS =1/[β p *(V SG −|V thp |)]. From this equation, the resistance R PMOS can be changed if the parameters β p , |V thp |, or V SG are changed. Since β p and |V thp | are process parameters that are not changed, this leaves V SG as the lone variable that can be adjusted to either increase or decrease the equivalent resistance R PMOS .

FIG. 6 shows a block diagram of an embodiment of circuit 600 , which may be employed as an embodiment of circuit 100 of FIG. 1 . Amplifier 601 further includes resistance circuit 616 and variable resistance circuit 622 .

FIG. 7 illustrates a functional block diagram of an embodiment of circuit 700 , which may be employed as an embodiment of circuit 500 of FIG. 5 . FIG. 7 illustrates that circuit 500 may be shown functionally as a combination of an amplifier having a voltage gain A V and an attenuator having a gain of 1/(1+[m/(m+1)]*[R 2 /R PMOS ]), where R PMOS is adjusted by adjusted control voltage VC.

FIG. 8 shows a block diagram of an embodiment of circuit 800 , which may be employed as an embodiment of circuit 400 of FIG. 4 . Circuit 800 further includes automatic level control circuit (ALC) 850 .

ALC 850 is arranged to receive differential output voltage Voutd and reference voltage Vref, and to provide control voltage VC. ALC 850 is arranged to automatically reduce the gain of VCA 801 (via control voltage VC) to provide differential output voltage Voutd from exceeding a predetermined level.

In some embodiment, differential input signal Vin is an audio input signal, and differential output voltage Voutd is provided to an audio power amplifier, such as a class D audio power amplifier, class AB audio power amplifier, or the like. In other embodiments, circuit 800 is used in other applications.

ALC 850 is arranged to monitor amplifier output voltage Voutd and make an adjustment to the signal path gain whenever amplifier output voltage Voutd exceeds a reference level associated with reference voltage Vref. If amplifier output voltage Voutd remains below the reference level, the signal path gain is not changed. However, if the Voutd exceeds the reference level, the signal path gain is attenuated by ALC 850 .

In audio applications, it is preferable to ensure that both linearity (as measured by total harmonic distortion [THD]) and sound quality are minimally affected by the signal path gain attenuation. By using MOS transistors arranged in the triode operation, and modulating the resistance of the MOS transistors by controlling the control voltage VC at their gates and biased appropriately, as previously discussed, the linearity needed to keep distortion low and maintain good audio quality is provided. Further, circuit 800 provides a low distortion voltage-controlled amplifier that is controlled via an analog control loop, rather than employing a digital gain step, thereby allowing lower costs and less design complexity.

FIG. 9 illustrates a block diagram of an embodiment of circuit 900 , which may be employed as an embodiment of circuit 800 of FIG. 8 . ALC 950 includes detection circuit 960 , charging circuit 970 , timing capacitor Ctiming, and control voltage generator circuit 980 . Voltage controlled amplifier 901 is arranged to provide amplifier output signal Out from amplifier input voltage Vin, where the gain is adjusted based on control voltage VC. Amplifier input voltage Vin may be either single-ended or differential, and amplifier output signal Out may be either single-ended or differential.

Detection circuit 960 is arranged to determine whether output signal Out exceeds a reference level, and is further arranged to assert detection output signal compOutALC if the determination is positive. In embodiments in which amplifier output signal Out is single-ended, detection circuit 960 may consist of a comparator comparing amplifier output signal Out to the reference level. In embodiments in which amplifier output signal Out is differential, detection circuit 960 may first full-wave rectify amplifier output signal Out.

Charging circuit 970 is arranged to receive signal compOutALC, and is arranged to control charging of timing capacitor Ctiming such that timing capacitor voltage Vcap ramps when signal compOutALC is asserted. Control voltage generator circuit 980 is arranged to provide control voltage VC based on timing capacitor voltage Vcap. Among other things, control voltage generator circuit 980 performs level-shifting, and ensures that control voltage VC does not cause voltage attenuation when compOutALC has not been asserted, but that attenuation begins once compOutALC has been asserted. Control voltage generator circuit 980 may more generically be referred to as a control signal generator circuit, since, as previously discussed, in some embodiment the control signal may be a voltage, and in other embodiment, the control signal may be another type of signal, such as a current.

FIG. 10 shows a schematic diagram of an embodiment of detection circuit 1060 , which may be employed as an embodiment of detection circuit 960 of FIG. 9 . Detection circuit 1060 provides a bandgap voltage across a resistor R 1 to provide a current Vbgap/R 1 , and provides current Vbgap/R 1 to resistor R 2 , to provide a voltage (R 2 /R 1 )*Vbgap. This allows a reference level (R 2 /R 1 )*Vbgap+VDD/2 to be defined, for comparison to the different output voltage Voutd. Differential output voltage Voutd includes Voutp and Voutn. Detection circuit 1060 full-wave rectifies output voltage Voutd, offsets the full-wave rectified output voltage by (R 2 /R 1 )*Vbgap, and compares the offset full-wave rectified output voltage with the common node voltage of Voutp and Voutn (which is Vdd/2) to provide signal compOutALC. This effectively compares the full-wave rectified output voltage with the reference level (R 2 /R 1 )*Vbgap+VDD/2 to provide signal compOutALC, but does so with only one comparator.

FIG. 11 illustrates a block diagram of a portion 1105 of an embodiment of circuit 900 of FIG. 9 . Portion 1105 includes detection circuit 1160 , charging circuit 1180 , and timing capacitor Ctiming. Charging circuit 1180 includes current source Icharge, current source Idischarge, and switch S 1 . Current Icharge is greater than current Idischarge. Switch S 1 is arranged to be closed when signal compOutALC is asserted, and to be open when signal compOutALC is not asserted, so that signal Icharge is provided to timing capacitor Ctiming when signal compOutALC is asserted. When switch S 1 is open, timing capacitor Ctiming is discharged by current Idischarge. When switch S 2 is closed, capacitor Ctiming is charged by a total current of Icharge-Idischarge.

In one embodiment, control voltage generator circuit 980 generates voltage VC from Vcap according to the following equation: VC=VDD/2−0.84*Vcap−V dc — bias . The value 0.84 is a value based on design trade-off between attack time and release time, and may be modified by the desired trade-off accordingly. In its quiescent state, V cap =V in =0V and VC=0.5VDD−V dc — bias (<|V thp |). [V dc — bias is affected by process and temperature. The purpose of V dc — bias is to control attack time and release time. This implies V SGQ =V dc — bias ]. Once the quantity 0.84V cap +V dc — bias >|V thp |, transistors M 1 and M 2 turn on. Initially as V cap increases from 0V, the transistor starts in the subthreshold region and transitions to the linear region (i.e., triode region). In the subthreshold region, a small current flows through transistor M 1 and M 2 having a minimal affect on the signal path gain. When transistors M 1 and M 2 enter the triode region, 0.84V cap +V dc — bias >|V thp |. At this point, the resistance of PMOS is a strong function of the amount of overdrive (Vod=0.84V cap +V dc — bias −|V thp |), and the current is proportional to Vin. As V cap continues to increase beyond this point, the resistance decreases further allowing a larger amount of current to flow through transistor M 1 and M 2 . Beyond a certain V cap value, the gate voltage goes to zero and does not continue to diminish. This is the maximum attenuation point for VCA 901 .

The above specification, examples and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.