Systems and methods for self-testing of integrated devices during production

Embodiments of the present disclosure relate to integrated circuit devices, and more particularly, to the production and testing of the integrated circuit devices.

In the current state of integrated circuit (IC) technology, an IC device will often be tested for defects to ensure the quality and reliability of the IC device. As part of such testing, the IC devices, also referred to as “devices under test” (DUT), may be subject to various test patterns and the DUT's response to the test patterns often under various operating conditions, may determine whether the DUT passes or fails the testing.

Often, the testing is performed by automatic test equipment (ATE) which may require pins to be actually inserted into the IC device. Such procedures can be time-consuming and expensive.

The description in this section is related art, and does not necessarily include information disclosed under 37 C.F.R. 1.97 and 37 C.F.R. 1.98. Unless specifically denoted as prior art, it is not admitted that any description of related art is prior art.

The present disclosure provides a method that includes producing an integrated circuit device configured to include a system on a chip (SOC) and accessing test code within the SOC during the producing. The method further includes self-testing the integrated circuit device with the test code.

The present disclosure also provides an apparatus that includes a system on a chip (SOC) including a processor and memory, and test code stored within the memory of the SOC, the test code for use during a self-test the apparatus during production of the apparatus.

Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

FIG. 1 is a schematic illustration of an integrated circuit (IC) device operatively coupled to an external controller.

FIG. 2 is an operation diagram for generic purpose input/output (GPIO) pins of the IC device of FIG. 1 .

FIG. 3 is a flow chart illustrating a method of self-testing of the IC device of FIG. 1 .

FIG. 4 is a schematic illustration of a power circuit for providing power during self-testing of the IC device of FIG. 1 .

FIG. 5 is a schematic illustration of an arrangement for self-testing of multiple IC devices.

Embodiments of the present disclosure describe systems and methods related to the production and testing of integrated circuit devices. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

The description uses perspective-based descriptions such as up/down, back/front, over/under, and top/bottom. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

For the purposes of the present disclosure, the phrase “A/B” means A or B. For the purposes of the present disclosure, the phrase “A and/or B” means “(A), (B), or (A and B).” For the purposes of the present disclosure, the phrase at least one of A, B, and C″ means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).” For the purposes of the present disclosure, the phrase “(A)B” means “(B) or (AB)” that is, A is an optional element.

The description uses the phrases “in an embodiment,” “in embodiments,” or similar language, which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

The terms chip, die, integrated circuit, integrated circuit device, monolithic device, semiconductor device, and microelectronic device are often used interchangeably in the microelectronics field. The present invention is applicable to all of the above as they are generally understood in the field.

FIG. 1 illustrates a schematic diagram of an integrated circuit (IC) device 100 . The IC device 100 is illustrated as being configured with a system on a chip (SOC) 102 . In general, the IC device may include multiple SOCs 102 . Additionally, the SOC illustrated in FIG. 1 may include additional components as well as multiple components of the same type that are illustrated. For clarity, a single SOC with only a few single components is illustrated.

The SOC 102 includes a processor or central processing unit (CPU) 104 , an instruction static random access memory (I-SRAM) 106 , and a dynamic static random access memory (D-SRAM) 108 . The SOC 102 further includes a read channel 110 , a flash interface 112 , and a DDR interface 114 . The DDR interface 114 communicates with a DDR 116 while the flash interface 112 communicates with a flash memory 118 . In one embodiment, the SOC 102 further includes generic purpose input/output (GPIO) pins 120 .

In one embodiment, the I-SRAM 106 includes test code. The test code can be loaded into the I-SRAM 106 during production of the IC device 100 . When the IC device 100 is ready to for self-testing during the final phases of production, the test code is loaded from the I-SRAM 106 into the CPU 104 . The CPU 104 then executes the test code to thereby run one or more tests on the completed IC device 100 during the final phases of production. The self-testing is initiated by an external controller 130 , which is generally a computing type device such as, for example, a personal computer, that is operated by a user.

In accordance with various embodiments, the SOC 102 includes four GPIO pins 120 . During the self-testing process, one of the four pins is utilized as a reset pin, which an external controller 130 uses to reset the IC device 100 in order to begin self-testing. Another GPIO pin 120 is used as a status pin, which is used to provide the status of the IC device 100 to the external controller 130 . For example, the status pin can let the external controller 130 know that the IC device 100 is ready for self-testing, is in the process of self-testing or is finished with the self-testing. One of the GPIO pins is used to provide data (results of the self-testing) to the external controller 130 . Another GPIO pin is used as an acknowledgement pin with which the external controller 130 communicates with the IC device 100 to inform the IC device 100 that the test results have been received by the external controller 130 .

FIG. 2 provides an example of operation of the four GPIO pins during the self-testing for the IC device 100 as a device under test (DUT). FIG. 2 illustrates four signals—v rst n (reset), STATUS, DATA, and ACK (acknowledgment)—respectively received at the four GPIO pins. At 200 , the reset pin goes high in order to reset the IC device 100 for self-testing. At 202 , the status pin then indicates that the IC device 100 is self-testing by, for example, the status pin being low and the reset pin having gone high. At 204 , when the self-testing is completed, the status pin may so indicate by going high. At 206 , the test results are provided to the external controller 130 via the results pin. At 208 , the external controller 130 then communicates with the IC device 100 to indicate that the test results are being received by sending an acknowledgement via the acknowledgement pin. Once receipt of the test results by the external controller 130 is complete and receipt is acknowledged, the IC device 100 status pin is cleared by going low. The acknowledgement pin then goes low thereby indicating that the handshaking between the IC device 100 and the external controller 130 is complete.

FIG. 3 illustrates one implementation of a method 300 for performing a self-test on an IC device (e.g., the IC device 100 of FIG. 1 ). At 302 , the method 300 begins with a power-up of the IC device 100 . At 304 , the IC device 100 is reset in order to enter a testing mode. At 306 , instructions for the test are downloaded from the I-SRAM 106 into the CPU 104 . At 308 , the IC device 100 is initialized and at 310 , the identification of the IC device 100 is determined. At 312 , the status of the IC device 100 is provided to the external controller 130 . At 314 , the CPU 104 begins self-testing. The self-testing generally includes operating and testing the IC device 100 at a minimum voltage, a nominal voltage, and a maximum voltage. The nominal voltage is generally within plus or minus five percent of the minimum and maximum voltages. Examples of self-testing that may be performed include DDR testing, DLL Window Search and report, Shadow RAM solution calculation, Flash testing, SOC testing and Read Channel Loop Back testing. At 316 , upon completion of the self-testing, the IC device 100 it is determined whether or not the IC device 100 passes. At 318 and 322 , the IC device 100 provides the test results via a GPIO pin to the external controller 130 , which, as previously discussed, acknowledges receipt of the results. At 320 and 324 , the IC device is powered down.

FIG. 4 illustrates a circuit 400 for providing power to an IC device 100 and SOC 102 during self-testing. The circuit 400 includes a regulator 402 and a resistor branch 404 . The resistor branch 404 includes two variable resistors, 406 and 408 . Two shorting branches 410 and 412 are also provided. A ground branch 414 that includes a resistor 416 is also provided. The shorting branches 410 and 412 each include a variable resistor 418 , 420 and a switch 422 , 424 , respectively.

The circuit 400 is useful for providing three levels of a voltage (Vout) to the SOC 102 . When both switches 422 and 424 are open, then the maximum voltage (Vmax) is provided to the SOC 102 as Vout. When both switches 422 and 424 are closed, then a minimum voltage (Vmin) is provided as Vout to the SOC 102 . Finally, when only one switch 422 is closed and the other switch 424 is open, then a nominal voltage (Vnom) is provided as Vout to the SOC 102 . Such an arrangement allows for three different voltages to be provided to the IC device 100 and SOC 102 for various self-testing purposes. GPIO pins 120 of the IC device 100 are used to open and close the switches 422 and 424 . Such an arrangement prevents loss of power to the SOC 102 since the circuit 400 cannot short-out.

FIG. 5 schematically illustrates an arrangement 500 for self-testing of multiple IC devices 100 . The arrangement includes a handler 502 , an external controller 504 , (generally in the form of a personal computer (PC) and similar to external controller 130 as previously described), a power supply 506 and a printed circuit board (PCB) socket board 108 for placement of IC devices 100 as DUTs into out sockets 510 of the PCB socket board 508 .

The handler 502 is generally a robotic arm that places multiple IC devices 100 into the PCB socket board 508 and is generally known in the art. Generally, the handler 502 and PCB socket board 508 are configured to handle 256, 512, 1,024, etc., DUTs at a time.

Once the socket board 508 has been loaded with DUTs, self-testing of the DUTs may begin as has been previously described. Power is provided from the power supply 506 , which may include a circuit 400 as previously described with respect to FIG. 4 . The power is provided to the DUT. As the self-testing is done for each DUT and the results are reported to the external controller 504 , the handler 502 may move the DUTs based upon the test results. The IC devices 100 that pass may be binned into lots for DUTs that have passed, while DUTs that have failed may be binned into lots as IC devices 100 that have failed. After IC devices 100 are removed, they may be replaced by the handler 502 with new IC devices 100 to be tested.

Although certain embodiments have been illustrated and described herein, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments illustrated and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.