Power supply module with power saving mode

1. Technical Field

The present disclosure relates to power supplies and, particularly, to a power supply module with power saving mode.

2. Description of Related Art

Electronic devices powered by a power supply module correspond to rated input voltages. The power supply modules are charged by incoming Alternating Current (AC), and generate Direct Current (DC) voltage to power the electronic devices. The power supply module provides a power supply mode and a power saving mode. When the power supply module is in the power supply mode, DC voltage is supplied to the electronic device. When in the power saving mode, the module hibernates. However, even while hibernating, the power supply module still transmits voltage to the load, constituting waste of power.

Therefore, what is needed is to provide a power supply module which can address the problem described above.

FIG. 1 is a functional block diagram of a power supply module, according to an exemplary embodiment.

FIG. 2 is a partial circuit diagram of the power supply module of FIG. 1 .

Referring to FIG. 1 , a power supply module 100 supplies power received from an external power source 200 , such as a mains power system, to a load 300 when operating in a power supply mode, and inhibiting or stopping supplying of power when the power supply module 100 is operating in a power saving mode. The power supply module 100 includes a rectifying and filtering unit 12 , a power factor correction (PFC) unit 14 , a voltage transforming unit 16 , an input port 17 , a switch unit 18 , and a control unit 20 .

The rectifying and filtering unit 12 is electrically connected between the external power source 200 and the PFC unit 14 , for rectifying an alternating current (AC) voltage from the external power source 200 into a primary direct current (DC) voltage and filtering the primary DC voltage to the PFC unit 14 . The rectifying and filtering unit 12 includes a bridge rectifier and a low-pass filter circuit. The bridge rectifier is configured for providing the rectifying function for the AC voltage and generating the primary DC voltage. The low-pass filter circuit is configured for providing the high-block function for the rectified primary DC voltage.

The PFC unit 14 is configured for correcting a power factor of the filtered primary DC voltage and transmitting the corrected primary DC voltage to the voltage transforming unit 16 . When the PFC unit 14 is powered on, the PFC unit 14 corrects the power factor of the filtered primary DC voltage. When PFC unit 14 is powered off, the PFC unit 14 transmits the filtered primary DC voltage to the voltage transforming unit 16 . In particular, the PFC unit 14 brings voltage and current into phase, such that both can hold on the same level.

The voltage transforming unit 16 is configured for generating a first DC voltage configured for applying power to the load 300 , a second DC voltage configured for applying power to the control unit 20 , and a third DC voltage configured for applying power to the PFC unit 14 . The voltage transforming unit 16 includes a first port 160 , a second port 162 , and a third port 164 . The first port 160 is configured for outputting the first DC voltage, the second port 162 is configured for outputting the second DC voltage, and the third port 164 is configured for outputting the third DC voltage. In one embodiment, the voltage transforming unit 16 is a converter. The voltage transforming unit 16 includes a primary coil, a first secondary coil, a second secondary coil, and a third secondary coil. The first secondary coil, the second secondary coil, and the third secondary coil induct electromotive forces according to the variable current through the primary coil, and generate the first DC voltage, the second DC voltage and the third DC voltage correspondingly.

The input port 17 is configured for receiving a first instruction or a second instruction and generating a first signal or a second signal correspondingly. In this embodiment, the first signal is a high level signal and the second signal is a low level signal. In other embodiments, the first signal can be the low level signal and the second signal can be the high level signal. According to the first instruction, the power supply module 100 is operating in a power supply mode; and according to the second instruction, the power supply module 100 is operating in a power saving mode.

The switch unit 18 is configured for establishing or disconnecting an electrical connection between the first port 160 and the load 300 according to the first signal or the second signal. For example, according to the first signal, the switch unit 18 is switched on to establish the electrical connection between the first port 160 and the load 300 , allowing the first port 160 to apply the first DC voltage to the load 300 . Similarly, according to the second signal, the switch unit 18 is switched off to disconnect the electrical connection between the first port 160 and the load 300 , so as to inhibit or stop applying the first DC voltage to the load 300 .

Further referring to FIG. 2 , the switch unit 18 includes a first transistor Q 1 , a metal oxide semiconductor (MOS) transistor M 1 , a first resistor R 1 , a second resistor R 2 , and a third resistor R 3 . The first transistor Q 1 includes a base, a collector, and an emitter. The MOS transistor M 1 includes a gate, a drain, and a source. In this embodiment, the first transistor Q 1 is a NPN bipolar junction transistor; and the MOS transistor M 1 is an enhancement P type channel MOS transistor. The source of the MOS transistor M 1 is electrically connected to the first port 160 and the drain of the MOS transistor M 1 is electrically connected to the load 300 . The third resistor R 3 is electrically connected between the source and the gate of the MOS transistor M 1 . The second resistor R 2 is electrically connected between the gate of the MOS transistor M 1 and the collector of the first transistor Q 1 . The first resistor R 1 is electrically connected between the base of the first transistor Q 1 and the input port 17 . The emitter of the first transistor Q 1 is electrically grounded.

When the input port 17 generates the first signal in the high level signal, the first transistor Q 1 is conducting, and the collector of the first transistor Q 1 is electrically grounded. The second resistor R 2 and the third resistor R 3 function as divider resistors, so that the first DC voltage from the first port 160 is dividable. For example, the voltage of third resistor R 3 is VR 1 , and the voltage of the gate-source voltage is −VR 1 less than 0V. Thus, the MOS transistor M 1 is conducting, and the first DC voltage of the first port 160 is applied to the load 300 .

When the input port 17 generates the second signal in the low level signal, the first transistor Q 1 is cut off, and the collector-emitter voltage of the first transistor Q 1 is in high impedance. The current through the collector and the emitter of the first transistor Q 1 is small enough that the voltage of the third resistor R 3 is low. As a result, the source-gate voltage cannot conduct the MOS transistor M 1 , and the electrical connection between the first port 160 and the load 300 is disconnected.

The control unit 20 is applied by the second DC voltage from the second port 162 , and is configured for establishing or disconnecting an electrical connection between the third port 164 and the PFC unit 14 according to the first signal or the second signal. For example, when the control unit 20 is applied by the second DC voltage, the control unit 20 allows the third port 164 to apply the third DC voltage to the PFC unit 14 according to the first signal, and the PFC unit 14 corrects the power factor of the filtered primary DC voltage. According to the second signal, the control unit 20 disconnects the electrical connection between the third port 164 and the PFC unit 14 , and the PFC unit 14 powers off the PFC unit 14 . Then the PFC unit 14 functions as a transmission line for transmitting the filtered primary DC voltage to the voltage transforming unit 16 .

The control unit 20 includes a second transistor Q 2 , a filter capacitor C 1 , a third transistor Q 3 , an optical coupler U 1 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , and a seventh resistor R 7 . The second transistor Q 2 includes a base, a collector, and an emitter, as does the third transistor Q 3 . In this embodiment, the second transistor Q 2 is a NPN bipolar junction transistor, the third transistor Q 3 is a PNP bipolar junction transistor. The optical coupler U 1 includes a fourth transistor Q 4 and a light-emitting diode (LED) D 1 . The fourth transistor Q 4 includes a base, a collector, and an emitter. The LED D 1 includes an anode and a cathode. The emitter and the collector of the fourth transistor Q 4 together form the output ports of the optical coupler U 1 , and the anode and the cathode of the LED D 1 together form the input ports of the optical coupler U 1 . The collector of the third transistor Q 3 is electrically connected to the PFC unit 14 . The emitter of the third transistor Q 3 is electrically connected to the third port 164 to be applied by the third DC voltage. The base of the third transistor Q 3 is electrically connected to the emitter of the optical coupler U 1 via the fifth resistor R 5 . The collector of the optical coupler U 1 is electrically grounded. The second port 162 is electrically connected to the anode of the LED D 1 via the sixth resistor R 6 . The cathode of the LED D 1 is electrically connected to the collector of the second transistor Q 2 . The filter capacitor C 1 is electrically connected between the base and the emitter of the second transistor Q 2 . The emitter of the second transistor Q 2 is electrically grounded, and the base of the second transistor Q 2 is electrically connected to the input port 17 via the seventh resistor R 7 .

When the input port 17 generates the first signal in the high level signal, the second transistor Q 2 is conducting, and the second port 162 applies to the LED D 1 via the sixth resistor R 6 . As a result, the LED D 1 is conducting, and the fourth transistor Q 4 of the optical coupler U 1 is conducting. The base-emitter voltage of the third transistor Q 3 is the voltage of the fourth resistor R 4 , and the third transistor Q 3 is conducting. Thus, the third DC voltage applies to the PFC unit 14 , and the PFC unit 14 is powered on.

When the input port 17 generates the second signal in the low level signal, the second transistor Q 2 is cut off. The collector-emitter voltage of the second transistor Q 2 is in high impedance, and the optical coupler U 1 is cut off as the LED D 1 is cut off. Thus, the current through the collector and the emitter of the third second transistor Q 4 , and the voltage of the fourth resistor R 4 are too small to conduct the third transistor Q 3 . The PFC unit 14 is disabled to electrically connect to the third port 164 , and the PFC unit 14 is powered off.

As described, when the input port 17 outputs the second signal, the power supply module 100 is operating in power saving mode, and the switch unit 18 turns off to disconnect the electrical connection between the first port 160 and the load 300 . As a result, the load 300 cannot consume any power in the power saving mode. At the same time, according to the second signal, the control unit 20 directs the voltage transforming unit 16 to stop applying voltage to the PFC unit 14 , and the PFC unit 14 is out of the power factor corrective function to consume any power. Thus, the power supply module 100 further saves power.

It is to be understood, however, that even though numerous has been described with reference to particular embodiments, but the present invention is not limited to the particular embodiments described and exemplified, and the embodiments are capable of considerable variation and modification without departure from the scope of the appended claims.