Circuit for preventing computer power down sequence failure

1. Technical Field

The present disclosure relates to a circuit for preventing a computer power down sequence failure.

2. Description of Related Art

The micro ATX and ATX specifications recommend a 24-pin main connector interface for power supply. This interface incorporates standard ±5V, ±12V, 3.3V, 5V standby, and soft-power signals. Proper implementation of PSON#, 5 VSB, and PG (Power GOOD or Power OK) is required for an ATX-compliant power supply.

During a computer power up sequence, a Southbridge chip of an ATX motherboard receives a PWRBTN# (Power Button) signal and then sends a high level SLP_S3# (S3 Sleep) signal to a PSON# pin of a power connector of an ATX power supply. Then the power supply turns on all of the main power rails including 3.3V, 5V, −5V, 12V, and −12V power rails. After the power rails are powered up and stable, a PG pin of the power connector sends a high level PG signal to the Southbridge. There must be a time delay (100 ms˜500 ms) between the power rails and PG signal to conform to a specified computer power up sequence. After the Southbridge chip receives the high level PG signal, the Southbridge chip sends a reset signal to a CPU. Then, components on the motherboard are all powered up and capable of normally working.

During a computer power down sequence, the PG signal on a PG (Power Good) pin of the Southbridge chip must go to low level before the power rails are powered down. However, the PG signal on the PG (Power Good) pin of the Southbridge chip is often unstable and sometimes does not fall to low level, thereby causing the computer power down sequence to fail.

Therefore, a circuit for quickly setting the PG signal of the Southbridge chip to low level and preventing power down sequence failure is desired.

FIG. 1 illustrates a block diagram of a circuit for preventing a computer power down sequence failure in accordance with the present disclosure.

FIG. 2 illustrates a circuit diagram of the circuit for preventing a computer power down sequence failure in accordance with the present disclosure.

FIG. 3 illustrates a timing diagram explaining the operation of the circuit in FIG. 2 .

Referring to FIG. 1 , an embodiment of a circuit in an electronic device (such as a computer) for preventing the computer power down sequence failure includes a first switching transistor circuit 10 , a second switching transistor circuit 20 , a regulator circuit 30 , and a Southbridge chip 40 . The first switching transistor circuit 10 has an input terminal receiving a power good (PG) signal from a Super I/O chip of a motherboard (not shown). The second switching transistor circuit 20 has an input terminal receiving a S3 sleep (SLP_S3#) signal from the Southbridge chip 40 . The first and second switching transistor circuits 10 , 20 have a common output node connected to an input terminal of the regulator circuit 30 . An output terminal of the regulator circuit 30 is connected to a PG pin of the Southbridge chip 40 .

Referring to FIG. 2 , the first switching transistor circuit 10 includes a first transistor Q 1 and a second transistor Q 2 . The first transistor Q 1 and the second transistor Q 2 are both NPN bipolar transistors. A base terminal B 1 of the first transistor Q 1 is configured to receive the PG signal via a first resistor R 1 , a collector terminal C 1 of the first transistor Q 2 is coupled to a standby signal (+5 VSB) via a second resistor R 2 , and an emitter terminal E 1 of the first transistor Q 1 is connected to ground. A base terminal B 2 of the second transistor Q 2 is connected to the collector terminal C 1 of the first transistor Q 1 , a collector terminal C 2 of the second transistor Q 2 is coupled to a second standby signal (+3.3 VSB) via a third resistor R 3 and connects to the common output node A, and an emitter terminal E 2 of the second transistor Q 2 is connected to ground. The base terminal B 1 is a control terminal of the first transistor Q 1 , and the base terminal B 2 is a control terminal of the second transistor Q 2 . In the embodiment, a signal on the control terminal of the first transistor Q 1 is at an opposite logic level to that on the control terminal of the second transistor Q 2 . Thus, one of the first transistor Q 1 and the second transistor Q 2 is switched on, while another one of the first transistor Q 1 and the second transistor Q 2 is switched off.

The second switching transistor circuit 20 includes a third transistor Q 3 and a fourth transistor Q 4 . The third transistor Q 3 is an NPN bipolar transistor, and the fourth transistor Q 4 is an N-channel enhancement MOSFET. A base terminal B 3 of the third transistor Q 3 is configured to receive the S3 sleep (SLP_S3#) signal via a fourth resistor R 4 , a collector terminal C 3 of the third transistor Q 3 is coupled to a standby signal (+5 VSB) via a fifth resistor R 5 , and an emitter terminal E 3 of the third transistor Q 3 is connected to ground. A gate terminal G of the fourth transistor Q 4 is connected to the collector terminal C 3 of the third transistor Q 3 , a drain terminal D of the fourth transistor Q 4 is coupled to the output node A, and a source terminal S of the fourth transistor Q 4 is connected to ground. The base terminal B 3 is a control terminal of the third transistor Q 3 , and the gate terminal G is a control terminal of the fourth transistor Q 4 . In the embodiment, a signal on the control terminal of the third transistor Q 3 is at an opposite logic level to that on the control terminal of the fourth transistor Q 4 . Thus, one of the third transistor Q 3 and the fourth transistor Q 4 is switched on, while another one of the third transistor Q 3 and the fourth transistor Q 4 is switched off.

The regulator circuit 30 includes a first inverter (NOT gate) U 1 and a second inverter (NOT gate) U 2 serially connected to the first inverter U 1 . Each of the first inverter U 1 and the second inverter U 2 is coupled between a standby power supply (+3.3 VSB) and ground terminal. The first inverter U 1 converts the signal on the node A (from high/low level to low/high level) and outputs a converted signal to the second inverter U 2 . The second inverter U 2 converts the output signal of the first inverter U 1 (from low/high level to high/low level). Thus, the regulator circuit 30 sends out a signal having the same logic level as the signal on the node A. The first inverter U 1 and the second inverter U 2 are capable of generating a square wave signal without any falling/rising delay for regulating the signal on the node A and sending a regulated signal to the PG pin of the Southbridge chip 40 .

Referring to FIG. 3 , during a computer power up sequence, the SLP_S3# signal is set from low to high level. The PSON# signal is set from high to low level. The PG signal is set from low to high level after a time delay T 1 . During the time delay period T 1 , the SLP_S3# signal is at high level, and the PG signal is at low level. The transistor Q 1 is rendered non-conductive, and a collector terminal C 1 of the transistor Q 1 is at high level to render the transistor Q 2 conductive. Thus, the signal on the node A (output PG signal) is connected to ground via the conductive transistor Q 2 and at a low level. During the power up sequence, the PG signal is active and sent to the PG pin of the Southbridge chip 40 , and the output PG signal sent to the Southbridge chip 40 is synchronous with the PG signal and keeps the time delay T 1 for conforming to the power up sequence requirement.

During a computer power down sequence, the SLP_S3# signal is set from high to low level. The PSON# signal is set from low to high level. The PG signal is set from high to low level after a time delay T 2 . During the time delay period T 2 , the SLP_S3# signal has fallen low, and the PG signal is still at high level. The transistor Q 3 is rendered non-conductive, and a collector terminal C 3 of the transistor Q 3 is at high level to render the transistor Q 4 conductive. Thus, the signal on the node A (output PG signal) is connected to ground via the conductive transistor Q 4 and at a low level. During the power down sequence, the SLP_S3# signal is active and sent to the PG pin of the Southbridge chip 40 , and the output PG signal sent to the Southbridge chip 40 is synchronous with the SLP_S3# signal and does not have the time delay T 2 . Thus, a low level output PG signal is quickly sent to the PG pin of the Southbridge chip 40 and the power rails (+5V, +12V, 3.3V, 5V) can be powered down.

In the embodiment, during the computer power down sequence of the electronic device, the S3 sleep (SPL_S3#) signal falls low before than the power good signal, and the S3 sleep signal is active and fed to the power good pin of the Southbridge chip 40 , thereby decreasing a delay time of the power good signal fed to the Southbridge chip 40 and confirming the power down sequence is correct.

While the present disclosure has illustrated by the description preferred embodiments, and while the preferred embodiments have been described in considerable detail, it is not intended to restrict or in any way limit the scope of the appended claims to such details. Additional advantages and modifications within the spirit and scope of the present disclosure will readily appear to those skilled in the art. Therefore, the present disclosure is not limited to the specific details and illustrative examples shown and described.