Control circuit and control method for charge pump circuit

1. Field of the Invention

The present invention relates to a charge pump circuit.

2. Description of the Related Art

Battery-driven electronic devices such as cellular phones, PDAs (Personal Digital Assistants), etc., mount a circuit component which requires higher voltage than the output voltage of a battery (battery voltage). In order to supply a suitable power supply voltage to such a circuit component, a booster circuit such as a charge pump circuit, switching regulator, or the like, is employed.

In a case in which a charge pump circuit is mounted on a battery-driven electronic device, in order to drive such a device for a long time, it is desirable that the charge pump circuit and the control circuit thereof operate with reduced power consumption. Examples of such techniques which have already been proposed include: a technique in which a comparator judges whether or not the output voltage of the charge pump circuit has reached a predetermined voltage, and the frequency generated by an oscillator is switched in a stepwise manner (Patent documents 1 and 2); and a technique in which the driving capacity of a buffer for driving the charge pump is switched according to the output voltage (Patent document 2).

[Patent Document 1]

Japanese Patent Application Laid Open No. 2000-173266

[Patent Document 2]

Japanese Patent Application Laid Open No. 2004-222349

[Patent Document 3]

Japanese Patent Application Laid Open No. H9-293376

[Patent Document 4]

Japanese Patent Application Laid Open No. 2003-217291

[Patent Document 5]

Japanese Patent Application Laid Open No. H11-220872

An arrangement in which the driving state of a charge pump circuit is switched using a comparator has a problem of increased fluctuation of the output voltage. An arrangement in which the number of comparators is increased in order to suppress the fluctuation of the output voltage has another problem of an increased circuit area.

The present invention has been made in order to solve such a problem. It is a general purpose of the present invention to provide a control circuit for a charge pump circuit, which is capable of suppressing fluctuation of the output voltage with reduced power consumption.

An embodiment of the present invention relates to a control circuit for a charge pump circuit. The control circuit includes: a voltage/current conversion circuit which compares a feedback voltage that corresponds to an output voltage of the charge pump circuit with a predetermined reference voltage, and generates a bias current that corresponds to the difference therebetween; an oscillator which oscillates at a frequency that corresponds to the bias current; and a buffer which is biased according to the bias current, and which performs a driving operation by supplying a gate clock to the charge pump circuit based upon a clock signal output from the oscillator.

Such an embodiment is capable of reducing fluctuation of the output voltage in a state in which the output voltage is stabilized at a target value. Furthermore, such an embodiment reduces power consumption by the control circuit.

Also, the voltage/current conversion circuit may include: an output terminal via which the bias current is to be output; a differential amplifier which receives the feedback voltage and the reference voltage via an inverting input terminal and a non-inverting input terminal thereof, respectively, and which is biased by a predetermined reference bias current; an output transistor and an output resistor provided in series between the output terminal and a fixed voltage terminal; and a current source which supplies an auxiliary current to the output terminal according to the reference bias current. Also, the output of the differential amplifier may be input to the control terminal of the output transistor.

Also, the voltage/current conversion circuit may include: an output terminal via which the bias current is to be output; a differential amplifier which receives the feedback voltage and the reference voltage via an inverting input terminal and a non-inverting input terminal thereof, respectively, and which is biased by the predetermined reference bias current; an output transistor and an output transistor provided in series between the output terminal and a fixed voltage terminal; and a current source which supplies a differential current, which is the difference between the reference bias current and a current that corresponds to the result of the differential amplification performed by the differential amplifier, to the output terminal. Also, the output of the differential amplifier may be input to the control terminal of the output transistor.

With each of such voltage/current conversion circuits, the output voltage can be rapidly raised. Furthermore, such an arrangement stabilizes the output voltage around the target value, as well as reducing power consumption.

Also, the voltage/current conversion circuit may reduce the bias current according to an increase in the feedback voltage in a range in which the feedback voltage is smaller than the reference voltage.

Also, in a range in which the feedback voltage is smaller than the reference voltage, the absolute value of the rate of change of the bias current with respect to the feedback voltage may be increased according to an increase in the feedback voltage.

(1) In a first range in which the feedback voltage is a smallest value, the absolute value of the rate of change of the bias current with respect to the feedback voltage may be set to a first value which is approximately constant over this range.

(2) In a second range in which the feedback voltage is greater than the first range, the absolute value of the rate of change of the bias current with respect to the feedback voltage may be set to a second value which is approximately constant over this range and which is greater than the first value.

(3) In a third range in which the feedback voltage is greater than the second range and is smaller than the reference voltage, the absolute value of the rate of change of the bias current with respect to the feedback voltage may be set to a third value which is approximately constant over this range and which is greater than the second value.

Another embodiment of the present invention relates to a power supply circuit. The power supply circuit includes: a charge pump circuit; and any one of the above-described control circuits, which supplies a clock signal to the charge pump circuit so as to drive the charge pump circuit.

Yet another embodiment of the present invention relates to a control method for a charge pump circuit. The control method includes: comparing a feedback voltage that corresponds to an output voltage of the charge pump circuit with a predetermined reference voltage, and generating a bias current that corresponds to the difference therebetween; generating a clock signal with a frequency that corresponds to the bias current; and driving the charge pump circuit by supplying a gate clock to the charge pump circuit based upon the clock signal, using a buffer biased according to the bias current.

It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments.

Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.

Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:

FIG. 1 is a block diagram which shows a configuration of a power supply circuit according to an embodiment;

FIGS. 2A and 2B are circuit diagrams which show the configurations of charge pump circuits;

FIG. 3 is a circuit diagram which shows the configuration of an oscillator and a buffer;

FIGS. 4A and 4B are circuit diagrams which show the example configurations of voltage/current conversion circuits;

FIG. 5 is a diagram which shows the relation between a feedback voltage and a bias voltage in the voltage/current conversion circuits shown in FIGS. 4A and 4B ; and

FIG. 6 is a time chart which shows the operation of the power supply circuit shown in FIG. 1 .

The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.

FIG. 1 is a block diagram which shows a configuration of a power supply circuit 2 according to an embodiment. The power supply circuit 2 includes a charge pump circuit 4 , a voltage divider circuit 6 , and a control circuit 100 .

The control circuit 100 is driven by supplying a gate clock CK 1 and an inverted gate clock CK 1 B to the charge pump circuit 4 . The charge pump circuit 4 boosts the power supply voltage Vdd with a predetermined step-up ratio, and outputs the output voltage Vout. The output voltage Vout is supplied to an unshown load. The voltage divider circuit 6 includes resistors R 1 and R 2 , and divides the output voltage Vout so as to output a feedback voltage VFB according to the output voltage Vout.

The control circuit 100 includes a voltage/current conversion circuit 10 , an oscillator 12 , and a buffer 14 .

The voltage/current conversion circuit 10 compares the feedback voltage VFB with a predetermined reference voltage VREF, and generates a bias current Ib that corresponds to the difference therebetween. The reference voltage VREF is determined according to the target value of the output voltage Vout.

The oscillator 12 oscillates at a frequency that corresponds to the bias current Ib, and outputs a clock signal CK 0 to the buffer 14 .

The buffer 14 is biased by the bias current Ib such that the driving capacity (current supply capacity) can be adjusted. The buffer 14 generates the gate clocks CK 1 and CK 1 B synchronously with the clock signal CK 0 output from the oscillator 12 , thereby driving the charge pump circuit 4 .

FIG. 2A and FIG. 2B are circuit diagrams which show configurations of the charge pump circuit 4 . The charge pump circuit 4 shown in FIG. 2A includes: an input terminal P 1 via which the power supply voltage Vdd is to be input; an output terminal P 2 via which the output voltage Vout is to be output; multiple transistors M 1 through M 5 ; multiple capacitors C 1 through C 4 ; an output capacitor Cout; and a Zener diode ZD.

The multiple transistors M 1 through M 5 are connected in series between the input terminal P 1 and the output terminal P 2 . Each of the transistors M 1 through M 5 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), each of which is arranged with the gate connected to one terminal thereof. One terminal of the i'th capacitor Ci is connected to the other terminal of the corresponding transistor Mi. Each of the transistors Ml through M 5 provides a function as a rectifier component.

The gate clock CK 1 generated by the buffer 14 is supplied to the other terminal of each odd-numbered capacitor C. The inverted gate clock CK 1 B generated by the buffer 14 is supplied to the other terminal of each even-numbered capacitor C. The output capacitor Cout is provided between the output terminal P 2 and the ground terminal. The Zener diode ZD is provided for stabilizing the output voltage Vout. The charge pump circuit 4 boosts the power supply voltage Vdd with a set-up ratio that corresponds to the number of transistors M.

The charge pump circuit 4 shown in FIG. 2B has a configuration in which the transistors M 1 through M 5 are replaced by the diodes D 1 through D 5 .

FIG. 3 is a circuit diagram which shows a configuration of the oscillator 12 and the buffer 14 . The oscillator 12 includes five inverters INV 1 through INV 5 connected in the form of rings. Capacitors C 11 through C 41 , each of which is used to adjust the delay amount for a corresponding inverter stage, are provided to the connection nodes that connect the adjacent inverters. A desired number of inverters INV may be provided.

The i'th inverter INVi includes four transistors MPi 1 , MPi 2 , MNi 2 , and MNi 1 , connected in series between the power supply terminal VDD and the ground terminal VSS. The transistors MPi 1 and MNi 2 are biased such that a current flows therethrough in proportion to the bias current Ib supplied to the bias terminal IB. The oscillation frequency of the oscillator 12 is increased according to an increase in the bias current Ib. In other words, the oscillation frequency is reduced according to a reduction in the bias current Ib.

The buffer 14 includes four inverters INV 6 through INV 9 connected in cascade. Each inverter INV has the same configuration as that of each of the inverters which are components of the oscillator 12 . The first inverter included in the buffer 14 receives the clock signal CK 0 output from the oscillator 12 as an input signal. The gate clock CK 1 is generated by the first and third inverters INV 6 and INV 8 . The inverted gate clock CK 1 B is output by the first, second, and fourth inverters INV 6 , INV 7 , and INV 9 .

The configuration of the oscillator 12 and the buffer 14 is not restricted to that shown in FIG. 3 . For example, description will be made below regarding a modification.

The oscillator 12 may output the clock signal CK 0 and the inverted clock signal CK 0 B. The inverted clock signal CK 0 can be obtained from the output of the even-numbered inverter INV 4 . With such an arrangement, the inverted clock signal CK 0 B obtained from the oscillator 12 may be input to the second inverter INV included in the buffer 14 .

FIG. 4A and FIG. 4B are circuit diagrams which show example configurations of the voltage/current conversion circuit 10 .

The voltage/current conversion circuit 10 shown in FIG. 4A includes a differential amplifier 30 , an output transistor MP 23 , an output resistor R 0 , and a current source 32 . An output terminal IB is provided for outputting a bias current IBO. The differential amplifier 30 receives the feedback voltage VFB and the reference voltage VREF via the inverting input terminal and the non-inverting input terminal thereof, respectively. The transistor MN 10 generates a tail current I 10 according to a predetermined bias current IBIAS.

The output transistor MP 23 and the output resistor R 0 are provided in series between the output terminal IB and a fixed voltage terminal (power supply terminal) VDD. An output signal S 1 of the differential amplifier 30 is input to a control terminal (gate) of the output transistor MP 23 .

The current source 32 supplies an auxiliary current I 22 to the output terminal IB according to the reference bias current IBIAS. The bias voltage IBO obtained by combining the current I 23 that flows through the output transistor MP 23 and the auxiliary current I 22 is output via the output terminal IB, and the bias voltage IBO is supplied to the downstream components, i.e., the oscillator 12 and the buffer 14 .

The voltage/current conversion circuit 10 a shown in FIG. 4B includes a differential amplifier 30 , a current source 33 , an output resistor R 0 , and an output transistor MP 23 .

A first current I 20 that corresponds to the reference bias current IBIAS flows through a transistor MN 20 included in the current source 33 . A current I 13 flows through a transistor MP 13 according to the result of the differential amplification by the differential amplifier 30 . That is to say, the current I 13 flows through the transistor MP 13 according to a current I 11 that flows through a differential transistor MN 11 . A transistor MP 21 is provided on a path for a differential current I 21 (I 20 -I 30 ) which is the difference between the current I 20 and the current I 13 . The control terminal (gate) of the transistor MP 21 is biased by a reference voltage VREF. The current source 33 supplies a current I 22 to an output terminal IB according to the differential current I 21 . A bias current IBO obtained by combining a current I 23 that flows through the output transistor MP 23 and the current I 22 is output via the output terminal IB, and the bias current IBO thus output is supplied to the oscillator 12 and the buffer 14 , which are downstream components.

FIG. 5 is a diagram which shows the relation between the feedback voltage and the bias current in each of the voltage/current conversion circuits shown in FIG. 4A and FIG. 4B . The upper graph shows the feedback voltage VFB and the reference voltage VREF. The middle graph shows the feedback current IFB. The lower graph shows the absolute value of the change (i.e., the differential value) of the feedback current IFB with respect to the feedback voltage VFB.

In the upper, middle, and lower graphs, the horizontal axis represents the bias voltage VFB. The broken line in the middle graph represents the bias current IBO_ 1 generated by the voltage/current conversion circuit 10 shown in FIG. 4A . The solid line in the middle graph represents the bias current IBO_ 2 generated by the voltage/current conversion circuit 10 a shown in FIG. 4B .

The bias current IBO generated by each of the voltage/current conversion circuits shown in FIG. 4A and FIG. 4B has the following features.

The bias current IBO is continuously reduced in the region in which the feedback voltage VFB is lower than the reference voltage VREF.

That is to say, when the feedback voltage VFB is set to the minimum value, the bias current IBO exhibits the maximum value. Furthermore, the bias current IBO is reduced as the feedback voltage VFB approaches the reference voltage VREF. Accordingly, when the output voltage Vout is small immediately after the driving operation of the charge pump circuit 4 is started, the oscillator 12 operates at a high frequency, thereby increasing the driving capacity of the buffer 14 . Thus, such an arrangement is capable of raising the output voltage in a short period of time. As the output voltage Vout approaches the target value, the operating frequency of the oscillator 12 is reduced, which reduces the driving capacity of the buffer 14 , thereby reducing power consumption.

With a conventional technique employing a comparator, the bias current IBO changes substantially in a discontinuous manner. Accordingly, the charge pump circuit 4 is alternately and repeatedly switched between the operating state and the non-operating state. In this case, ripples occur in the output voltage Vout. On the other hand, with the present embodiment employing the voltage/current conversion circuit, the bias current IBO is continuously changed. Thus, such an arrangement prevents ripples from occurring in the output voltage Vout, thereby stabilizing the output voltage Vout around the target value.

As shown in the lower graph in FIG. 5 , the absolute value of the rate of change of the bias current IBO with respect to the feedback voltage VFB is set to an increased value according to an increase in the feedback voltage VFB in the region in which the feedback voltage VFB is smaller than the reference voltage VREF.

The absolute value of the rate of change of the bias current IBO with respect to the feedback voltage VFB can be classified into the following three regions.

(1) In a first region (I) in which the feedback voltage VFB is set to a smallest-value range, the absolute value of the rate of change of the bias current IBO with respect to the feedback voltage VFB is set to a first value which is approximately constant over the first region (I). (2) In a second region (II) in which the feedback voltage VFB therein is greater than that in the first region (I), the absolute value of the rate of change of the bias current IBO with respect to the feedback voltage VFB is set to a second value which is greater than the first value, and which is approximately constant over the second region (II). (3) In a third region (III) in which the feedback voltage VFB therein is greater than that in the second region (II) and is smaller than the reference voltage VREF, the absolute value of the rate of change of the bias current IBO with respect to the feedback voltage VFB is set to a third value which is greater than the second value, and which is approximately constant over the third region (III).

The above is the configuration of the control circuit 100 according to the embodiment. Next, description will be made regarding the operation thereof. FIG. 6 is a time chart which shows the operation of the power supply circuit 2 shown in FIG. 1 . At the point in time t 0 , the control circuit 100 is instructed to start to drive the charge pump circuit 4 . During a period between the points in time t 0 through t 1 , the output voltage Vout rapidly rises up to the target value Vcp (=5 V). As the output voltage Vout rises, the bias current IBO is reduced. After the output voltage Vout reaches the target value, the charge pump circuit 4 enters the stable state. In the stable state, the charge pump circuit 4 is driven at a very low frequency and with very small driving capacity. As a result, such an arrangement is capable of supplying reduced power consumption, as well as a stable output voltage Vout.

While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.