Method and system of finding a read voltage for a flash memory

1. Field of the Invention

The present invention generally relates to a flash memory, and more particularly to a method and system of finding an optimal read voltage for a flash memory.

2. Description of the Prior Art

Flash memory is a non-volatile solid state memory device that can be electrically erased and reprogrammed, and is a specific type of electrically erasable programmable read-only memory (EEPROM) device. Conventional flash memory stores a single bit of information in each memory cell such that each memory cell can be programmed to assume two possible states. The conventional flash memory is thus commonly referred to as single-level cell (SLC) flash memory or single-bit cell (SBC) flash memory. Modern flash memory is capable of storing two or more bits of information in each memory cell such that each memory cell can be programmed to assume more than two possible states. The modern flash memory is thus commonly referred to as multi-level cell (MLC) flash memory or multi-bit cell (MBC) flash memory.

In the MLC flash memory, data of different state are programmed to the flash memory by storing different amount of charge in the floating gate of the flash memory. As the charge in the floating gate specifically determines the corresponding threshold voltage, the data can then be read from the MLC flash memory according to their different threshold voltage. Due to variations among the memory cells during the manufacture, operation or according to other factors, the threshold voltage of each state is not a constant value but a range. When the flash memory is being read, the threshold voltage of a cell is compared to read voltages to determine its state.

The read voltages for reading data from the traditional MLC flash memory are constant. In practice, however, the threshold voltage distribution may probably change after the flash memory has been subjected to a predetermined number of program/erase cycles or/and a predetermined data retention time has elapsed. For example, as shown in FIG. 1 (in which only two states are concerned and shown for illustrative purpose), the initial distribution 10 with read voltage Th 0 may be suffered from retention issue after a long time not going through program/erase cycle, and therefore drifted downward to a shifted distribution 12 with a new read voltage Th 1 . A number of error bits (e.g., the shaded area) may incur if the initial read voltage Th 0 is still used to read data from the flash memory.

For the reason that conventional MLC or SLC flash memory could probably result in read errors due to cycle/retention issue, a need has arisen to propose some novel schemes to obtain proper read voltages for reading data from the flash memory.

In view of the foregoing, it is an object of the present embodiment to provide a method and system of finding a proper or optimal read voltage for a flash memory in order to minimize the error bit number.

According to one embodiment, data are read from array cells of the flash memory with a default read voltage, and a recorded state bit number that is recorded during programming is also read. Determine whether the readout data passes error correction control (ECC), followed by determining an optimal read voltage if the readout data do not pass the ECC. Data are re-read from the array cells of the flash memory with the determined optimal read voltage.

FIG. 1 shows error bits accompanied with a shifted threshold voltage distribution;

FIG. 2A is a flow diagram that illustrates a method of finding an optimal read voltage for a flash memory according to one embodiment of the present invention;

FIG. 2B is a flow diagram that illustrates a method of finding an optimal read voltage for a flash memory according to an embodiment alternative to that in FIG. 2A ;

FIG. 3A shows a detailed flow diagram of the optimal read voltage determination step in FIG. 2A or FIG. 2B according to a first embodiment of the present invention;

FIG. 3B illustrates the concept of the failure bit number;

FIG. 3C shows a further example that illustrates finding the failure ratio for a 3-bit MLC flash memory;

FIG. 4A shows a detailed flow diagram of the optimal read voltage determination step in FIG. 2A or FIG. 2B according to a second embodiment of the present invention;

FIG. 4B shows an example of finding the optimal read voltage by interpolation;

FIG. 4C shows an example of finding the optimal read voltage by extrapolation;

FIG. 5A shows a process of effectively reading a 3-bit MLC flash memory;

FIG. 5B shows a sequence according to which the state bit numbers are programmed;

FIG. 6A shows a block diagram that illustrates a system of finding an optimal read voltage for a flash memory according to the first embodiment with respect to FIG. 2 A/ 2 B and FIG. 3A ; and

FIG. 6B shows a block diagram that illustrates a system of finding an optimal read voltage for a flash memory according to the second embodiment with respect to FIG. 2 A/ 2 B and FIG. 4A .

FIG. 2A is a flow diagram that illustrates a method of finding an optimal read voltage for a flash memory according to one embodiment of the present invention. The embodiment may be adapted to a multi-level cell (MLC) flash memory as well as a single-level cell (SLC) flash memory.

Referring to FIG. 2A , after the flash memory is requested by a read command (the step 21 ), data are read from array cells of the flash memory with a default or original read voltage, and the bit number of each state that has been recorded beforehand in spare or redundant cells, during programming, is also read (the step 22 ). If the reading passes the error correction control (ECC), in the step 23 , that is applied to detect and correct error or errors, the reading finishes. Otherwise, an optimal read voltage is searched or determined in the step 24 . The determined optimal read voltage may be stored, for example, in a register before its use. Afterwards, the array cells of the flash memory are re-read, in the step 25 , using the determined read voltage.

FIG. 2B is a flow diagram that illustrates a method of finding an optimal read voltage for a flash memory according to an embodiment alternative to that in FIG. 2A . In the embodiment shown in FIG. 2B , before the step 24 is performed, if any new read voltage exists (the step 26 ), then the existed read voltage may be used to re-read the flash memory (the step 27 ). For example, if an optimal read voltage has been determined for a neighboring page, that optimal read voltage may then be used for the present page to re-read the flash memory. After the re-reading in the step 27 , determine whether the reading passes the error correction control (ECC) (the step 28 ). If the reading still does not pass the ECC, the read voltage searching step 24 is then performed.

FIG. 3A shows a detailed flow diagram of the step 24 (of FIG. 2A or FIG. 2B ) for determining the optimal read voltage according to a first embodiment of the present invention. In the embodiment, a page (or any specific amount) is read from the flash memory many times using multiple read voltages respectively (the step 241 ). Next, in the step 242 , the (cumulative) bit numbers (e.g., N 1 , N 2 , etc.) respectively corresponding to the read voltages (e.g., V 1 , V 2 , etc.) are counted, for example, as <N 1 ,V 1 >, <N 2 ,V 2 >, etc. Subsequently, in the step 243 , an optimal read voltage or offset voltage is determined according to a predetermined lookup table (LUT) that maps a failure ratio (or a failure bit number) to a read voltage (or offset voltage). FIG. 3B illustrates the concept of the failure bit number. As shown in the figure, the recorded (cumulative) bit number of state “1” using a default read voltage V 0 is n, and the counted (cumulative) bit number of the state “1” using the read voltage V 1 is N 1 . Therefore, the failure ratio F 1 with respect to the read voltage V 1 is (N 1 −n)/n. Similarly, the failure ratio F 2 with respect to a read voltage V 2 is (N 2 −n)/n, where N 2 is the associated counted bit number of state “1.” A lookup table is exemplified in the following Table 1. Specifically, the left column of Table 1 lists failure ratio with respect to each read voltage in the right column. Based on the lookup table, the optimal read voltage (or the offset voltage) may then be determined according to the failure ratio resulted from the reading in the step 241 .

It is appreciated that the failure ratio in the left column of Table 1 may be replaced with the failure bit number if all the states are uniformly distributed such that all the state bit numbers n are substantially the same. Moreover, the read voltage in the right column may be replaced with the offset voltage that is the difference between the read voltage and the default (or original) read voltage V 0 .

FIG. 3C shows a further example that illustrates finding the failure ratio for a 3-bit MLC flash memory that has 8 states. In the figure, a 0 is the recorded bit number for the state “1” that is recorded beforehand during the programming, and A 0 ′ is the counted bit number for the state “1” during reading. The shaded area, or (A 0 ′−a 0 ), is the failure bit number of the state c 4 . The failure ratio of the state c 4 is the ratio of the failure bit number to the bit number (c 4 ) of the state c 4 , or (A 0 ′−a 0 )/c4.

FIG. 4A shows a detailed flow diagram of the step 24 (of FIG. 2 A or FIG. 2B ) for determining the optimal read voltage according to a second embodiment of the present invention. The flow diagram in FIG. 4A is similar to that in FIG. 3A except that the step 243 is now replaced with the step 244 , in which the optimal read voltage is determined according to at least two sets of the recorded state bit number (during the programming) and the counted bit number (during the reading). For example, n 1 is the recorded bit number for the state “1,” N 1 is the first counted bit number for the state “1” using a first read voltage V 1 , and N 2 is the second counted bit number for the state “1” using a second read voltage V 2 . FIG. 4B shows an example in which the Y axis represents the counted state bit number minus the recorded state bit number, and the X axis represents the associated read voltage. The optimal interpolated read voltage V target between V 1 and V 2 has a state bit number equal to the counted state bit number n 1 . FIG. 4C shows a further example in which the optimal extrapolated read voltage V target of V 1 and V 2 has a state bit number equal to the recorded state bit number n 1 . Although interpolation/extrapolation optimization process is used in the embodiment, it is appreciated that other optimization process, such as linear regression analysis (LRA), maximum likelihood estimation (MLE), expectation maximization (EM) or binary search, may be used instead.

According to the embodiments described above, an optimal read voltage may be determined and then utilized to read the array cells of the flash memory with minimized failure (or error) bit number due to threshold voltage shift.

In order to facilitate the effectiveness of programming/reading a MLC flash memory, an effective method of recording the state bit number is adopted in the embodiment. FIG. 5A shows a process of effectively reading a 3-bit MLC flash memory. Specifically, group A is read using read voltage V 3 ; followed by reading group B using read voltages V 1 and V 5 ; and finally group C is read using read voltages V 0 , V 2 , V 4 and V 6 . In order to make sure the correctness and the reliability, the state bit numbers are programmed in a sequence as illustrated in Table 2 and depicted in FIG. 5B . According to this program sequence, read margin and reliability for each state can be substantially maximized.

According to one aspect of the present embodiment, the recorded space in the flash memory may be minimized by reducing the recorded state bit number. Table 3 shows an example in which only some portions of the state bit numbers are recorded, while other portions (that are in parenthesis) of the state bit numbers may be derived according to the recorded ones. Assume the page number is N, then the non-recorded state bit numbers may be derived as follows:

Group A; a1=N−a0; Group B: b1=a0−b0, b2=a1−b3=N−a0−b3; Group C: c1=b0−c0, c2=b1−c3=a0−b0−c3, c5=b2−c4=a1−b3−c4, c6=b3−c7.

FIG. 6A shows a block diagram that illustrates a system 5 of finding an optimal read voltage for a flash memory according to the first embodiment with respect to FIG. 2 A/ 2 B and FIG. 3A . The system 5 includes a flash memory 50 and a memory controller 52 . Data may be programmed to or read from the flash memory 50 from/to a host (not shown) through the memory controller 52 . Regarding the flash memory 50 , the data being programmed to or read from the array cells (not shown) of the flash memory 50 may be temporarily stored in a page buffer 500 , and operation and timing of the flash memory 50 may be managed by control logic 502 . Regarding the memory controller 52 , a data buffer 520 is used for temporarily storing data and for interfacing with the flash memory 50 , and control logic 522 is used for managing the operation and timing of the memory controller 52 .

The memory controller 52 further includes a data pair <N,V> generator 524 that generates the (cumulative) bit numbers (e.g., N 1 , N 2 , etc.) respectively corresponding to the read voltages (e.g., V 1 , V 2 , etc.) in the step 242 ( FIG. 3A ). The memory controller 52 also includes a read voltage decision device 528 that performs the step 243 ( FIG. 3A ) for determining the optimal read voltage or offset voltage according to a predetermined lookup table (LUT) 526 that maps a failure ratio (or a failure bit number) to a read voltage (or offset voltage).

FIG. 6B shows a block diagram that illustrates a system 5 B of finding an optimal read voltage for a flash memory according to the second embodiment with respect to FIG. 2 A/ 2 B and FIG. 4A . The system 5 B is similar to the system 5 except that the read voltage decision device 528 B performs the step 244 ( FIG. 4A ) for determining the optimal read voltage according to at least two sets of the recorded state bit number (during the programming) and the counted bit number (during the reading). In this second embodiment, no lookup table is need in the system 5 B.

Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.