Bi-directional low latency bus mode

This application claims the benefit of U.S. Provisional Application No. 61/091,864 filed on Aug. 26, 2008, the contents of which are herein incorporated by reference.

The present invention relates generally to wireless peripheral component interconnect busses.

Peripheral component interconnect such as PCI Express (PCIe) is a high performance, generic and scalable system interconnect bus for a wide variety of applications ranging from personal computers to embedded applications. PCIe implements serial, full duplex, multi-lane, point-to-point interconnect, packet-based, and switch based technology. Current versions of PCIe buses allow for a transfer rate of 2.5 Gbps per lane, with a total of 32 lanes.

As illustrated in FIG. 1 , the PCIe is a layered protocol bus, consisting of a transaction layer 110 , a data link layer 120 , and a physical layer 130 . The PCIe implements split transactions, i.e., transactions with request and response separated by time, allowing the link to carry other traffic while the target device gathers data for the response. With this aim, the primary function of the transaction layer 110 is to assemble and disassemble transaction layer packets (TLPs). TLPs are used to carry transactions, where each TLP has a unique identifier that enables a response directed at the originator. The data link layer 120 acts as an intermediate between the transaction layer 110 and the physical layer 130 and provides a reliable mechanism for exchanging TLPs. The data link layer 120 implements error checking (known as “link cyclic redundancy check (LCRC)”) and retransmission mechanisms. LCRC and sequencing are applied on received TLPs and if an error is detected, a data link retry is activated. The physical layer 130 consists of a logical sub-layer 132 and an electrical sub-layer 134 . The logical sub-layer 132 is a transmitter and receiver pair implementing symbol mapping, serialization and de-serialization of data. At the electrical sub-layer 134 , each lane utilizes two unidirectional low-voltage differential signaling (LVDS) pairs at 2.5 Gbit/s or 5 Gbit/s to transmit and receive symbols from the logical sub-layer 132 .

In the current technology, peripheral components are physically coupled to the PCIe. Recently, an effort is being made to wirelessly connect the peripheral devices to a computer. For example, a wireless USB technology for USB and Wi-Fi is a standard for Ethernet connection. However, each such wireless interconnect solution can support the connectivity of only a limited set of peripheral devices.

More advanced solutions propose a wireless peripheral interconnect bus, thereby allowing de-coupling of all peripheral devices connected to a computer. In order to enable efficient wireless transmissions peripheral interconnect bus solutions must guarantee low latency and reliable transmissions of data between the peripheral components of a wireless peripheral interconnect bus.

The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a diagram of layered protocol of a conventional PCIe bus.

FIG. 2 is a block diagram of a wireless PCIe fabric.

FIG. 3 is a diagram illustrating the bi-directional transmission during a service period.

FIG. 4 is a diagram of a frame structure constructed in accordance with certain embodiments of the invention.

FIG. 5 is a flowchart describing the bi-directional low latency bus mode implemented in accordance with certain embodiments of the invention.

It is important to note that the embodiments disclosed by the invention are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.

FIG. 2 is an exemplary diagram of a wireless fabric 200 utilized to describe the principles of the invention. The wireless fabric 200 is utilized for connecting peripheral components to a CPU (not shown) of a computer over a wireless medium. The CPU is connected to a host bridge 210 which communicates with endpoints 220 , a wireless root device 240 , and switches 250 . The wireless root device 240 communicates with wireless endpoint devices 230 - 1 through 230 -M using a wireless PCIe bus 205 .

The host bridge 210 identifies the wireless root device 240 and endpoint devices 230 as standard bus terminators (e.g., a PCIe endpoint, a PCIe switch, etc.). Data is transferred between the wireless root device 240 and the endpoint devices 230 over a wireless link, where the underlying wireless specifics are transparent to any component connected to fabric 200 . A wireless endpoint device 230 may be, but is not limited to, a legacy endpoint, a PCIe endpoint, a PCI switch, etc. and can be utilized to provide a connection to any type of peripheral devices including, but not limited to, storage devices, displays, projectors, monitors, input devices, PDAs, printers, optical disks, and so on. Point-to-multipoint connections are accomplished by the wireless root device 240 , which provides the fanout for the wireless PCIe bus 205 .

The invention discloses a method and data frame structure adapted to enable low latency bi-directional transmission between the wireless root device 240 and wireless endpoint devices 230 . The frame is a data structure that supports the physical (PHY) layer and medium access control (MAC) layer specifications of the wireless PCIe bus 205 . An exemplary implementation of the wireless PCIe 205 is described in US Publication No. 2008/0288705 entitled “Wireless Peripheral Interconnect Bus”, assigned to the common assignee and is hereby incorporated by reference for merely for the useful understanding of the invention.

The frame structure provides means for point-to-multipoint communication between the wireless root device 240 and the plurality of wireless endpoint devices 230 . The wireless root device 240 and endpoint devices 230 transmit and receive data packets during service periods, where a service period is defined as a period of time that the wireless root device 240 can communicate with its paired wireless endpoint devices 230 . As depicted in FIG. 3 , during a service period 300 , a wireless root device DEV-1 240 exchanges data with endpoint devices DEV-2 230 - 1 and DEV-3 230 - 2 . The root device communicates with each endpoint device at a time. For example, first, data is transferred between a wireless root device DEV-1 240 and an endpoint device DEV-2 230 - 1 , and then data is transferred between the wireless root device DEV-1 240 and an endpoint device DEV-3 230 - 2 . In accordance with an embodiment of the invention, when it is a first time that a root device and an endpoint device communicate with each other a short interframe space (SIFS) 310 follows by a long preamble (LP) 320 are transmitted. For subsequent data transfers, only a short preamble (SP) 330 is utilized.

A long preamble 320 typically includes a code sequence that allows a receiving device to perform the tasks of automatic gain control (AGC), signal detection, symbol alignment, frequency offset estimation, timing recovery and channel parameters estimation. The short preamble 330 may be used to increase the link efficiency. A device (either a root or an endpoint) transmits the receptive preamble together with aggregated MAC service data units (MSDUs) within a frame. Two consecutive frames transmitted by two different devices are separated by SIFS 310 that allows a device switching between a transmit mode and a receive mode. The duration of the SIFS can be shorter than that typically being used to further increase the efficiency of the bi-directional transmission mode.

FIG. 4 shows a non-limiting and exemplary diagram of a frame structure 400 constructed in accordance with an embodiment of the invention. The frame 400 is transmitted by the wireless root 240 and endpoint devices 230 . The structure of the frame 400 provides reliable MAC layer transmission by implementing an in-order delivery, a selective re-transmission of un-acknowledged MSDUs, and a block acknowledgment (ACK) mechanism. In addition, the frame 400 provides a mechanism for aggregating MSDUs and a “cut-through” transfer mode. In the cut-through transfer mode, packets which are being sent by the application layer are immediately being transmitted and are not buffered. It will be appreciated by one of ordinary skill in the art that the mechanisms implemented in accordance with the invention significantly reduce the latency of the wireless PCIe bus 205 .

The frame 400 comprises at least a preamble 411 , a physical (PHY) header 412 , a block acknowledgment (ACK) frame 420 , a plurality of MAC service data units (MSDUs) 430 - 1 through 430 -N. The block ACK frame 420 may be sent within the frame 400 and includes the following fields: a reverse direction (RD) 421 , a receiver (RX) buffer size 422 , a block ACK (BA) base request 423 , a BA reply 424 , a BA bitmap 425 , and a frame checksum (FCS) 426 . In the RD field 421 each device (either a root or an endpoint) indicates that a bi-directional transmission is employed. That is, the RD field 421 provides an indication to the receiving device that it should be switched from a receive mode to a transmit mode and replies with ACK information and MSDUs to the transmitting device. The RD field 421 maintains a “MORE” subfield (not shown) indicating additional data is to be sent on either side and implies the continuation of the RD assertion. When the RD “MORE” subfield is cleared, the transmitting device may choose to stop transmission handoff with the current receiving device, and select another device to initiate RD transmission handoff.

The fields 422 , 423 , 424 , and 425 are part of the block ACK (BA) mechanism. This mechanism transmits an ACK message upon a proper reception of a predefined number of MSDUs. The block ACK mechanism further provides an inline handshake of buffer management that determines how many more MSDUs can be transmitted (if there are no available MDSUs, then idle data units are transmitted). Specifically, the RX buffer size field 422 indicates that the free buffer space in MSDU units at the receiver; the BA base request field 423 indicates the block ACK base address expectations from the receiver, i.e., the most recent MSDU sequence number acknowledged at the transmitter; the BA base reply field 424 designates the first MSDU sequence number in the transmitted BA bitmap field 425 ; and the BA bitmap field 425 includes a number of N bits, a bit per MSDU, indicating whether or not the MSDU was received correctly. The size of the BA bitmap field 425 can be negotiated between the devices. In accordance with an embodiment of the invention the block ACK mechanism enables recovery of payload data (i.e., MSDUs 430 ) even if the block ACK frame 420 was not correctly transmitted. The FCS field 426 includes a cyclic redundancy check (CRC) code computed for the entire data in the block ACK frame 420 .

Each MSDU 430 includes a MSDU subheader 431 , MSDU payload data 432 , and a frame checksum field 433 which includes a CRC value computed over the MSDU payload data and subheader. A MSDU 430 comprises data packets received from a data link layer (e.g., layer 120 ) of the PCIe protocol. The MSDU subheader 431 includes three fields: a sequence number of the MSDU, its length and the header checksum.

FIG. 5 shows a non-limiting and exemplary flowchart 500 describing the bi-directional low latency bus (BDLLB) mode implemented in accordance with certain embodiments of the invention. The BDLLB mode allows low latency data transfers between a wireless root device 240 and wireless end point devices 230 .

At S 510 , the wireless root and the endpoint devices are set to operate in the BDLLB mode. Specifically, a wireless root device 240 advertises its capabilities (e.g., data rate) and association information and an endpoint device 230 searches for a wireless root device 240 operating in a BDLLB mode to establish the connection with. The search also can be initiated by the wireless root device 240 . Once the operation mode is set, a time for transmission during a service period is allocated for both wireless root device 240 and endpoint device 230 . At S 520 , the wireless root device 240 generates a frame to be transmitted to the endpoint device 230 . As this is a first time that data is transferred between the devices, the preamble 411 would be a long preamble. In addition, the RD field 421 is set for reverse-direction, the RX buffer size field 422 is set for a maximum MSDUs that the root can receive, and the bits in the BA bitmap 425 are set to null. MSDUs received from a data link layer are order, in the MSDU 430 , according to the order in which they received from the data link layer. The receptive MSDU subheaders 431 are also generated. At S 530 , after waiting for the SIFS period to elapse, the generated frame is sent to the endpoint device, which processes the frame and switches from a receive mode to a transmit mode.

Upon reception of the frame, at S 540 , the endpoint generates a frame to be transmitted to the wireless root device 240 . This includes generating a long preamble to be inserted in the preamble field 411 , setting the RX buffer size 422 to the free space in the buffer, and designating in the BA bitmaps MSDUs that were properly received. In addition, aggregated MSDUs are arranged in the frame 400 according to the order in which they received from a data link layer. At S 550 , the generated frame is sent from the endpoint device 230 to the wireless root device 240 . At S 560 , the received frame is processed by the wireless root device 240 which checks at least which MSDUs were not acknowledged, thereby were not received at the endpoint 230 . The MSDUs will be transmitted in the next frame sent from the wireless root device 240 to the endpoint device 230 . It should be noted that using the BA base request 423 and BA base reply 424 the root device 240 may decide not to re-transmit one or more MSDUs. Any subsequent transmissions will be performed as described herein, where a short preamble may be used instead of a long preamble in field 411 .

The teachings described herein can be adapted for the use with any peripheral interconnect bus including, but not limited to, PCIe second generation, PCIe third generation, SATA, USB, and the like. Moreover, some or all of the method components described herein are implemented as a computer executable code. Such a computer executable code contains a plurality of computer instructions that when performed result with the execution of the tasks disclosed herein. Such computer executable code may be available as source code or in object code, and may be further comprised as part of, for example, a portable memory device or downloaded from the Internet, or embodied on a program storage unit or computer readable medium. Information that is generated by the computer executable code may be output from a computer. In accordance with another embodiment, the invention described herein can be utilized to provide an efficient communication between a wireless docking station and a plurality of peripheral devices wirelessly connected to the docking station.

The foregoing detailed description has set forth a few of the many forms that the invention can take. It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a limitation to the definition of the invention. It is only the claims, including all equivalents that are intended to define the scope of this invention. Most preferably, the principles of the invention are implemented as any combination of hardware, firmware and software. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage unit or computer readable medium. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units (“CPUs”), a memory, and input/output interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a CPU, whether or not such computer or processor is explicitly shown. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit.