Low noise amplifier

This application claims the priority benefit of Taiwan application serial no. 98119055, filed on Jun. 8, 2009. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

The present invention relates to a low noise amplifier.

The low noise amplifier (LNA) in a radio frequency (RF) chip with a single receiving or a differential receiving is determined by the product positioning. In other words, after the RF chip is manufactured, the receiving mode of the LNA is either the single receiving or the differential receiving. Therefore, the LNA is incapable of supporting these two receiving modes under the RF chip is manufactured.

The present disclosure is directed to a low noise amplifier including an amplifier kernel circuit and a DC bias unit. The amplifier kernel circuit is used for receiving a single input signal or a differential input signal so as to generate a differential output signal. The DC bias unit is coupled to the amplifier kernel circuit, and is used for processing a signal source to generate the single input signal or the differential input signal according to its circuit configuration.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a block diagram of a low noise amplifier according to an exemplary embodiment.

FIG. 2 is a circuit diagram of an amplifier kernel circuit according to an exemplary embodiment.

FIGS. 3 through 4C are respectively a circuit diagram of a DC bias unit which may make that the receiving mode of the low noise amplifier is a differential receiving according to an exemplary embodiment.

FIGS. 5A through 5C are respectively a circuit diagram of a DC bias unit which may make that the receiving mode of the low noise amplifier is a single receiving according to an exemplary embodiment.

Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a block diagram of a low noise amplifier (LNA) 100 according to an exemplary embodiment. Referring to FIG. 1 , the LNA 100 includes an amplifier kernel circuit 101 and a DC bias unit 103 . The amplifier kernel circuit 101 is used for receiving a single input signal Vs or a differential input signal Vs+ and Vs− so as to output a differential output signal Vo+ and Vo−, for example, a differential voltage output signal. The DC bias unit 103 is coupled to the amplifier kernel circuit 101 , and is used for processing a signal source SS to generate the single input signal Vs (for example, a single voltage input signal, but not limited thereto) or the differential input signal Vs+ and Vs− (for example, a differential voltage input signal, but not limited thereto) according to its circuit configuration.

In the exemplary embodiment, the amplifier kernel circuit 101 and the DC bias unit 103 are not simultaneously implemented on a chip (not shown, for example, an RF is chip, but not limited thereto). To be specific, the amplifier kernel circuit 101 may be implemented on the chip, and the DC bias unit 103 may be implemented using off-chip components (for example, the DC bias unit 103 may be implemented on the PCB). Accordingly, after the RF chip is manufactured, the receiving mode of the LNA 100 may be adaptively changed to a single receiving or a differential receiving by designing the circuit configuration of the DC bias unit 103 in accordance with the product positioning. Therefore, the LNA 100 is capable of supporting the single receiving and the differential receiving under the RF chip is manufactured, namely, the amplifier kernel circuit 101 is not changed.

However, in the other exemplary embodiments, the amplifier kernel circuit 101 and the DC bias unit 103 can be simultaneously implemented on the same chip. In other words, the DC bias unit 103 is not limited to be implemented using off-chip components.

FIG. 2 is a circuit diagram of the amplifier kernel circuit 101 according to an exemplary embodiment. Referring to FIGS. 1 and 2 , the amplifier kernel circuit 101 includes an input transconductance unit 201 , a current buffer unit 203 and an output load unit 205 . The input transconductance unit 201 is coupled to the DC bias unit 103 , and used for receiving and processing the single input signal Vs or the differential input signal Vs+ and Vs− so as to generate a differential current signal I+ and I−. The current buffer unit 203 is coupled to the input transconductance unit 201 , and used for receiving and buffering the differential current signal I+ and I− so as to output a buffered differential current signal I B + and I B −. The output load unit 205 is coupled to the current buffer unit 203 , and used for receiving the buffered differential current signal I B + and I B − and outputting a differential output signal Vo+ and Vo− accordingly.

To be specific, the input transconductance unit 201 includes two transistors M 1 and M 2 , two resistors R 1 and R 2 , and two capacitors C 1 and C 2 . The gate of the transistor M 1 receives a bias voltage V B1 through the resistor R 1 and is coupled to the source of the transistor M 2 through the capacitor C 1 . The drain of the transistor M 1 is used for outputting the positive current signal I+ of the differential current signal I+ and I−. The source of the transistor M 1 is used for receiving the single input signal Vs or the positive input signal Vs+ of the differential input signal Vs+ and Vs−.

The gate of the transistor M 2 receives the bias voltage V B1 through the resistor R 2 and is coupled to the source of the transistor M 1 through the capacitor C 2 . The bulk of the transistor M 2 is coupled to the source of the transistor M 1 . The-drain of the transistor M 2 is used for outputting the negative current signal I− of the, differential current signal I+ and I−. The source of the transistor M 2 is coupled to the bulk of the transistor M 1 , and used for receiving the negative input signal Vs− of the differential input signal Vs+ and Vs− or coupled to the ground GND through the DC bias unit 103 .

In addition, the current buffer unit 203 includes two transistors M 3 and M 4 , two resistors R 3 and R 4 , and two capacitors C 3 and C 4 . The gate of the transistor M 3 receives a bias voltage V B2 through the resistor R 3 and is coupled to the source of the transistor M 4 through the capacitor C 3 . The source of the transistor M 3 is coupled to the drain of the transistor M 1 . The drain of the transistor M 3 is used for outputting the positive buffered current signal I B + of the buffered differential current signal I B + and I B −. The gate of the transistor M 4 receives the bias voltage V B2 through the resistor R 4 and is coupled to the source of the transistor M 3 through the capacitor C 4 . The source of the transistor M 4 is coupled to the drain of the transistor M 2 . The drain of the transistor M 4 is used for outputting the negative buffered current signal I B − of the buffered differential current signal I B + and I B −.

Furthermore, the output load unit 205 includes two loads ZL 1 and ZL 2 . The first terminal of the load ZL 1 is coupled to a system voltage V DD and a second terminal of the load ZL 1 is coupled to the drain of the transistor M 3 and used for outputting the positive output signal Vo+ of the differential output signal Vo+ and Vo−. The first terminal of the load ZL 2 is coupled to the system voltage V DD and, a second terminal of the load ZL 2 is coupled to the drain of the transistor M 4 and outputting the negative output signal Vo− of the differential output signal Vo+ and Vo−.

Herein, suppose the receiving mode of the LNA 100 is the differential receiving, the circuit configuration of the DC bias unit 103 has several choices in below, but not limited thereto.

FIG. 3 is a circuit diagram of the DC bias unit 103 which may make that the receiving mode of the LNA 100 is a differential receiving according to an exemplary embodiment. Referring to FIGS. 1 through 3 , the DC bias unit 103 includes a balance-unbalance (Balun) converter T such as a transformer, but not limited thereto. The Balun T has a primary side and a secondary side. The first terminal of the primary side of the Balun T is used for receiving the signal source SS, wherein the signal source SS may be a signal received from an antenna, but not limited thereto.

The second terminal of the primary side of the Balun T is coupled to the ground GND. The first terminal of the secondary side of the Balun T is coupled to the source of the transistor M 1 to generate the positive input signal Vs+ of the differential input signal Vs+ and Vs−. The center tap terminal of the secondary side of the Balun T is coupled to the ground GND. The second terminal of the secondary side of the Balun T is coupled to source of the transistor M 2 to generate the negative input signal Vs− of the differential input signal Vs+ and Vs−.

FIG. 4A is a circuit diagram of the DC bias unit 103 which also may make that the receiving mode of the LNA 100 is a differential receiving according to another exemplary embodiment of the present disclosure. Referring to FIGS. 1 , 2 and 4 A, the DC bias unit 103 includes a balance-unbalance (Balun) converter T′ and two inductors L 1 and L 2 , wherein the Balun T′ may be a transformer or an element recited in the website of http://en.wikipedia.org/wiki/Balun, but not limited thereto. The Balun T′ has a primary side and a secondary side. The first terminal of the primary side of the Balun T′ is used for receiving the signal source SS, wherein the signal source SS may be a signal received from an antenna, but not limited thereto.

The second terminal of the primary side of the Balun T′ is coupled to the ground GND. The first terminal of the secondary side of the Balun T′ is coupled to the source of the transistor M 1 to generate the positive input signal Vs+ of the differential input signal Vs+ and Vs−. The second terminal of the secondary side of the Balun T′ is coupled to source of the transistor M 2 to generate the negative input signal Vs− of the differential input signal Vs+ and Vs−. The first terminal of the inductor L 1 is coupled to the first terminal of secondary side of the Balun T′, and the second terminal of the inductor L 1 is coupled to the ground GND. The first terminal of the inductor L 2 is coupled to the second terminal of secondary side of the Balun T′, and the second terminal of the inductor L 2 is coupled-to the ground GND.

FIG. 4B is a circuit diagram of the DC bias unit 103 which also may make that the receiving mode of the LNA 100 is a differential receiving according to another exemplary embodiment. Referring to FIGS. 4A and 4B , compared FIG. 4A with FIG. 4B , the difference between FIGS. 4A and 4B is that two high impedance elements ZH 1 and ZH 2 in FIG. 4B would replace the inductors L 1 and L 2 in FIG.4A . The high impedance elements ZH 1 and ZH 2 can be a resistor respectively, but not limited thereto.

FIG. 4C is a circuit diagram of the DC bias unit 103 which also may make that the receiving mode of the LNA 100 is a differential receiving according to another exemplary embodiment. Referring to FIGS. 4A and 4C , compared FIG. 4A with FIG. 4C , the difference between FIGS. 4A and- 4 C is that two transistors M 5 and M 6 in FIG. 4C would replace the inductors L 1 and L 2 in FIG.4A . The gate of the transistor M 5 is used for receiving a bias voltage V B3 , the drain of the transistor M 5 is coupled to the source of the transistor M 1 , and the source of the transistor M 5 is coupled to the ground GND. The gate of the transistor M 6 is used for receiving the bias voltage V B3 , the drain of the transistor M 6 is coupled to the source of the transistor M 2 , and the source of the transistor M 6 is coupled to the ground GND.

The DC bias units 103 respectively shown in FIGS. 3 through 4C all can be made that the receiving mode of the LNA 100 is a differential receiving, and the transistors M 1 and M 2 are both configured as a common gate amplifier at this time. Since the capacitors C 1 and C 2 are cross-coupled between the gates and sources of the transistors M 1 and M 2 , the transconductance of the transistors M 1 and M 2 are boosted from g m to 2*g m . Furthermore, the bulks of the transistors M 1 and M 2 are also cross-coupled, which effectively boosts the transconductance of the transistors M 1 and M 2 from g m to (g m +g mb ), where g mb is the body transconductance. Therefore, the input transconductance (g m ) can be effectively amplified to 2*(g m +g mb ) under the turns ratio of the Balun T/T′ is set to be 1:1. Accordingly, the input impedance (Z in ) of the LNA 100 with the differential receiving can be approximately seen as 1/(g m +g mb ), and the voltage gain (Av) is equal to 2*k*(g m +g mb )*ZL, wherein k=2*Z in /(Rs+Z in ). The value of k is equal to 1 under the perfect input impedance match with Z in =Rs=50Ω; and ZL is the resistance value of the loads ZL 1 and ZL 2 .

Herein, suppose the receiving mode of the LNA 100 is the single receiving, the circuit configuration of the DC bias unit 103 has several choices in below, but not limited thereto.

FIG. 5A is a circuit diagram of the DC bias unit 103 which may make that the receiving mode of the LNA: 100 is a single receiving according to an exemplary embodiment. Referring to FIGS. 1 , 2 and 5 A, the DC bias unit 103 includes an inductor L. The first terminal of the inductor L is used for receiving the signal source SS and is coupled to the source of the transistor M 1 , and the second terminal of the inductor L is coupled to the ground GND and the source of the transistor M 2 , wherein the signal source SS may be a signal received from an antenna, but not limited thereto.

FIG. 5B is a circuit diagram of the DC bias unit 103 which also may make that the receiving mode of the LNA 100 is a single receiving according to another exemplary embodiment. Referring to FIGS. 1 , 2 and 5 B, the DC bias unit 103 includes two high impedance elements ZH 1 and ZH 2 , and a capacitor C 5 . The first terminal of the high impedance element ZH 1 is coupled to the source of the transistor M 1 , and the second terminal of the high impedance element ZH 1 is coupled to the ground GND. The first terminal of the high impedance element ZH 2 is coupled to the source of the transistor M 2 , and the second terminal of the high impedance element ZH 2 is coupled to the ground GND. The capacitor C 5 is coupled with the high impedance element ZH 2 in parallel. The high impedance elements ZH 1 and ZH 2 may be a resistor respectively, but not limited thereto.

FIG. 5C is a circuit diagram of the DC bias unit 103 which also may make that the receiving mode of the LNA 100 is a single receiving according to another exemplary embodiment of the present disclosure. Referring to FIGS. 1 , 2 and 5 C, the DC bias unit 103 includes two transistors M 5 and M 6 , and a capacitor C 5 . The gate of the transistor M 5 is used for receiving a bias voltage V B3 , the drain of the transistor M 5 is coupled to the source of the transistor M 1 , and the source of the transistor M 5 is coupled to the ground GND. The gate of the transistor M 6 is used for receiving the bias voltage V B3 , the drain of the transistor M 6 is coupled to the source of the transistor M 2 , and the source of the transistor M 6 is coupled to the ground GND. The first terminal of the capacitor C 5 is coupled to the source of the transistor M 2 and the second terminal of the capacitor C 5 is coupled to the ground GND.

The DC bias units 103 respectively shown in FIGS. 5A through 5C all can be made that the receiving mode of the LNA 100 is a single receiving, and the transistors M 1 and M 2 are respectively configured as a common gate amplifier and a common source amplifier at this time. Since the bulks of the transistors M 1 and M 2 are cross-coupled, the input transconductance (g m ) can be amplified to (g m +g mb ). Thus, the parallel common-gate and common-source amplifiers totally contributes an effective transconductance of 2*(g m +g mb ). Accordingly, the input impedance (Z in ) of the LNA 100 with the single receiving also can be approximately seen as 1/(g m +g mb ), and the voltage gain (Av) is also equal to 2*k*(g m +g mb )*ZL.

Thereunder, whether the receiving mode of the LNA 100 is the single receiving or the differential receiving, the input impedance (Z in ) and the voltage gain (Av) are not changed. Accordingly, the LNA 100 is capable of supporting the single receiving and the differential receiving by changing the circuit configuration of the DC bias unit 103 under the amplifier kernel circuit 101 is not changed.

Besides, in accordance with the requirements of different product positioning, for example, the develop of product with high performance or low cost and high integration (e.g. SoC) or lower integration (e.g. RF transceiver), the circuit configuration of the DC bias unit 103 can be adaptively changed so as to make that the receiving mode of the LNA 100 can be adaptively changed to the single receiving or the differential receiving.

It will be apparent to those skills in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.