Circuit arrangement for controlling a high side CMOS transistor in a high voltage deep sub micron process

The present invention relates to a circuit arrangement, which is used for controlling a high side Complementary Metal Oxide Semiconductor (CMOS) transistor in a high voltage deep sub micron process. The high side CMOS transistor is used for switching high voltages. But, in a high voltage deep sub micron process, the maximum allowed voltage across the gate oxide and the source of the high side transistor is limited to be smaller than a predetermined voltage rating, e.g. 3.3 V, while the voltage with respect to the substrate of the circuit arrangement can vary from 5 V to 100V, which is the high side voltage. In an automotive environment, the battery voltage of a car is between 5 V and 60V. This voltage may appear when the battery is charged and the connection to the battery is suddenly interrupted, a so-called load dump.

In other words, the supply voltage of the high side CMOS transistor exceeds the maximum voltage rating of the gate oxide. For limiting the gate voltage and for reliably operating the high side CMOS transistor, an accurate voltage reference is required to provide a voltage within the voltage rating of the gate oxide. This high side voltage reference must be accurate and provide a low current. Such accuracy is needed due to the low tolerance of the maximum voltage rating of the gate oxide of the high side CMOS transistor. Additionally, the circuit should consume as little current as possible due to reliability concerns. In the automotive industry, circuits can be fed directly from the battery. Therefore, they are continuously under voltage during the total lifecycle of a car. Thus, it is strongly required to reduce the current as much as possible, especially for chips having a very thin gate oxide, as in the case of a deep sub micron process.

A known solution for providing a high side voltage reference is a floating DC voltage source. However, such a solution does not have limited current consumption. Such a floating DC voltage source is illustrated in FIG. 1 in an abstract from.

Therefore, the object of the present invention is to provide a circuit arrangement for switching a high side CMOS transistor in a circuit having a very thin gate oxide, which is in particular produced by a deep sub micron process. This object is obtained by the features of the independent claims.

The invention is based on the idea of providing a high side voltage reference having a low current consumption. By providing such a high side voltage reference, it is possible to control the high side CMOS transistor without providing a circuit having a high current consumption. In particular, it is proposed to control the high side CMOS transistor at its gate with a high side reference potential including a capacitor which is charged or discharged and thereby switches on or off the high side CMOS transistor.

Due to the use of the capacitor, it is possible to create an accurate biasing voltage at the reference voltage for switching on the high side CMOS transistor. The capacitor is charged using a current having only a small number of pulses. The high side voltage reference used for the inventive circuit may include a resistor connected to the high side voltage and the reference voltage. The capacitor is coupled in parallel to the resistor between the high side voltage and the reference voltage. A diode is coupled between the resistor and the capacitor at the reference voltage for preventing a discharge of the charged capacitor during the off-periods of the pulsed current source.

In a preferred embodiment, it is proposed that the current source includes a first and a second switch, which are controlled to charge/discharge the capacitor and thereby to switch on/off the high side CMOS transistor. The first switch is connected to the cathode of the diode and to the first resistor of the high side voltage reference. The second switch is used for discharging the capacitor. The first and second switches are controlled by using a first and a second pulse, which are generated by an external clock. The duty cycle for the first and second pulses is very low. Thus, the effective current running through the circuit is drastically reduced.

In the preferred embodiment, the first switch is realized as an N-type Metal Oxide Semiconductor (NMOS) transistor, which is switched on by the first pulse, which is applied to the gate of the first NMOS transistor. The NMOS transistor is creates a pulsed current flowing through the resistor, the diode, and the capacitor for charging the capacitor. By applying the first pulses to the first NMOS transistor, an accurate biasing voltage is created at the reference voltage, which is necessary for reliably switching on the high side CMOS transistor. Due to the use of the capacitor, it is possible to provide this accurate biasing voltage, which is within the voltage rating of the gate oxide. Thereby, the gate oxide of the high side CMOS transistor is prevented from being destroyed due to higher voltages.

The second switch is also realized as an NMOS transistor, which is switched on by a second pulse at its gate, wherein, by switching on the second pulse at the second NMOS transistor, the high side CMOS transistor is switched off. In particular, it is proposed to reliably discharge the capacitor to provide a further resistor between the high voltage and the reference voltage and to provide a third transistor between the high voltage and the reference voltage. By switching off the first transistor and by providing the second pulse at the gate of the second transistor, a voltage pulse is created across the further resistor between the high voltage and the reference voltage. Thus, the third transistor between the high side voltage and the reference voltage is driven, thereby discharging the capacitor and resulting in a switching off of the high side CMOS transistor.

In a preferred embodiment of the invention, the first and second pulses used for controlling the first and second switches are identical in their duty cycle. Alternatively, it may be advantageous that the first and second pulses have different forms. In particular, it may be required to charge the capacitor after switching off the high side transistor faster. Thus, it is required to extend the first pulse in time to charge the capacitor for a longer time.

In a further preferred embodiment, it is proposed to use a level shifter as a high side voltage reference for providing the reference potential voltage.

Below, preferred embodiments of the invention are explained in more detail by use of the following figures in which:

FIG. 1 shows a schematic circuit diagram of a floating DC voltage source for controlling the high side CMOS transistor;

FIG. 2 shows a first embodiment;

FIG. 3 shows a realization of the first embodiment;

FIGS. 4 a and 4 b illustrate timing diagrams showing the first and second pulses for charging and discharging the capacitor;

FIG. 5 shows second embodiment.

FIG. 1 shows a schematic circuit diagram, in which a high side CMOS transistor M 1 is coupled to the high side voltage Vbat and an external output OUT, wherein the gate of the high side CMOS transistor M 1 is controlled by a high side voltage reference 11 . The high side CMOS transistor M 1 is used for switching high voltages. Since the gate source voltage of this high side CMOS transistor M 1 has a limited voltage rating, an accurate high side voltage reference 11 is required to operate the high side CMOS transistor M 1 . This high side voltage reference 11 should consume as little power as possible, since it should be used in an automotive environment. Integrated circuits of a car may be coupled to the power supply (Vbat) during the whole lifetime of a car. Therefore, the power consumption should be reduced as much as possible.

In more detail, a circuit diagram is illustrated in FIG. 2 . There is a high side CMOS transistor M 1 , which is coupled between the high side voltage Vbat, and an external output OUT. The high side voltage reference 11 is composed of a resistor R 1 connected to the high side voltage Vbat and the reference voltage and a capacitor C 1 having a capacity of 1 to 50 pF. The capacitor C 1 is charged/discharged and thereby a switching on/off of the high side CMOS transistor M 1 is achieved. The capacitor C 1 is connected to the high side voltage Vbat and the reference voltage. For charging the capacitor C 1 , a pulsed current source 21 is used. For preventing a current flow during off cycles of the pulsed current source, which would cause a discharge of the capacitor C 1 , a diode D is connected between the capacitor C 1 and the current source 21 .

A first embodiment of a circuit arrangement is explained in more detail with reference to FIG. 3 . Therein, the high side CMOS transistor M 1 is connected between the high side voltage Vbat and the external output OUT. Further, there is a high side voltage reference 11 comprising the resistor R 1 , the capacitor C 1 , and the diode D between the resistor R 1 and the capacitor C 1 . Additionally, there is the current source 21 comprising a first switch M 3 and a second switch M 4 . The first switch M 3 is realized as an NMOS transistor coupled between the reference voltage and ground via a further resistor R 3 . The first switch M 3 is pulsed by a first pulse A. A second switch M 4 is pulsed by a second pulse B, wherein a further resistor R 4 is connected between the source of the second switch M 4 and ground. A third transistor M 2 is coupled between the high side voltage Vbat and the reference voltage, wherein the gate of the third transistor M 2 is connected to second switch M 4 . A further resistor R 2 is coupled between the high side voltage Vbat and the second switch M 4 for providing a voltage for controlling the gate of the third transistor M 2 .

Now, the functioning of the circuit diagram as shown in FIG. 3 is explained by use of FIG. 4 a . When applying the first pulse A at the gate of the first switch M 3 , the peak voltage across the resistor R 1 is determined by the peak voltage at the gate of the first switch M 3 and the ratio of the resistors R 1 and R 3 . By applying the pulse A at the gate of the first switch M 3 , the capacitor C 1 is charged to an accurate voltage, which can drive the gate of the high side CMOS transistor M 1 . Thus, the high side CMOS transistor M 1 could be switched on by use of an accurate voltage provided by the charge of the capacitor C 1 . For turning off the high side CMOS transistor M 1 , a first pulse A at the first switch M 3 is switched off and a second pulse B is provided at the gate of the second switch M 4 instead. This creates accurate voltage pulses across the resistor R 2 between the high voltage Vbat and second switch M 4 which drives the third transistor M 2 to discharge the capacitor C 1 and thereby switching off the high side CMOS transistor M 1 . Both switches M 3 , M 4 are driven with a very low duty cycle as can be seen in FIG. 4 a for charging the capacitor C 1 or to keep the capacitor C 1 discharged even in the presence of leakage currents. FIG. 4 a illustrates the voltage waveforms on nodes A, B, C as shown in FIG. 4 a . As long as there is a voltage drop across capacitor C 1 , it is charged. When switching off the first pulse A and switching on the second pulse B, instead, there is no voltage drop across C 1 anymore. Thus, the capacitor C 1 is discharged, resulting in a switching off the high side CMOS transistor M 1 .

As shown in FIG. 4 a , the pulses for the first and second switch M 3 and M 4 have identical duty cycles. However, it is possible to use different pulse forms as shown in FIG. 4 b . Especially, when first switching on the first switch M 3 , after the second switch M 4 was operated, the capacitor C 1 is fully discharged and it is advantageous to switch on the first switch M 3 for a longer time in order to charge capacitor C 1 more quickly. This could be easily seen in FIG. 4 b . The capacitor C 1 is charged during one long pulse or several short pulses with a predetermined duty cycle as illustrated in FIG. 4 b . After C 1 is charged, a recharging with a low duty cycle with short pulses is necessary. Recharging is necessary because leakage currents are always present in silicon processes, which can discharge the capacitor C 1 slowly. Therefore, a controlled discharge of the capacitor C 1 would ideally be done with one pulse on the second switch M 4 , wherein the length of the pulse is unrelated to the length of the pulse on M 3 which charges C 1 .

In case of identical pulses the pulse widths for pulses A and B maybe in the range of 0.1-1 μs, wherein the distance between the pulses maybe 0.1-1 ms. For FIG. 4 b the same values could be used, wherein the longer pulse of pulse A may be three times longer than the shorter pulses of M 4 .

FIG. 5 illustrates a second embodiment of the circuit arrangement. FIG. 5 illustrates a high side voltage reference 11 providing the reference voltage for switching on/off the high side CMOS transistor M 1 . There is an external voltage source V ex , providing a predetermined voltage, e.g., 3.3 V. By using a double-switch Q 1 , the external voltage source V ex , can be connected to a second capacitor CO for charging this second capacitor CO. The second capacitor CO may be connected to the high voltage Vbat and to ground by switches Q 1 or Q 2 , respectively. The switch Q 2 connects the second capacitor CO with the high side voltage Vbat. The second capacitor CO is coupled in parallel to the first capacitor C 1 . At the reference potential, there is a diode D for preventing a discharge of the first capacitor C 1 . When switch Q 1 is closed and switch Q 2 is opened, the second capacitor CO is charged at 3.3V. When switch Q 2 is closed and switch Q 1 is opened, the voltage drop on the second capacitor CO is still 3.3V. The voltage drop on the first capacitor C 1 is then increased to the high voltage Vbat-3.3V. Again, the diode D serves to make sure that current can flow back to C 1 to discharge the first capacitor C 1 . By charging/discharging the first capacitor C 1 , the high side CMOS transistor M 1 could be switched on/off. When switches Q 1 and Q 2 are controlled to discharge the first capacitor C 1 , the high side CMOS transistor M 1 is switched off. By providing the low current high side voltage reference according to the second embodiment, it is possible to switch on/off the high side CMOS transistor M 1 without destroying the very thin gate oxide of the high side CMOS transistor M 1 that is produced in deep sub micron process.

A clear advantage of the second embodiment over the first is that there is no wasted power, when neglecting parasitic capacitances. When switched on, the first embodiment always consumes power even when the capacitor C 1 , that stores the high-side voltage, does not need to be charged. In contrast, the second embodiment only supplies the charge needed to create the required voltage.