Output circuit and driving method thereof

The present application claims priority of Korean patent application No. 10-2008-0079862, filed on Aug. 14, 2008, the disclosure of which is incorporated herein by reference in its entirety.

The present invention relates to a semiconductor device, and more particularly, to an output circuit for adjusting a slew rate of data outputted from the semiconductor device, when an operation frequency of the semiconductor device is changed.

In general, a semiconductor device includes the output circuit to output a data, and the output circuit includes a pre-driver and an output driver. The pre-driver outputs a pull-up signal and a pull-down signal which correspond to the data outputted from memory cells. The output driver outputs the data to an output pad in response to the pull-up signal and the pull-down signal.

The data transferred from the output circuit to the output pad has the slew rate, which is a change amount of output voltage per unit time. The slew rate of data is changed according to a design of a semiconductor device such as the number of the output pads. For example, when the number of the output circuits satisfies the conditions for ×4, ×8 and ×16 operation modes of the semiconductor device, the slew rate of data is depending on operation modes, that is, operation modes have different slew rate of data. Particularly, when the semiconductor device is operated in ×16 operation mode, the slew rate of data is lower then that of ×4 or ×8 operation mode.

FIG. 1 is a timing diagram illustrating the operation of a conventional output circuit.

Referring to FIG. 1 , the slew rate of data in ×4, ×8 and ×16 operation modes are different. Generally, the output circuit is designed based on the slew rate of data corresponding to ×16 operation mode. Thus, when the semiconductor device is operated in ×4 or ×8 operation mode, the semiconductor device may consume an operation current excessively.

Embodiments of the present invention are directed to provide an output circuit that can prevent the current consumption of the semiconductor device.

In accordance with an aspect of the present invention, there is provided an output circuit comprising a pre-driving unit configured to drive an input signal by using a different driving power according to an output operation mode and generate pull-up and pull-down signals corresponding to the resultant input signal and an output driving unit configured to output data in response to the pull-up and pull-down signals.

In accordance with another aspect of the present invention, there is provided a method for driving an output circuit comprising varying a driving power of an input signal according to an output operation mode, generating pull-up and pull-down signals corresponding to the resultant input signal and generating an output data corresponding to the pull-up and pull-down signals.

In accordance with another aspect of the present invention, there is provided an output circuit comprising a pre-driving unit configured to have a variable driving power selected in response to an output operation mode and generate pull-up and pull-down signals corresponding to an input signal by using the selected driving power and an output driving unit configured to generate output data in response to the pull-up and pull-down signals.

FIG. 1 is a timing diagram illustrating the operation of the conventional output circuit.

FIG. 2 is a block diagram illustrating an output circuit of a semiconductor device in accordance with an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the output circuit shown in FIG. 2 .

FIG. 4 is a timing diagram illustrating the operation of the output circuit shown in FIG. 2 .

Other objects and advantages of the present invention can be understood by the following description, and become apparent with reference to the embodiments of the invention.

FIG. 2 is a block diagram illustrating an output circuit of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2 , the output circuit includes a pre-driving unit 10 and an output driving unit 20 .

The pre-driving unit 10 is configured to receive an input data DOUT and output operation modes, and to vary a driving power according to an output operation mode, and generates pull-up and pull-down signals PU and PD. The output operation mode includes a first output operation mode being ×4 operation mode, a second output operation mode being ×8 operation mode and a third output operation mode being ×16 operation mode. Herein, ×4, ×8 and ×16 operation modes indicate the number of data which is simultaneously inputted or outputted once during a write operation or a read operation when the semiconductor device operates. For example, ×8 operation mode denotes that eight data are simultaneously inputted or outputted once during a write operation or a read operation. That is, in ×8 operation mode, the semiconductor device enables eight write drivers selected from a plurality of write drivers in the bank to perform the write operation or the read operation.

The output driving unit 20 is configured to generate output data DQ in response to the pull-up and pull-down signals PU and PD, and the output data DQ is transferred to an output pad.

FIG. 3 is a circuit diagram illustrating the output circuit shown in FIG. 2 .

Referring to FIG. 3 , the pre-driving unit 10 includes a pull-up pre-driving unit 100 , a pull-down pre-driving unit 102 and a control unit 104 .

The pull-up pre-driving unit 100 generates the pull-up signal PU corresponding to the input data DOUT. The pull-down pre-driving unit 102 generates the pull-down signal PD corresponding to the input data DOUT. The control unit 104 enables the pull-up and pull-down pre-driving units 100 and 102 based on the output operation mode.

The pull-up pre-driving unit 100 includes a first pull-up pre-driving block 110 and a second pull-up pre-driving block 112 . The first pull-up pre-driving block 110 includes a first PMOS transistor P 1 and a first NMOS transistor N 1 , and generates the pull-up signal PU corresponding to the input data DOUT. A gate of the first PMOS transistor P 1 and a gate of the first NMOS transistor N 1 receive the input data DOUT.

The second pull-up pre-driving block 112 includes first and second pull-up pre-drivers 112 A and 112 B, and generates the pull-up signals PU corresponding to the input data DOUT. The first and second pull-up pre-drivers 112 A and 112 B are selectively enabled in response to control signals CNT 1 and CNT 2 outputted from the control unit 104 .

The first pull-up pre-driver 112 A includes a second inverter INV 2 , second and third PMOS transistors P 2 and P 3 and second and third NMOS transistors N 2 and N 3 .

The second inverter INV 2 inverts the first control signal CNT 1 and outputs an inverted first control signal. A gate of the second PMOS transistor P 2 receives the inverted first control signal. A gate of a third PMOS transistor P 3 receives the input data DOUT. A gate of the second NMOS transistor N 3 receives the input data DOUT. A gate of the third NMOS transistor N 3 receives the first control signal CNT 1 .

The second pull-up pre-driver 112 B includes a third inverter INV 3 , fourth and fifth PMOS transistors P 4 and P 5 and fourth and fifth NMOS transistors N 4 and N 5 .

The third inverter INV 3 inverts the second control signal CNT 2 and outputs an inverted second control signal. A gate of the fourth PMOS transistor P 4 receives the inverted second control signal. A gate of the fifth PMOS transistor P 5 receives the input data DOUT. A gate of the fourth NMOS transistor N 4 receives the input data DOUT. A gate of the fifth NMOS transistor N 5 receives the second control signal CNT 2 .

The pull-down pre-driving unit 102 includes a first pull-down pre-driving block 116 and a second pull-down pre-driving block 118 . The first pull-down pre-driving block 116 includes a sixth PMOS transistor P 6 and a sixth NMOS transistor N 6 , and generates the pull-down signal PD corresponding to the input data DOUT. A gate of the sixth PMOS transistor P 6 receives the input data DOUT, and a gate of the sixth NMOS transistor N 6 receives the input data DOUT.

The second pull-down pre-driving block 118 includes first and second pull-down pre-drivers 118 A and 118 B, and generates the pull-up signal PD corresponding to the input data DOUT. The first and second pull-down pre-drivers 118 A and 118 B are selectively enabled in response to a control signals CNT 1 and CNT 2 outputted from the control unit 104 .

The first pull-down pre-driver 118 A receives the input data DOUT, outputs the pull-down signal PD, and is enabled by the first control signal CNT 1 . The first pull-down pre-driver 118 A includes seventh and eighth PMOS transistors P 7 and P 8 and seventh and eighth NMOS transistors N 7 and N 8 .

A gate of the seventh PMOS transistor P 7 receives the inverted first control signal from the second inverter INV 2 of a first pull-up pre-driver 112 A. A gate of the eighth NMOS transistor N 8 receives the first control signal CNT 1 .

The second pull-down pre-driver 118 B includes ninth and tenth PMOS transistors P 9 and P 10 and ninth and tenth NMOS transistors N 9 and N 10 . The second pull-down pre-driver 118 B receives the input data DOUT, outputs the pull-down signal PD, and is enabled by the second control signal CNT 2 .

A gate of the ninth PMOS transistor P 9 receives the inverted second control signal from the third inverter INV 3 of the second pull-up pre-driver 112 B. A gate of the tenth PMOS transistor P 10 receives the input data DOUT. A gate of the ninth NMOS transistor N 9 receives the input data DOUT. A gate of the tenth NMOS transistor N 10 receives the second control signal CNT 2 .

The control unit 104 generates the first control signal CNT 1 corresponding to the second and third output operation modes, and second control signal CNT 2 corresponding to the third output operation mode. The control unit 104 includes a NOR gate NR 1 for receiving the second and third output operation mode signals ×8 and ×16, and a first inverter INV 1 for receiving an output of the NOR gate NR 1 , and for outputting the first control signal CNT 1 .

The output driving unit 20 includes a first driving unit 200 for generating the output data DQ in response to the pull-up signal PU, and a second driving unit 202 for generating the output data DQ in response to the pull-down signal PD.

The first driving unit 200 includes an eleventh PMOS transistor P 11 , and the second driving unit 202 includes an eleventh NMOS transistor N 11 . A gate of the eleventh PMOS transistor P 11 receives the pull-up signal PU, and a gate of the eleventh NMOS transistor N 11 receives the pull-down signal PD.

The operation of output circuit will be described hereinafter in detail.

It is assumed that the semiconductor device operates in ×4 operation mode, the control unit 104 generates the first control signal CNT 1 inactivated, and the second control signal CNT 2 inactivated. That is, the first and second control signals CNT 1 and CNT 2 have a logic ‘low’ level. Thus, the first and second pull-up pre-drivers 112 A and 112 B, and the first and second pull-down pre-drivers 118 A and 118 B are disabled in response to the first and second control signals CNT 1 and CNT 2 inactivated. Therefore, the first pull-up pre-driving block 110 and the first pull-down pre-driving block 116 are only enabled, and output the pull-up and pull-down signals PU and PD. That is, the pull-up and pull-down signals PU and PD are generated by using the driving power of the first pull-up pre-driving block 110 and the first pull-down pre-driving block 116 . Thus, the output driving unit 20 receives the pull-up and pull-down signals PU and PD, and generates the output data DQ. The output data DQ is transferred to an output pad.

It is assumed that the semiconductor device operates in ×8 operation mode, the control unit 104 generates the first control signal CNT 1 activated, and the second control signal CNT 2 inactivated. That is, the first control signal CNT 1 has a logic ‘high’ level, and the second control signal CNT 2 has a logic ‘low’ level. Thus, the first pull-up pre-driver 112 A and the first pull-down pre-driver 118 A are enabled in response to the first control signal CNT 1 activated, and the second pull-up pre-driver 112 B and the second pull-down pre-driver 118 B are disabled in response to the second control signal CNT 2 inactivated. Accordingly, the first pull-up pre-driving block 110 , the first pull-up pre-driver 112 A, the first pull-down pre-driving block 116 , and the first pull-down pre-driver 118 A are enabled, and output the pull-up and pull-down signals PU and PD. That is, the pull-up and pull-down signals PU and PD are generated by using driving power of the first pull-up pre-driving block 110 , the first pull-up pre-driver 112 A, the first pull-down pre-driving block 116 , and the first pull-down pre-driver 118 A. Thus, the output driving unit 20 receives the pull-up and pull-down signals PU and PD, and generates the output data DQ. The output data DQ is transferred to an output pad.

It is assumed that the semiconductor device operates in ×16 operation mode, the control unit 104 generates the first control signal CNT 1 activated, and the second control signal CNT 2 activated. That is, the first control signal CNT 1 has a logic ‘high’ level, and the second control signal CNT 2 has a logic ‘high’ level. Thus, the first pull-up pre-driver 112 A and the first pull-down pre-driver 118 A are enabled by the first control signal CNT 1 activated, and the second pull-up pre-driver 112 B and the second pull-down pre-driver 118 B are enabled in response to the second control signal CNT 2 activated. Accordingly, the first pull-up pre-driving block 110 , the first pull-up pre-driver 112 A, the second pull-up pre-driver 112 B, the first pull-down pre-driving block 116 , the first pull-down pre-driver 118 A, and second pull-down pre-driver 118 B are enabled, and output the pull-up and pull-down signals PU and PD. That is, the pull-up and pull-down signals PU and PD are generated by using the driving power of the first pull-up pre-driving block 110 , the first pull-up pre-driver 112 A, the second pull-up pre-driver 112 B, the first pull-down pre-driving block 116 , the first pull-down pre-driver 118 A, and the second pull-down pre-driver 118 B. Thus, the output driving unit 20 receives the pull-up and pull-down signals PU and PD, and generates the output data DQ. The output data DQ is transferred to an output pad.

FIG. 4 is a timing diagram illustrating the operation of the output circuit shown in FIG. 2 .

Referring to FIG. 4 , when the number of the output circuits satisfies the conditions for ×4, ×8 and ×16 operation modes of the semiconductor device, the slew rates of data is same during all operation modes. Thus, even though the output circuit is designed according to the slew rate of data corresponding to ×16 operation mode, when the semiconductor device is operated in ×4 or ×8 operation mode, the semiconductor device does not consume an operation current excessively.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.