Embedded bridge rectifier integrated with configurable I/O pads

This application claims the benefit of the filing date of Taiwan Application Ser. No. 097123439, filed on Jun. 24, 2008, the content of which is incorporated herein by reference.

1. Field of the Invention

The invention relates to semiconductor devices, particularly to a bridge rectifier embedded in an integrated circuit (IC), into which internal pads and an external bridge rectifier are integrated.

2. Description of the Related Art

In addition to detecting radio signals, rectifiers are used to convert alternating current (AC) signals into direct current (DC) signals, especially converting AC power into DC power.

FIG. 1 is a circuit diagram of a conventional bridge rectifier located outside an IC. Referring FIG. 1 , a conventional bridge rectifier 100 , located outside an IC 120 , has four diodes D 1 , D 2 , D 3 and D 4 connected in a bridge arrangement to achieve full-wave rectification. A feature of the bridge rectifier 100 is that for both polarities of the input voltage (V in1 with respect to V in2 ), the polarity of the output voltage (VPX with respect to GND) is always constant. For example, when the voltage V in1 is positive with respect to the voltage V in2 , two diodes D 1 and D 3 are forward biased and then current flows along the path La. When the voltage V in1 is negative with respect to the voltage V in2 , two diodes D 2 and D 4 are forward biased and then current flows along the path Lb. As can be observed from the current paths La and Lb, the current flow through a load 120 is always in the same direction.

It is desirable to reduce hardware cost of conventional external bridge rectifiers. The invention addresses such a need.

In view of the above-mentioned problems, an object of the invention is to provide an embedded bridge rectifier, which reconfigures internal electrostatic discharge (ESD) protection circuits originally installed inside an IC, thereby saving the hardware cost of conventional external bridge rectifiers and reducing the space of print circuit boards, without adding additional components into the interior of the IC.

To achieve the above-mentioned object, the embedded bridge rectifier, applied to the interior of an integrated circuit, for receiving an input alternating current (AC) signal and generating an output direct current (DC) signal, comprising: a first PMOS transistor, the gate and the source of the first PMOS transistor being shorted together; a first NMOS transistor, the gate and the source of the first NMOS transistor being shorted together, wherein the drains of the first NMOS transistor and the first PMOS transistor are connected at a first pad of the integrated circuit; a second PMOS transistor, the gate and the source of the second PMOS transistor being shorted together, wherein the sources of the first PMOS transistor and the second PMOS transistor are connected at a first output node of the integrated circuit; and, a second NMOS transistor, the gate and the source of the second NMOS transistor being shorted together, wherein the drains of the second NMOS transistor and the second PMOS transistor are connected at a second pad of the integrated circuit and the sources of the first NMOS transistor and the second NMOS transistor are connected at a second output node of the integrated circuit; wherein the input AC signal is applied to the first pad and the second pad and the output DC signal is generated between the first output node and the second output node, and wherein the voltage of the first output node is greater than that of the second output node.

Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

FIG. 1 is a circuit diagram of a conventional bridge rectifier located outside an IC.

FIG. 2 is a circuit diagram of a conventional internal ESD protection circuit installed at a bonding pad IO.

FIG. 3 is a circuit diagram of an embedded bridge rectifier according to a first embodiment of the invention.

FIG. 4A is a circuit diagram of a conventional internal ESD protection circuit and a conventional internal output buffer installed at an output bonding pad OUT.

FIG. 4B is a circuit diagram of a conventional internal ESD protection circuit and a conventional internal input buffer installed at an input bonding pad IN 5 .

FIG. 5 is a circuit diagram of an embedded bridge rectifier according to a second embodiment of the invention.

FIG. 6 is a circuit diagram of an embedded bridge rectifier according to a third embodiment of the invention.

FIG. 7 is a circuit diagram of an embedded bridge rectifier according to a fourth embodiment of the invention.

FIG. 2 is a circuit diagram of a conventional internal ESD protection circuit installed at a bonding pad IO. ESD protection circuits are used to offer ESD protection in general ICs. When an ESD event occurs, the ESD protection circuit diverts a potentially damaging charge away from internal circuitry and protects the IC from permanent damage. Referring FIG. 2 , as can be observed from the conventional ESD protection circuit originally installed near the bonding pad IO, the gate and the source of a PMOS transistor P 1 are shorted together and the gate and the source of a NMOS transistor N 1 are shorted together. Both transistors P 1 and N 1 are substantially equivalent to two diodes connected in series.

FIG. 3 is a circuit diagram of an embedded bridge rectifier according to a first embodiment of the invention. As shown in FIG. 3 , an internal ESD protection circuit originally installed at a bonding pad IO 1 includes a PMOS transistor P 11 and a NMOS transistor N 11 ; another internal ESD protection circuit originally installed at a bonding pad IO 2 includes a PMOS transistor P 21 and a NMOS transistor N 21 . According to the invention, the two ESD protection circuits originally installed at two bonding pads IO 1 and IO 2 are reconfigured and reconnected. That is, the sources of the PMOS transistors P 21 and P 11 are shorted together and the sources of the NMOS transistors N 21 and N 11 are shorted together. Consequently, an embedded bridge rectifier 300 of the invention is formed. Comparing FIGS. 1 and 3 , the PMOS transistor P 11 is equivalent to the diode D 1 ; the PMOS transistor P 21 is equivalent to the diode D 2 ; the NMOS transistor N 11 is equivalent to the diode D 4 ; the NMOS transistor N 21 is equivalent to the diode D 3 . Thus, an input signal that is originally applied to two input terminals of the conventional bridge rectifier 100 can be directly fed into the IC (the two bonding pads IO 1 and IO 2 ) instead. In comparison to conventional external bridge rectifiers, conventional external components are allowed to be discarded and the hardware cost and the space of the printed circuit board are saved in the first embodiment of the invention. Certainly, the output rectified voltage VDD of the embedded bridge rectifier 300 can directly or indirectly serve as a power supply for the use of the IC. For example, the output rectified voltage VDD can be reduced by a regulator to a desired voltage level VDDL for use.

It should be noted that the embedded bridge rectifier of the invention making use of the bonding pads and the ESD protection circuits do not conflict with the common input/output signal applications. The reasons are as follows. First, when the bonding pads and the ESD protection circuits used in the embedded bridge rectifier of the invention, the voltage VDD is not connected to any power supply, but receives the AC signal or the AC power fed into the two bonding pads IO 1 and IO 2 instead; in contrast, in the common input/output signal applications, the voltage VDD needs to be connected to a power supply. Secondly, in the embedded bridge rectifier of the invention, one of the voltages at the bonding pads IO 1 and IO 2 has to be greater than the voltage VDD in order to turn on diodes; in contrast, in the common input/output signal applications, both the voltages at the bonding pads IO 1 and IO 2 are less than or equal to the voltage VDD. Thirdly, in the embedded bridge rectifier of the invention, the polarities of the voltages of the bonding pads IO 1 and IO 2 are reversed to each other; in contrast, in the common input/output signal applications, each polarity of two voltages at the bonding pads IO 1 and IO 2 depends on its own application. Accordingly, depending on functional requirements, related circuit configurations can be modified to develop various applications.

FIG. 4A is a circuit diagram of a conventional internal ESD protection circuit and a conventional internal output buffer installed at an output bonding pad OUT. Referring to FIG. 4A , an output bonding pad OUT is typically connected with an ESD protection circuit 410 and an output buffer 420 . In the output buffer 420 , a PMOS transistor P 12 and a NMOS transistor N 12 are responsive to two control signals Dx and Dy, respectively. When the control signal Dx is at a logic high voltage level (VDD) and the control signal Dy is at a logic low voltage level (GND) (indicating that the output buffer 420 is disabled), the operable ESD protection circuit 410 is equivalent to the circuit of FIG. 2 . In other words, in connection with the embedded bridge rectifier 300 of the invention, either or both of the bonding pads IO 1 and IO 2 can be replaced with the output bonding pad OUT connected to its ESD protection circuit 410 and its disabled output buffer 420 . FIG. 4B is a circuit diagram of a conventional internal ESD protection circuit and a conventional internal input buffer installed at an input bonding pad IN 5 . Referring to FIG. 4B , an input bonding pad IN 5 is typically connected with an ESD protection circuit 410 and an input buffer 430 . The input buffer 430 is responsive to a control signals Dz. When the control signal Dz is disabled (indicating that the input buffer 430 is also disabled), the operable ESD protection circuit 410 is equivalent to the circuit of FIG. 2 . In other words, in connection with the embedded bridge rectifier 300 of the invention, either or both of the bonding pads IO 1 and IO 2 can be replaced with the input bonding pad IN 5 connected to its ESD protection circuit 410 and its disabled input buffer 430 .

FIG. 5 is a circuit diagram of an embedded bridge rectifier according to a second embodiment of the invention. Referring to FIG. 5 , a first internal ESD protection circuit originally installed at an output bonding pad OUT 1 includes the PMOS transistor P 11 and the NMOS transistor N 11 and a first internal output buffer originally installed at the output bonding pad OUT 1 includes the PMOS transistor P 12 and the NMOS transistor N 12 . A second internal ESD protection circuit originally installed at an output bonding pad OUT 2 includes a PMOS transistor P 21 and a NMOS transistor N 21 and a second internal output buffer originally installed at the output bonding pad OUT 2 includes a PMOS transistor P 22 and a NMOS transistor N 22 . According to the invention, the two ESD protection circuits and the two output buffers originally installed at two output bonding pad OUT 1 and OUT 2 are reconfigured and reconnected. Consequently, an embedded bridge rectifier 500 of the invention is formed. Here, the gates of transistors P 12 and N 12 are connected at a node DO 1 and simultaneously connected to the output bonding pad OUT 2 (represented in dotted lines). The gates of transistors P 22 and N 22 are connected at a node DO 2 and simultaneously connected to the output bonding pad OUT 1 (represented in dotted lines). The operations of the embedded bridge rectifier 500 will be described in detail as follows.

Two input terminals (i.e., the output bonding pads OUT 1 and OUT 2 ) of the embedded bridge rectifier 500 receives an input AC signal, so the polarities of the voltages of the bonding pads OUT 1 and OUT 2 are reversed to each other. When the voltage at the bonding pad OUT 1 is positive with respect to the voltage at the bonding pad OUT 2 , the transistor P 12 is turned on and the transistor N 12 is turned off since V DO1 =V OUT2 =L. In contrast, since V OUT =V DO2 =H, the transistor P 22 is turned off and the transistor N 22 is turned on; thus, the current will take the path of lower resistance, i.e., along the path Lc, through the load 510 and along the path Ld, without passing through the transistors P 12 and N 21 (with higher resistance). On the contrary, when the voltage of the bonding pad OUT 1 is negative with respect to the voltage of the bonding pad OUT 2 , the transistor P 12 is turned off and the transistor N 12 is turned on since V DO1 =V OUT2 =H. In contrast, since V OUT1 =V DO2 =L, the transistor P 22 is turned on and the transistor N 22 is turned off; thus, the current will take the path of lower resistance, i.e., along the path Le, through the load 510 and along the path Lf, without passing through the transistors P 21 and N 11 (with higher resistance). As can be observed from the rectified current paths, although the polarities of the voltages of two input terminals of the embedded bridge rectifier 500 change, the polarities (VDD with respect to GND) of the two voltages of two output terminals remain constant.

Further, in each of the conventional bridge rectifier 100 and the embedded bridge rectifier 300 , there is a voltage drop of around 2×Vt (around 2×0.6 V) in the output voltage swing at its output terminals. In the second embodiment, the current takes the path through the conducted MOS transistors (P 12 & N 22 , or P 22 & N 12 ) rather than the path through the transistors (P 11 , N 11 , P 21 , N 21 ) configured as diodes. Although there is a voltage drop of around 0.1 V across a conducted MOS transistor (the voltage drop is varied depending on the size of the MOS transistor), the output voltage swing at the output terminals of the embedded bridge rectifier 500 is much close to its input voltage swing.

On the other hand, the frequency of a normal AC signal is not necessarily constant. When an input AC signal is applied to two input terminals (the output bonding pads OUT 1 and OUT 2 ) of the embedded bridge rectifier 500 , if the output DC signal (VDD with respect to GND) serves as a power supply, the frequency of the input AC signal will disappear. To solve this problem, an inverter or a level shifter is provided to connect with one of two input terminals of the embedded bridge rectifier 500 for obtaining an output AC signal which has the same frequency as the input AC signal but has a reversed polarity. The obtained output AC signal with the same frequency as the input AC signal will be supplied to the following stage circuit for demodulation. Instead, two inverters or two level shifters can be provided to connect with the two input terminals respectively. Then, depending on circuit applications, one or two output AC signal(s) of either the two inverters or the two level shifters can be used for demodulation. FIG. 6 is a circuit diagram of an embedded bridge rectifier according to a third embodiment of the invention. Comparing FIGS. 3 and 6 , the differences are that the bonding pads IO 1 and IO 2 are replaced with input bonding pads IN 1 and IN 2 and their corresponding two input buffers 601 and 602 are configured as inverters. FIG. 7 is a circuit diagram of an embedded bridge rectifier according to a fourth embodiment of the invention. Comparing FIGS. 5 and 7 , the differences are that the output bonding pad OUT 1 is replaced with an input/output bonding pad IO 4 and its corresponding input buffers 701 is configured as an inverter. The embedded bridge rectifier 700 is formed by reconfiguring and reconnecting two ESD protection circuits, an input buffer and two output buffers originally installed at an input/output bonding pad IO 4 and the output bonding pad OUT 2 respectively.

Referring to FIG. 6 , since the rectified voltage VDD may directly or indirectly serve as a power supply, the rectified voltage VDD may be greater than or equal to the operating voltages VDDL of the inverters 601 and 602 . For example, if with regulation, the output rectified voltage VDD will be reduced to the operating voltage VDDL by a regulator (not shown). Contrarily, if without regulation, the output rectified voltage VDD will be equal to the operating voltage VDDL. Besides, depending on circuit functional requirements, both or one of two output AC signals DA 1 and DA 2 of the inverters 601 and 602 can be supplied to the following stage circuit for demodulation. Referring to FIG. 7 , only the output AC signal DA 3 of the inverter 701 is supplied to the following stage circuit for demodulation. In summary, in each of the embedded bridge rectifiers 600 and 700 , the correct frequency of the input AC signal (applied to the pads IN 3 , IN 4 and IO 4 ) is obtained and the voltage level of the output DC signal (VDD is reduced to VDDL) is able to be adjusted, thereby achieving signal rectification, frequency demodulation and voltage level adjustment.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.